clock-g12a.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 - AmLogic, Inc.
  4. * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  5. * Copyright 2018 - BayLibre, SAS
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #ifndef _ARCH_MESON_CLOCK_G12A_H_
  9. #define _ARCH_MESON_CLOCK_G12A_H_
  10. /*
  11. * Clock controller register offsets
  12. *
  13. * Register offsets from the data sheet are listed in comment blocks below.
  14. * Those offsets must be multiplied by 4 before adding them to the base address
  15. * to get the right value
  16. */
  17. #define HHI_MIPI_CNTL0 0x000
  18. #define HHI_MIPI_CNTL1 0x004
  19. #define HHI_MIPI_CNTL2 0x008
  20. #define HHI_MIPI_STS 0x00C
  21. #define HHI_GP0_PLL_CNTL0 0x040
  22. #define HHI_GP0_PLL_CNTL1 0x044
  23. #define HHI_GP0_PLL_CNTL2 0x048
  24. #define HHI_GP0_PLL_CNTL3 0x04C
  25. #define HHI_GP0_PLL_CNTL4 0x050
  26. #define HHI_GP0_PLL_CNTL5 0x054
  27. #define HHI_GP0_PLL_CNTL6 0x058
  28. #define HHI_GP0_PLL_STS 0x05C
  29. #define HHI_PCIE_PLL_CNTL0 0x098
  30. #define HHI_PCIE_PLL_CNTL1 0x09C
  31. #define HHI_PCIE_PLL_CNTL2 0x0A0
  32. #define HHI_PCIE_PLL_CNTL3 0x0A4
  33. #define HHI_PCIE_PLL_CNTL4 0x0A8
  34. #define HHI_PCIE_PLL_CNTL5 0x0AC
  35. #define HHI_PCIE_PLL_STS 0x0B8
  36. #define HHI_HIFI_PLL_CNTL0 0x0D8
  37. #define HHI_HIFI_PLL_CNTL1 0x0DC
  38. #define HHI_HIFI_PLL_CNTL2 0x0E0
  39. #define HHI_HIFI_PLL_CNTL3 0x0E4
  40. #define HHI_HIFI_PLL_CNTL4 0x0E8
  41. #define HHI_HIFI_PLL_CNTL5 0x0EC
  42. #define HHI_HIFI_PLL_CNTL6 0x0F0
  43. #define HHI_VIID_CLK_DIV 0x128
  44. #define HHI_VIID_CLK_CNTL 0x12C
  45. #define HHI_GCLK_MPEG0 0x140
  46. #define HHI_GCLK_MPEG1 0x144
  47. #define HHI_GCLK_MPEG2 0x148
  48. #define HHI_GCLK_OTHER 0x150
  49. #define HHI_GCLK_OTHER2 0x154
  50. #define HHI_VID_CLK_DIV 0x164
  51. #define HHI_MPEG_CLK_CNTL 0x174
  52. #define HHI_AUD_CLK_CNTL 0x178
  53. #define HHI_VID_CLK_CNTL 0x17c
  54. #define HHI_TS_CLK_CNTL 0x190
  55. #define HHI_VID_CLK_CNTL2 0x194
  56. #define HHI_SYS_CPU_CLK_CNTL0 0x19c
  57. #define HHI_VID_PLL_CLK_DIV 0x1A0
  58. #define HHI_MALI_CLK_CNTL 0x1b0
  59. #define HHI_VPU_CLKC_CNTL 0x1b4
  60. #define HHI_VPU_CLK_CNTL 0x1bC
  61. #define HHI_HDMI_CLK_CNTL 0x1CC
  62. #define HHI_VDEC_CLK_CNTL 0x1E0
  63. #define HHI_VDEC2_CLK_CNTL 0x1E4
  64. #define HHI_VDEC3_CLK_CNTL 0x1E8
  65. #define HHI_VDEC4_CLK_CNTL 0x1EC
  66. #define HHI_HDCP22_CLK_CNTL 0x1F0
  67. #define HHI_VAPBCLK_CNTL 0x1F4
  68. #define HHI_VPU_CLKB_CNTL 0x20C
  69. #define HHI_GEN_CLK_CNTL 0x228
  70. #define HHI_VDIN_MEAS_CLK_CNTL 0x250
  71. #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
  72. #define HHI_NAND_CLK_CNTL 0x25C
  73. #define HHI_SD_EMMC_CLK_CNTL 0x264
  74. #define HHI_MPLL_CNTL0 0x278
  75. #define HHI_MPLL_CNTL1 0x27C
  76. #define HHI_MPLL_CNTL2 0x280
  77. #define HHI_MPLL_CNTL3 0x284
  78. #define HHI_MPLL_CNTL4 0x288
  79. #define HHI_MPLL_CNTL5 0x28c
  80. #define HHI_MPLL_CNTL6 0x290
  81. #define HHI_MPLL_CNTL7 0x294
  82. #define HHI_MPLL_CNTL8 0x298
  83. #define HHI_FIX_PLL_CNTL0 0x2A0
  84. #define HHI_FIX_PLL_CNTL1 0x2A4
  85. #define HHI_FIX_PLL_CNTL3 0x2AC
  86. #define HHI_SYS_PLL_CNTL0 0x2f4
  87. #define HHI_SYS_PLL_CNTL1 0x2f8
  88. #define HHI_SYS_PLL_CNTL2 0x2fc
  89. #define HHI_SYS_PLL_CNTL3 0x300
  90. #define HHI_SYS_PLL_CNTL4 0x304
  91. #define HHI_SYS_PLL_CNTL5 0x308
  92. #define HHI_SYS_PLL_CNTL6 0x30c
  93. #define HHI_HDMI_PLL_CNTL0 0x320
  94. #define HHI_HDMI_PLL_CNTL1 0x324
  95. #define HHI_HDMI_PLL_CNTL2 0x328
  96. #define HHI_HDMI_PLL_CNTL3 0x32c
  97. #define HHI_HDMI_PLL_CNTL4 0x330
  98. #define HHI_HDMI_PLL_CNTL5 0x334
  99. #define HHI_HDMI_PLL_CNTL6 0x338
  100. #define HHI_SPICC_CLK_CNTL 0x3dc
  101. #endif