clock-axg.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 - AmLogic, Inc.
  4. * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  5. * Copyright 2018 - BayLibre, SAS
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #ifndef _ARCH_MESON_CLOCK_AXG_H_
  9. #define _ARCH_MESON_CLOCK_AXG_H_
  10. /*
  11. * Clock controller register offsets
  12. *
  13. * Register offsets from the data sheet are listed in comment blocks below.
  14. * Those offsets must be multiplied by 4 before adding them to the base address
  15. * to get the right value
  16. */
  17. #define HHI_GP0_PLL_CNTL 0x40
  18. #define HHI_GP0_PLL_CNTL2 0x44
  19. #define HHI_GP0_PLL_CNTL3 0x48
  20. #define HHI_GP0_PLL_CNTL4 0x4c
  21. #define HHI_GP0_PLL_CNTL5 0x50
  22. #define HHI_GP0_PLL_STS 0x54
  23. #define HHI_GP0_PLL_CNTL1 0x58
  24. #define HHI_HIFI_PLL_CNTL 0x80
  25. #define HHI_HIFI_PLL_CNTL2 0x84
  26. #define HHI_HIFI_PLL_CNTL3 0x88
  27. #define HHI_HIFI_PLL_CNTL4 0x8C
  28. #define HHI_HIFI_PLL_CNTL5 0x90
  29. #define HHI_HIFI_PLL_STS 0x94
  30. #define HHI_HIFI_PLL_CNTL1 0x98
  31. #define HHI_XTAL_DIVN_CNTL 0xbc
  32. #define HHI_GCLK2_MPEG0 0xc0
  33. #define HHI_GCLK2_MPEG1 0xc4
  34. #define HHI_GCLK2_MPEG2 0xc8
  35. #define HHI_GCLK2_OTHER 0xd0
  36. #define HHI_GCLK2_AO 0xd4
  37. #define HHI_PCIE_PLL_CNTL 0xd8
  38. #define HHI_PCIE_PLL_CNTL1 0xdC
  39. #define HHI_PCIE_PLL_CNTL2 0xe0
  40. #define HHI_PCIE_PLL_CNTL3 0xe4
  41. #define HHI_PCIE_PLL_CNTL4 0xe8
  42. #define HHI_PCIE_PLL_CNTL5 0xec
  43. #define HHI_PCIE_PLL_CNTL6 0xf0
  44. #define HHI_PCIE_PLL_STS 0xf4
  45. #define HHI_MEM_PD_REG0 0x100
  46. #define HHI_VPU_MEM_PD_REG0 0x104
  47. #define HHI_VIID_CLK_DIV 0x128
  48. #define HHI_VIID_CLK_CNTL 0x12c
  49. #define HHI_GCLK_MPEG0 0x140
  50. #define HHI_GCLK_MPEG1 0x144
  51. #define HHI_GCLK_MPEG2 0x148
  52. #define HHI_GCLK_OTHER 0x150
  53. #define HHI_GCLK_AO 0x154
  54. #define HHI_SYS_CPU_CLK_CNTL1 0x15c
  55. #define HHI_SYS_CPU_RESET_CNTL 0x160
  56. #define HHI_VID_CLK_DIV 0x164
  57. #define HHI_SPICC_HCLK_CNTL 0x168
  58. #define HHI_MPEG_CLK_CNTL 0x174
  59. #define HHI_VID_CLK_CNTL 0x17c
  60. #define HHI_TS_CLK_CNTL 0x190
  61. #define HHI_VID_CLK_CNTL2 0x194
  62. #define HHI_SYS_CPU_CLK_CNTL0 0x19c
  63. #define HHI_VID_PLL_CLK_DIV 0x1a0
  64. #define HHI_VPU_CLK_CNTL 0x1bC
  65. #define HHI_VAPBCLK_CNTL 0x1F4
  66. #define HHI_GEN_CLK_CNTL 0x228
  67. #define HHI_VDIN_MEAS_CLK_CNTL 0x250
  68. #define HHI_NAND_CLK_CNTL 0x25C
  69. #define HHI_SD_EMMC_CLK_CNTL 0x264
  70. #define HHI_MPLL_CNTL 0x280
  71. #define HHI_MPLL_CNTL2 0x284
  72. #define HHI_MPLL_CNTL3 0x288
  73. #define HHI_MPLL_CNTL4 0x28C
  74. #define HHI_MPLL_CNTL5 0x290
  75. #define HHI_MPLL_CNTL6 0x294
  76. #define HHI_MPLL_CNTL7 0x298
  77. #define HHI_MPLL_CNTL8 0x29C
  78. #define HHI_MPLL_CNTL9 0x2A0
  79. #define HHI_MPLL_CNTL10 0x2A4
  80. #define HHI_MPLL3_CNTL0 0x2E0
  81. #define HHI_MPLL3_CNTL1 0x2E4
  82. #define HHI_PLL_TOP_MISC 0x2E8
  83. #define HHI_SYS_PLL_CNTL1 0x2FC
  84. #define HHI_SYS_PLL_CNTL 0x300
  85. #define HHI_SYS_PLL_CNTL2 0x304
  86. #define HHI_SYS_PLL_CNTL3 0x308
  87. #define HHI_SYS_PLL_CNTL4 0x30c
  88. #define HHI_SYS_PLL_CNTL5 0x310
  89. #define HHI_SYS_PLL_STS 0x314
  90. #define HHI_DPLL_TOP_I 0x318
  91. #define HHI_DPLL_TOP2_I 0x31C
  92. #endif