meson-gxl.dtsi 17 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Endless Computers, Inc.
  4. * Author: Carlo Caione <carlo@endlessm.com>
  5. */
  6. #include "meson-gx.dtsi"
  7. #include <dt-bindings/clock/gxbb-clkc.h>
  8. #include <dt-bindings/clock/gxbb-aoclkc.h>
  9. #include <dt-bindings/gpio/meson-gxl-gpio.h>
  10. #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  11. / {
  12. compatible = "amlogic,meson-gxl";
  13. soc {
  14. usb: usb@d0078080 {
  15. compatible = "amlogic,meson-gxl-usb-ctrl";
  16. reg = <0x0 0xd0078080 0x0 0x20>;
  17. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. ranges;
  21. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
  22. clock-names = "usb_ctrl", "ddr";
  23. resets = <&reset RESET_USB_OTG>;
  24. dr_mode = "otg";
  25. phys = <&usb2_phy0>, <&usb2_phy1>;
  26. phy-names = "usb2-phy0", "usb2-phy1";
  27. dwc2: usb@c9100000 {
  28. compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
  29. reg = <0x0 0xc9100000 0x0 0x40000>;
  30. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  31. clocks = <&clkc CLKID_USB1>;
  32. clock-names = "otg";
  33. phys = <&usb2_phy1>;
  34. dr_mode = "peripheral";
  35. g-rx-fifo-size = <192>;
  36. g-np-tx-fifo-size = <128>;
  37. g-tx-fifo-size = <128 128 16 16 16>;
  38. };
  39. dwc3: usb@c9000000 {
  40. compatible = "snps,dwc3";
  41. reg = <0x0 0xc9000000 0x0 0x100000>;
  42. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  43. dr_mode = "host";
  44. maximum-speed = "high-speed";
  45. snps,dis_u2_susphy_quirk;
  46. };
  47. };
  48. acodec: audio-controller@c8832000 {
  49. compatible = "amlogic,t9015";
  50. reg = <0x0 0xc8832000 0x0 0x14>;
  51. #sound-dai-cells = <0>;
  52. sound-name-prefix = "ACODEC";
  53. clocks = <&clkc CLKID_ACODEC>;
  54. clock-names = "pclk";
  55. resets = <&reset RESET_ACODEC>;
  56. status = "disabled";
  57. };
  58. crypto: crypto@c883e000 {
  59. compatible = "amlogic,gxl-crypto";
  60. reg = <0x0 0xc883e000 0x0 0x36>;
  61. interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
  62. <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  63. clocks = <&clkc CLKID_BLKMV>;
  64. clock-names = "blkmv";
  65. status = "okay";
  66. };
  67. };
  68. };
  69. &aiu {
  70. compatible = "amlogic,aiu-gxl", "amlogic,aiu";
  71. clocks = <&clkc CLKID_AIU_GLUE>,
  72. <&clkc CLKID_I2S_OUT>,
  73. <&clkc CLKID_AOCLK_GATE>,
  74. <&clkc CLKID_CTS_AMCLK>,
  75. <&clkc CLKID_MIXER_IFACE>,
  76. <&clkc CLKID_IEC958>,
  77. <&clkc CLKID_IEC958_GATE>,
  78. <&clkc CLKID_CTS_MCLK_I958>,
  79. <&clkc CLKID_CTS_I958>;
  80. clock-names = "pclk",
  81. "i2s_pclk",
  82. "i2s_aoclk",
  83. "i2s_mclk",
  84. "i2s_mixer",
  85. "spdif_pclk",
  86. "spdif_aoclk",
  87. "spdif_mclk",
  88. "spdif_mclk_sel";
  89. resets = <&reset RESET_AIU>;
  90. };
  91. &apb {
  92. usb2_phy0: phy@78000 {
  93. compatible = "amlogic,meson-gxl-usb2-phy";
  94. #phy-cells = <0>;
  95. reg = <0x0 0x78000 0x0 0x20>;
  96. clocks = <&clkc CLKID_USB>;
  97. clock-names = "phy";
  98. resets = <&reset RESET_USB_OTG>;
  99. reset-names = "phy";
  100. status = "okay";
  101. };
  102. usb2_phy1: phy@78020 {
  103. compatible = "amlogic,meson-gxl-usb2-phy";
  104. #phy-cells = <0>;
  105. reg = <0x0 0x78020 0x0 0x20>;
  106. clocks = <&clkc CLKID_USB>;
  107. clock-names = "phy";
  108. resets = <&reset RESET_USB_OTG>;
  109. reset-names = "phy";
  110. status = "okay";
  111. };
  112. };
  113. &efuse {
  114. clocks = <&clkc CLKID_EFUSE>;
  115. };
  116. &ethmac {
  117. clocks = <&clkc CLKID_ETH>,
  118. <&clkc CLKID_FCLK_DIV2>,
  119. <&clkc CLKID_MPLL2>;
  120. clock-names = "stmmaceth", "clkin0", "clkin1";
  121. mdio0: mdio {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. compatible = "snps,dwmac-mdio";
  125. };
  126. };
  127. &aobus {
  128. pinctrl_aobus: pinctrl@14 {
  129. compatible = "amlogic,meson-gxl-aobus-pinctrl";
  130. #address-cells = <2>;
  131. #size-cells = <2>;
  132. ranges;
  133. gpio_ao: bank@14 {
  134. reg = <0x0 0x00014 0x0 0x8>,
  135. <0x0 0x0002c 0x0 0x4>,
  136. <0x0 0x00024 0x0 0x8>;
  137. reg-names = "mux", "pull", "gpio";
  138. gpio-controller;
  139. #gpio-cells = <2>;
  140. gpio-ranges = <&pinctrl_aobus 0 0 14>;
  141. };
  142. uart_ao_a_pins: uart_ao_a {
  143. mux {
  144. groups = "uart_tx_ao_a", "uart_rx_ao_a";
  145. function = "uart_ao";
  146. bias-disable;
  147. };
  148. };
  149. uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  150. mux {
  151. groups = "uart_cts_ao_a",
  152. "uart_rts_ao_a";
  153. function = "uart_ao";
  154. bias-disable;
  155. };
  156. };
  157. uart_ao_b_pins: uart_ao_b {
  158. mux {
  159. groups = "uart_tx_ao_b", "uart_rx_ao_b";
  160. function = "uart_ao_b";
  161. bias-disable;
  162. };
  163. };
  164. uart_ao_b_0_1_pins: uart_ao_b_0_1 {
  165. mux {
  166. groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
  167. function = "uart_ao_b";
  168. bias-disable;
  169. };
  170. };
  171. uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
  172. mux {
  173. groups = "uart_cts_ao_b",
  174. "uart_rts_ao_b";
  175. function = "uart_ao_b";
  176. bias-disable;
  177. };
  178. };
  179. remote_input_ao_pins: remote_input_ao {
  180. mux {
  181. groups = "remote_input_ao";
  182. function = "remote_input_ao";
  183. bias-disable;
  184. };
  185. };
  186. i2c_ao_pins: i2c_ao {
  187. mux {
  188. groups = "i2c_sck_ao",
  189. "i2c_sda_ao";
  190. function = "i2c_ao";
  191. bias-disable;
  192. };
  193. };
  194. pwm_ao_a_3_pins: pwm_ao_a_3 {
  195. mux {
  196. groups = "pwm_ao_a_3";
  197. function = "pwm_ao_a";
  198. bias-disable;
  199. };
  200. };
  201. pwm_ao_a_8_pins: pwm_ao_a_8 {
  202. mux {
  203. groups = "pwm_ao_a_8";
  204. function = "pwm_ao_a";
  205. bias-disable;
  206. };
  207. };
  208. pwm_ao_b_pins: pwm_ao_b {
  209. mux {
  210. groups = "pwm_ao_b";
  211. function = "pwm_ao_b";
  212. bias-disable;
  213. };
  214. };
  215. pwm_ao_b_6_pins: pwm_ao_b_6 {
  216. mux {
  217. groups = "pwm_ao_b_6";
  218. function = "pwm_ao_b";
  219. bias-disable;
  220. };
  221. };
  222. i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
  223. mux {
  224. groups = "i2s_out_ch23_ao";
  225. function = "i2s_out_ao";
  226. bias-disable;
  227. };
  228. };
  229. i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
  230. mux {
  231. groups = "i2s_out_ch45_ao";
  232. function = "i2s_out_ao";
  233. bias-disable;
  234. };
  235. };
  236. spdif_out_ao_6_pins: spdif_out_ao_6 {
  237. mux {
  238. groups = "spdif_out_ao_6";
  239. function = "spdif_out_ao";
  240. bias-disable;
  241. };
  242. };
  243. spdif_out_ao_9_pins: spdif_out_ao_9 {
  244. mux {
  245. groups = "spdif_out_ao_9";
  246. function = "spdif_out_ao";
  247. bias-disable;
  248. };
  249. };
  250. ao_cec_pins: ao_cec {
  251. mux {
  252. groups = "ao_cec";
  253. function = "cec_ao";
  254. bias-disable;
  255. };
  256. };
  257. ee_cec_pins: ee_cec {
  258. mux {
  259. groups = "ee_cec";
  260. function = "cec_ao";
  261. bias-disable;
  262. };
  263. };
  264. };
  265. };
  266. &cec_AO {
  267. clocks = <&clkc_AO CLKID_AO_CEC_32K>;
  268. clock-names = "core";
  269. };
  270. &clkc_AO {
  271. compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
  272. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  273. clock-names = "xtal", "mpeg-clk";
  274. };
  275. &gpio_intc {
  276. compatible = "amlogic,meson-gpio-intc",
  277. "amlogic,meson-gxl-gpio-intc";
  278. status = "okay";
  279. };
  280. &hdmi_tx {
  281. compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
  282. resets = <&reset RESET_HDMITX_CAPB3>,
  283. <&reset RESET_HDMI_SYSTEM_RESET>,
  284. <&reset RESET_HDMI_TX>;
  285. reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  286. clocks = <&clkc CLKID_HDMI_PCLK>,
  287. <&clkc CLKID_CLK81>,
  288. <&clkc CLKID_GCLK_VENCI_INT0>;
  289. clock-names = "isfr", "iahb", "venci";
  290. };
  291. &sysctrl {
  292. clkc: clock-controller {
  293. compatible = "amlogic,gxl-clkc";
  294. #clock-cells = <1>;
  295. clocks = <&xtal>;
  296. clock-names = "xtal";
  297. };
  298. };
  299. &i2c_A {
  300. clocks = <&clkc CLKID_I2C>;
  301. };
  302. &i2c_AO {
  303. clocks = <&clkc CLKID_AO_I2C>;
  304. };
  305. &i2c_B {
  306. clocks = <&clkc CLKID_I2C>;
  307. };
  308. &i2c_C {
  309. clocks = <&clkc CLKID_I2C>;
  310. };
  311. &periphs {
  312. pinctrl_periphs: pinctrl@4b0 {
  313. compatible = "amlogic,meson-gxl-periphs-pinctrl";
  314. #address-cells = <2>;
  315. #size-cells = <2>;
  316. ranges;
  317. gpio: bank@4b0 {
  318. reg = <0x0 0x004b0 0x0 0x28>,
  319. <0x0 0x004e8 0x0 0x14>,
  320. <0x0 0x00520 0x0 0x14>,
  321. <0x0 0x00430 0x0 0x40>;
  322. reg-names = "mux", "pull", "pull-enable", "gpio";
  323. gpio-controller;
  324. #gpio-cells = <2>;
  325. gpio-ranges = <&pinctrl_periphs 0 0 100>;
  326. };
  327. emmc_pins: emmc {
  328. mux-0 {
  329. groups = "emmc_nand_d07",
  330. "emmc_cmd";
  331. function = "emmc";
  332. bias-pull-up;
  333. };
  334. mux-1 {
  335. groups = "emmc_clk";
  336. function = "emmc";
  337. bias-disable;
  338. };
  339. };
  340. emmc_ds_pins: emmc-ds {
  341. mux {
  342. groups = "emmc_ds";
  343. function = "emmc";
  344. bias-pull-down;
  345. };
  346. };
  347. emmc_clk_gate_pins: emmc_clk_gate {
  348. mux {
  349. groups = "BOOT_8";
  350. function = "gpio_periphs";
  351. bias-pull-down;
  352. };
  353. };
  354. nor_pins: nor {
  355. mux {
  356. groups = "nor_d",
  357. "nor_q",
  358. "nor_c",
  359. "nor_cs";
  360. function = "nor";
  361. bias-disable;
  362. };
  363. };
  364. spi_pins: spi-pins {
  365. mux {
  366. groups = "spi_miso",
  367. "spi_mosi",
  368. "spi_sclk";
  369. function = "spi";
  370. bias-disable;
  371. };
  372. };
  373. spi_ss0_pins: spi-ss0 {
  374. mux {
  375. groups = "spi_ss0";
  376. function = "spi";
  377. bias-disable;
  378. };
  379. };
  380. sdcard_pins: sdcard {
  381. mux-0 {
  382. groups = "sdcard_d0",
  383. "sdcard_d1",
  384. "sdcard_d2",
  385. "sdcard_d3",
  386. "sdcard_cmd";
  387. function = "sdcard";
  388. bias-pull-up;
  389. };
  390. mux-1 {
  391. groups = "sdcard_clk";
  392. function = "sdcard";
  393. bias-disable;
  394. };
  395. };
  396. sdcard_clk_gate_pins: sdcard_clk_gate {
  397. mux {
  398. groups = "CARD_2";
  399. function = "gpio_periphs";
  400. bias-pull-down;
  401. };
  402. };
  403. sdio_pins: sdio {
  404. mux-0 {
  405. groups = "sdio_d0",
  406. "sdio_d1",
  407. "sdio_d2",
  408. "sdio_d3",
  409. "sdio_cmd";
  410. function = "sdio";
  411. bias-pull-up;
  412. };
  413. mux-1 {
  414. groups = "sdio_clk";
  415. function = "sdio";
  416. bias-disable;
  417. };
  418. };
  419. sdio_clk_gate_pins: sdio_clk_gate {
  420. mux {
  421. groups = "GPIOX_4";
  422. function = "gpio_periphs";
  423. bias-pull-down;
  424. };
  425. };
  426. sdio_irq_pins: sdio_irq {
  427. mux {
  428. groups = "sdio_irq";
  429. function = "sdio";
  430. bias-disable;
  431. };
  432. };
  433. uart_a_pins: uart_a {
  434. mux {
  435. groups = "uart_tx_a",
  436. "uart_rx_a";
  437. function = "uart_a";
  438. bias-disable;
  439. };
  440. };
  441. uart_a_cts_rts_pins: uart_a_cts_rts {
  442. mux {
  443. groups = "uart_cts_a",
  444. "uart_rts_a";
  445. function = "uart_a";
  446. bias-disable;
  447. };
  448. };
  449. uart_b_pins: uart_b {
  450. mux {
  451. groups = "uart_tx_b",
  452. "uart_rx_b";
  453. function = "uart_b";
  454. bias-disable;
  455. };
  456. };
  457. uart_b_cts_rts_pins: uart_b_cts_rts {
  458. mux {
  459. groups = "uart_cts_b",
  460. "uart_rts_b";
  461. function = "uart_b";
  462. bias-disable;
  463. };
  464. };
  465. uart_c_pins: uart_c {
  466. mux {
  467. groups = "uart_tx_c",
  468. "uart_rx_c";
  469. function = "uart_c";
  470. bias-disable;
  471. };
  472. };
  473. uart_c_cts_rts_pins: uart_c_cts_rts {
  474. mux {
  475. groups = "uart_cts_c",
  476. "uart_rts_c";
  477. function = "uart_c";
  478. bias-disable;
  479. };
  480. };
  481. i2c_a_pins: i2c_a {
  482. mux {
  483. groups = "i2c_sck_a",
  484. "i2c_sda_a";
  485. function = "i2c_a";
  486. bias-disable;
  487. };
  488. };
  489. i2c_b_pins: i2c_b {
  490. mux {
  491. groups = "i2c_sck_b",
  492. "i2c_sda_b";
  493. function = "i2c_b";
  494. bias-disable;
  495. };
  496. };
  497. i2c_c_pins: i2c_c {
  498. mux {
  499. groups = "i2c_sck_c",
  500. "i2c_sda_c";
  501. function = "i2c_c";
  502. bias-disable;
  503. };
  504. };
  505. i2c_c_dv18_pins: i2c_c_dv18 {
  506. mux {
  507. groups = "i2c_sck_c_dv19",
  508. "i2c_sda_c_dv18";
  509. function = "i2c_c";
  510. bias-disable;
  511. };
  512. };
  513. eth_pins: eth_c {
  514. mux {
  515. groups = "eth_mdio",
  516. "eth_mdc",
  517. "eth_clk_rx_clk",
  518. "eth_rx_dv",
  519. "eth_rxd0",
  520. "eth_rxd1",
  521. "eth_rxd2",
  522. "eth_rxd3",
  523. "eth_rgmii_tx_clk",
  524. "eth_tx_en",
  525. "eth_txd0",
  526. "eth_txd1",
  527. "eth_txd2",
  528. "eth_txd3";
  529. function = "eth";
  530. bias-disable;
  531. };
  532. };
  533. eth_link_led_pins: eth_link_led {
  534. mux {
  535. groups = "eth_link_led";
  536. function = "eth_led";
  537. bias-disable;
  538. };
  539. };
  540. eth_act_led_pins: eth_act_led {
  541. mux {
  542. groups = "eth_act_led";
  543. function = "eth_led";
  544. };
  545. };
  546. pwm_a_pins: pwm_a {
  547. mux {
  548. groups = "pwm_a";
  549. function = "pwm_a";
  550. bias-disable;
  551. };
  552. };
  553. pwm_b_pins: pwm_b {
  554. mux {
  555. groups = "pwm_b";
  556. function = "pwm_b";
  557. bias-disable;
  558. };
  559. };
  560. pwm_c_pins: pwm_c {
  561. mux {
  562. groups = "pwm_c";
  563. function = "pwm_c";
  564. bias-disable;
  565. };
  566. };
  567. pwm_d_pins: pwm_d {
  568. mux {
  569. groups = "pwm_d";
  570. function = "pwm_d";
  571. bias-disable;
  572. };
  573. };
  574. pwm_e_pins: pwm_e {
  575. mux {
  576. groups = "pwm_e";
  577. function = "pwm_e";
  578. bias-disable;
  579. };
  580. };
  581. pwm_f_clk_pins: pwm_f_clk {
  582. mux {
  583. groups = "pwm_f_clk";
  584. function = "pwm_f";
  585. bias-disable;
  586. };
  587. };
  588. pwm_f_x_pins: pwm_f_x {
  589. mux {
  590. groups = "pwm_f_x";
  591. function = "pwm_f";
  592. bias-disable;
  593. };
  594. };
  595. hdmi_hpd_pins: hdmi_hpd {
  596. mux {
  597. groups = "hdmi_hpd";
  598. function = "hdmi_hpd";
  599. bias-disable;
  600. };
  601. };
  602. hdmi_i2c_pins: hdmi_i2c {
  603. mux {
  604. groups = "hdmi_sda", "hdmi_scl";
  605. function = "hdmi_i2c";
  606. bias-disable;
  607. };
  608. };
  609. i2s_am_clk_pins: i2s_am_clk {
  610. mux {
  611. groups = "i2s_am_clk";
  612. function = "i2s_out";
  613. bias-disable;
  614. };
  615. };
  616. i2s_out_ao_clk_pins: i2s_out_ao_clk {
  617. mux {
  618. groups = "i2s_out_ao_clk";
  619. function = "i2s_out";
  620. bias-disable;
  621. };
  622. };
  623. i2s_out_lr_clk_pins: i2s_out_lr_clk {
  624. mux {
  625. groups = "i2s_out_lr_clk";
  626. function = "i2s_out";
  627. bias-disable;
  628. };
  629. };
  630. i2s_out_ch01_pins: i2s_out_ch01 {
  631. mux {
  632. groups = "i2s_out_ch01";
  633. function = "i2s_out";
  634. bias-disable;
  635. };
  636. };
  637. i2sout_ch23_z_pins: i2sout_ch23_z {
  638. mux {
  639. groups = "i2sout_ch23_z";
  640. function = "i2s_out";
  641. bias-disable;
  642. };
  643. };
  644. i2sout_ch45_z_pins: i2sout_ch45_z {
  645. mux {
  646. groups = "i2sout_ch45_z";
  647. function = "i2s_out";
  648. bias-disable;
  649. };
  650. };
  651. i2sout_ch67_z_pins: i2sout_ch67_z {
  652. mux {
  653. groups = "i2sout_ch67_z";
  654. function = "i2s_out";
  655. bias-disable;
  656. };
  657. };
  658. spdif_out_h_pins: spdif_out_ao_h {
  659. mux {
  660. groups = "spdif_out_h";
  661. function = "spdif_out";
  662. bias-disable;
  663. };
  664. };
  665. };
  666. eth-phy-mux {
  667. compatible = "mdio-mux-mmioreg", "mdio-mux";
  668. #address-cells = <1>;
  669. #size-cells = <0>;
  670. reg = <0x0 0x55c 0x0 0x4>;
  671. mux-mask = <0xffffffff>;
  672. mdio-parent-bus = <&mdio0>;
  673. internal_mdio: mdio@e40908ff {
  674. reg = <0xe40908ff>;
  675. #address-cells = <1>;
  676. #size-cells = <0>;
  677. internal_phy: ethernet-phy@8 {
  678. compatible = "ethernet-phy-id0181.4400";
  679. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  680. reg = <8>;
  681. max-speed = <100>;
  682. };
  683. };
  684. external_mdio: mdio@2009087f {
  685. reg = <0x2009087f>;
  686. #address-cells = <1>;
  687. #size-cells = <0>;
  688. };
  689. };
  690. };
  691. &pwrc_vpu {
  692. resets = <&reset RESET_VIU>,
  693. <&reset RESET_VENC>,
  694. <&reset RESET_VCBUS>,
  695. <&reset RESET_BT656>,
  696. <&reset RESET_DVIN_RESET>,
  697. <&reset RESET_RDMA>,
  698. <&reset RESET_VENCI>,
  699. <&reset RESET_VENCP>,
  700. <&reset RESET_VDAC>,
  701. <&reset RESET_VDI6>,
  702. <&reset RESET_VENCL>,
  703. <&reset RESET_VID_LOCK>;
  704. clocks = <&clkc CLKID_VPU>,
  705. <&clkc CLKID_VAPB>;
  706. clock-names = "vpu", "vapb";
  707. /*
  708. * VPU clocking is provided by two identical clock paths
  709. * VPU_0 and VPU_1 muxed to a single clock by a glitch
  710. * free mux to safely change frequency while running.
  711. * Same for VAPB but with a final gate after the glitch free mux.
  712. */
  713. assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  714. <&clkc CLKID_VPU_0>,
  715. <&clkc CLKID_VPU>, /* Glitch free mux */
  716. <&clkc CLKID_VAPB_0_SEL>,
  717. <&clkc CLKID_VAPB_0>,
  718. <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  719. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  720. <0>, /* Do Nothing */
  721. <&clkc CLKID_VPU_0>,
  722. <&clkc CLKID_FCLK_DIV4>,
  723. <0>, /* Do Nothing */
  724. <&clkc CLKID_VAPB_0>;
  725. assigned-clock-rates = <0>, /* Do Nothing */
  726. <666666666>,
  727. <0>, /* Do Nothing */
  728. <0>, /* Do Nothing */
  729. <250000000>,
  730. <0>; /* Do Nothing */
  731. };
  732. &saradc {
  733. compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
  734. clocks = <&xtal>,
  735. <&clkc CLKID_SAR_ADC>,
  736. <&clkc CLKID_SAR_ADC_CLK>,
  737. <&clkc CLKID_SAR_ADC_SEL>;
  738. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  739. };
  740. &sd_emmc_a {
  741. clocks = <&clkc CLKID_SD_EMMC_A>,
  742. <&clkc CLKID_SD_EMMC_A_CLK0>,
  743. <&clkc CLKID_FCLK_DIV2>;
  744. clock-names = "core", "clkin0", "clkin1";
  745. resets = <&reset RESET_SD_EMMC_A>;
  746. };
  747. &sd_emmc_b {
  748. clocks = <&clkc CLKID_SD_EMMC_B>,
  749. <&clkc CLKID_SD_EMMC_B_CLK0>,
  750. <&clkc CLKID_FCLK_DIV2>;
  751. clock-names = "core", "clkin0", "clkin1";
  752. resets = <&reset RESET_SD_EMMC_B>;
  753. };
  754. &sd_emmc_c {
  755. clocks = <&clkc CLKID_SD_EMMC_C>,
  756. <&clkc CLKID_SD_EMMC_C_CLK0>,
  757. <&clkc CLKID_FCLK_DIV2>;
  758. clock-names = "core", "clkin0", "clkin1";
  759. resets = <&reset RESET_SD_EMMC_C>;
  760. };
  761. &simplefb_hdmi {
  762. clocks = <&clkc CLKID_HDMI_PCLK>,
  763. <&clkc CLKID_CLK81>,
  764. <&clkc CLKID_GCLK_VENCI_INT0>;
  765. };
  766. &spicc {
  767. clocks = <&clkc CLKID_SPICC>;
  768. clock-names = "core";
  769. resets = <&reset RESET_PERIPHS_SPICC>;
  770. num-cs = <1>;
  771. };
  772. &spifc {
  773. clocks = <&clkc CLKID_SPI>;
  774. };
  775. &uart_A {
  776. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  777. clock-names = "xtal", "pclk", "baud";
  778. };
  779. &uart_AO {
  780. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
  781. clock-names = "xtal", "pclk", "baud";
  782. };
  783. &uart_AO_B {
  784. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  785. clock-names = "xtal", "pclk", "baud";
  786. };
  787. &uart_B {
  788. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  789. clock-names = "xtal", "pclk", "baud";
  790. };
  791. &uart_C {
  792. clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  793. clock-names = "xtal", "pclk", "baud";
  794. };
  795. &vpu {
  796. compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
  797. power-domains = <&pwrc_vpu>;
  798. };
  799. &vdec {
  800. compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
  801. clocks = <&clkc CLKID_DOS_PARSER>,
  802. <&clkc CLKID_DOS>,
  803. <&clkc CLKID_VDEC_1>,
  804. <&clkc CLKID_VDEC_HEVC>;
  805. clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
  806. resets = <&reset RESET_PARSER>;
  807. reset-names = "esparser";
  808. };