meson-gxbb.dtsi 17 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Andreas Färber
  4. */
  5. #include "meson-gx.dtsi"
  6. #include <dt-bindings/gpio/meson-gxbb-gpio.h>
  7. #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  8. #include <dt-bindings/clock/gxbb-clkc.h>
  9. #include <dt-bindings/clock/gxbb-aoclkc.h>
  10. #include <dt-bindings/reset/gxbb-aoclkc.h>
  11. / {
  12. compatible = "amlogic,meson-gxbb";
  13. soc {
  14. usb0_phy: phy@c0000000 {
  15. compatible = "amlogic,meson-gxbb-usb2-phy";
  16. #phy-cells = <0>;
  17. reg = <0x0 0xc0000000 0x0 0x20>;
  18. resets = <&reset RESET_USB_OTG>;
  19. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
  20. clock-names = "usb_general", "usb";
  21. status = "disabled";
  22. };
  23. usb1_phy: phy@c0000020 {
  24. compatible = "amlogic,meson-gxbb-usb2-phy";
  25. #phy-cells = <0>;
  26. reg = <0x0 0xc0000020 0x0 0x20>;
  27. resets = <&reset RESET_USB_OTG>;
  28. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
  29. clock-names = "usb_general", "usb";
  30. status = "disabled";
  31. };
  32. usb0: usb@c9000000 {
  33. compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  34. reg = <0x0 0xc9000000 0x0 0x40000>;
  35. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  36. clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
  37. clock-names = "otg";
  38. phys = <&usb0_phy>;
  39. phy-names = "usb2-phy";
  40. dr_mode = "host";
  41. status = "disabled";
  42. };
  43. usb1: usb@c9100000 {
  44. compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  45. reg = <0x0 0xc9100000 0x0 0x40000>;
  46. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  47. clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  48. clock-names = "otg";
  49. phys = <&usb1_phy>;
  50. phy-names = "usb2-phy";
  51. dr_mode = "host";
  52. status = "disabled";
  53. };
  54. };
  55. };
  56. &aiu {
  57. compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
  58. clocks = <&clkc CLKID_AIU_GLUE>,
  59. <&clkc CLKID_I2S_OUT>,
  60. <&clkc CLKID_AOCLK_GATE>,
  61. <&clkc CLKID_CTS_AMCLK>,
  62. <&clkc CLKID_MIXER_IFACE>,
  63. <&clkc CLKID_IEC958>,
  64. <&clkc CLKID_IEC958_GATE>,
  65. <&clkc CLKID_CTS_MCLK_I958>,
  66. <&clkc CLKID_CTS_I958>;
  67. clock-names = "pclk",
  68. "i2s_pclk",
  69. "i2s_aoclk",
  70. "i2s_mclk",
  71. "i2s_mixer",
  72. "spdif_pclk",
  73. "spdif_aoclk",
  74. "spdif_mclk",
  75. "spdif_mclk_sel";
  76. resets = <&reset RESET_AIU>;
  77. };
  78. &aobus {
  79. pinctrl_aobus: pinctrl@14 {
  80. compatible = "amlogic,meson-gxbb-aobus-pinctrl";
  81. #address-cells = <2>;
  82. #size-cells = <2>;
  83. ranges;
  84. gpio_ao: bank@14 {
  85. reg = <0x0 0x00014 0x0 0x8>,
  86. <0x0 0x0002c 0x0 0x4>,
  87. <0x0 0x00024 0x0 0x8>;
  88. reg-names = "mux", "pull", "gpio";
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. gpio-ranges = <&pinctrl_aobus 0 0 14>;
  92. };
  93. uart_ao_a_pins: uart_ao_a {
  94. mux {
  95. groups = "uart_tx_ao_a", "uart_rx_ao_a";
  96. function = "uart_ao";
  97. bias-disable;
  98. };
  99. };
  100. uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  101. mux {
  102. groups = "uart_cts_ao_a",
  103. "uart_rts_ao_a";
  104. function = "uart_ao";
  105. bias-disable;
  106. };
  107. };
  108. uart_ao_b_pins: uart_ao_b {
  109. mux {
  110. groups = "uart_tx_ao_b", "uart_rx_ao_b";
  111. function = "uart_ao_b";
  112. bias-disable;
  113. };
  114. };
  115. uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
  116. mux {
  117. groups = "uart_cts_ao_b",
  118. "uart_rts_ao_b";
  119. function = "uart_ao_b";
  120. bias-disable;
  121. };
  122. };
  123. remote_input_ao_pins: remote_input_ao {
  124. mux {
  125. groups = "remote_input_ao";
  126. function = "remote_input_ao";
  127. bias-disable;
  128. };
  129. };
  130. i2c_ao_pins: i2c_ao {
  131. mux {
  132. groups = "i2c_sck_ao",
  133. "i2c_sda_ao";
  134. function = "i2c_ao";
  135. bias-disable;
  136. };
  137. };
  138. pwm_ao_a_3_pins: pwm_ao_a_3 {
  139. mux {
  140. groups = "pwm_ao_a_3";
  141. function = "pwm_ao_a_3";
  142. bias-disable;
  143. };
  144. };
  145. pwm_ao_a_6_pins: pwm_ao_a_6 {
  146. mux {
  147. groups = "pwm_ao_a_6";
  148. function = "pwm_ao_a_6";
  149. bias-disable;
  150. };
  151. };
  152. pwm_ao_a_12_pins: pwm_ao_a_12 {
  153. mux {
  154. groups = "pwm_ao_a_12";
  155. function = "pwm_ao_a_12";
  156. bias-disable;
  157. };
  158. };
  159. pwm_ao_b_pins: pwm_ao_b {
  160. mux {
  161. groups = "pwm_ao_b";
  162. function = "pwm_ao_b";
  163. bias-disable;
  164. };
  165. };
  166. i2s_am_clk_pins: i2s_am_clk {
  167. mux {
  168. groups = "i2s_am_clk";
  169. function = "i2s_out_ao";
  170. bias-disable;
  171. };
  172. };
  173. i2s_out_ao_clk_pins: i2s_out_ao_clk {
  174. mux {
  175. groups = "i2s_out_ao_clk";
  176. function = "i2s_out_ao";
  177. bias-disable;
  178. };
  179. };
  180. i2s_out_lr_clk_pins: i2s_out_lr_clk {
  181. mux {
  182. groups = "i2s_out_lr_clk";
  183. function = "i2s_out_ao";
  184. bias-disable;
  185. };
  186. };
  187. i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
  188. mux {
  189. groups = "i2s_out_ch01_ao";
  190. function = "i2s_out_ao";
  191. bias-disable;
  192. };
  193. };
  194. i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
  195. mux {
  196. groups = "i2s_out_ch23_ao";
  197. function = "i2s_out_ao";
  198. bias-disable;
  199. };
  200. };
  201. i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
  202. mux {
  203. groups = "i2s_out_ch45_ao";
  204. function = "i2s_out_ao";
  205. bias-disable;
  206. };
  207. };
  208. spdif_out_ao_6_pins: spdif_out_ao_6 {
  209. mux {
  210. groups = "spdif_out_ao_6";
  211. function = "spdif_out_ao";
  212. };
  213. };
  214. spdif_out_ao_13_pins: spdif_out_ao_13 {
  215. mux {
  216. groups = "spdif_out_ao_13";
  217. function = "spdif_out_ao";
  218. bias-disable;
  219. };
  220. };
  221. ao_cec_pins: ao_cec {
  222. mux {
  223. groups = "ao_cec";
  224. function = "cec_ao";
  225. bias-disable;
  226. };
  227. };
  228. ee_cec_pins: ee_cec {
  229. mux {
  230. groups = "ee_cec";
  231. function = "cec_ao";
  232. bias-disable;
  233. };
  234. };
  235. };
  236. };
  237. &apb {
  238. mali: gpu@c0000 {
  239. compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
  240. reg = <0x0 0xc0000 0x0 0x40000>;
  241. interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  242. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  243. <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  244. <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
  245. <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
  246. <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
  247. <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
  248. <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
  249. <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
  250. <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  251. interrupt-names = "gp", "gpmmu", "pp", "pmu",
  252. "pp0", "ppmmu0", "pp1", "ppmmu1",
  253. "pp2", "ppmmu2";
  254. clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
  255. clock-names = "bus", "core";
  256. /*
  257. * Mali clocking is provided by two identical clock paths
  258. * MALI_0 and MALI_1 muxed to a single clock by a glitch
  259. * free mux to safely change frequency while running.
  260. */
  261. assigned-clocks = <&clkc CLKID_GP0_PLL>,
  262. <&clkc CLKID_MALI_0_SEL>,
  263. <&clkc CLKID_MALI_0>,
  264. <&clkc CLKID_MALI>; /* Glitch free mux */
  265. assigned-clock-parents = <0>, /* Do Nothing */
  266. <&clkc CLKID_GP0_PLL>,
  267. <0>, /* Do Nothing */
  268. <&clkc CLKID_MALI_0>;
  269. assigned-clock-rates = <744000000>,
  270. <0>, /* Do Nothing */
  271. <744000000>,
  272. <0>; /* Do Nothing */
  273. };
  274. };
  275. &cbus {
  276. spifc: spi@8c80 {
  277. compatible = "amlogic,meson-gxbb-spifc";
  278. reg = <0x0 0x08c80 0x0 0x80>;
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. clocks = <&clkc CLKID_SPI>;
  282. status = "disabled";
  283. };
  284. };
  285. &cec_AO {
  286. clocks = <&clkc_AO CLKID_AO_CEC_32K>;
  287. clock-names = "core";
  288. };
  289. &clkc_AO {
  290. compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
  291. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  292. clock-names = "xtal", "mpeg-clk";
  293. };
  294. &efuse {
  295. clocks = <&clkc CLKID_EFUSE>;
  296. };
  297. &ethmac {
  298. clocks = <&clkc CLKID_ETH>,
  299. <&clkc CLKID_FCLK_DIV2>,
  300. <&clkc CLKID_MPLL2>;
  301. clock-names = "stmmaceth", "clkin0", "clkin1";
  302. };
  303. &gpio_intc {
  304. compatible = "amlogic,meson-gpio-intc",
  305. "amlogic,meson-gxbb-gpio-intc";
  306. status = "okay";
  307. };
  308. &hdmi_tx {
  309. compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
  310. resets = <&reset RESET_HDMITX_CAPB3>,
  311. <&reset RESET_HDMI_SYSTEM_RESET>,
  312. <&reset RESET_HDMI_TX>;
  313. reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  314. clocks = <&clkc CLKID_HDMI_PCLK>,
  315. <&clkc CLKID_CLK81>,
  316. <&clkc CLKID_GCLK_VENCI_INT0>;
  317. clock-names = "isfr", "iahb", "venci";
  318. };
  319. &sysctrl {
  320. clkc: clock-controller {
  321. compatible = "amlogic,gxbb-clkc";
  322. #clock-cells = <1>;
  323. clocks = <&xtal>;
  324. clock-names = "xtal";
  325. };
  326. };
  327. &hwrng {
  328. clocks = <&clkc CLKID_RNG0>;
  329. clock-names = "core";
  330. };
  331. &i2c_A {
  332. clocks = <&clkc CLKID_I2C>;
  333. };
  334. &i2c_AO {
  335. clocks = <&clkc CLKID_AO_I2C>;
  336. };
  337. &i2c_B {
  338. clocks = <&clkc CLKID_I2C>;
  339. };
  340. &i2c_C {
  341. clocks = <&clkc CLKID_I2C>;
  342. };
  343. &periphs {
  344. pinctrl_periphs: pinctrl@4b0 {
  345. compatible = "amlogic,meson-gxbb-periphs-pinctrl";
  346. #address-cells = <2>;
  347. #size-cells = <2>;
  348. ranges;
  349. gpio: bank@4b0 {
  350. reg = <0x0 0x004b0 0x0 0x28>,
  351. <0x0 0x004e8 0x0 0x14>,
  352. <0x0 0x00520 0x0 0x14>,
  353. <0x0 0x00430 0x0 0x40>;
  354. reg-names = "mux", "pull", "pull-enable", "gpio";
  355. gpio-controller;
  356. #gpio-cells = <2>;
  357. gpio-ranges = <&pinctrl_periphs 0 0 119>;
  358. };
  359. emmc_pins: emmc {
  360. mux-0 {
  361. groups = "emmc_nand_d07",
  362. "emmc_cmd";
  363. function = "emmc";
  364. bias-pull-up;
  365. };
  366. mux-1 {
  367. groups = "emmc_clk";
  368. function = "emmc";
  369. bias-disable;
  370. };
  371. };
  372. emmc_ds_pins: emmc-ds {
  373. mux {
  374. groups = "emmc_ds";
  375. function = "emmc";
  376. bias-pull-down;
  377. };
  378. };
  379. emmc_clk_gate_pins: emmc_clk_gate {
  380. mux {
  381. groups = "BOOT_8";
  382. function = "gpio_periphs";
  383. bias-pull-down;
  384. };
  385. };
  386. nor_pins: nor {
  387. mux {
  388. groups = "nor_d",
  389. "nor_q",
  390. "nor_c",
  391. "nor_cs";
  392. function = "nor";
  393. bias-disable;
  394. };
  395. };
  396. spi_pins: spi-pins {
  397. mux {
  398. groups = "spi_miso",
  399. "spi_mosi",
  400. "spi_sclk";
  401. function = "spi";
  402. bias-disable;
  403. };
  404. };
  405. spi_ss0_pins: spi-ss0 {
  406. mux {
  407. groups = "spi_ss0";
  408. function = "spi";
  409. bias-disable;
  410. };
  411. };
  412. sdcard_pins: sdcard {
  413. mux-0 {
  414. groups = "sdcard_d0",
  415. "sdcard_d1",
  416. "sdcard_d2",
  417. "sdcard_d3",
  418. "sdcard_cmd";
  419. function = "sdcard";
  420. bias-pull-up;
  421. };
  422. mux-1 {
  423. groups = "sdcard_clk";
  424. function = "sdcard";
  425. bias-disable;
  426. };
  427. };
  428. sdcard_clk_gate_pins: sdcard_clk_gate {
  429. mux {
  430. groups = "CARD_2";
  431. function = "gpio_periphs";
  432. bias-pull-down;
  433. };
  434. };
  435. sdio_pins: sdio {
  436. mux-0 {
  437. groups = "sdio_d0",
  438. "sdio_d1",
  439. "sdio_d2",
  440. "sdio_d3",
  441. "sdio_cmd";
  442. function = "sdio";
  443. bias-pull-up;
  444. };
  445. mux-1 {
  446. groups = "sdio_clk";
  447. function = "sdio";
  448. bias-disable;
  449. };
  450. };
  451. sdio_clk_gate_pins: sdio_clk_gate {
  452. mux {
  453. groups = "GPIOX_4";
  454. function = "gpio_periphs";
  455. bias-pull-down;
  456. };
  457. };
  458. sdio_irq_pins: sdio_irq {
  459. mux {
  460. groups = "sdio_irq";
  461. function = "sdio";
  462. bias-disable;
  463. };
  464. };
  465. uart_a_pins: uart_a {
  466. mux {
  467. groups = "uart_tx_a",
  468. "uart_rx_a";
  469. function = "uart_a";
  470. bias-disable;
  471. };
  472. };
  473. uart_a_cts_rts_pins: uart_a_cts_rts {
  474. mux {
  475. groups = "uart_cts_a",
  476. "uart_rts_a";
  477. function = "uart_a";
  478. bias-disable;
  479. };
  480. };
  481. uart_b_pins: uart_b {
  482. mux {
  483. groups = "uart_tx_b",
  484. "uart_rx_b";
  485. function = "uart_b";
  486. bias-disable;
  487. };
  488. };
  489. uart_b_cts_rts_pins: uart_b_cts_rts {
  490. mux {
  491. groups = "uart_cts_b",
  492. "uart_rts_b";
  493. function = "uart_b";
  494. bias-disable;
  495. };
  496. };
  497. uart_c_pins: uart_c {
  498. mux {
  499. groups = "uart_tx_c",
  500. "uart_rx_c";
  501. function = "uart_c";
  502. bias-disable;
  503. };
  504. };
  505. uart_c_cts_rts_pins: uart_c_cts_rts {
  506. mux {
  507. groups = "uart_cts_c",
  508. "uart_rts_c";
  509. function = "uart_c";
  510. bias-disable;
  511. };
  512. };
  513. i2c_a_pins: i2c_a {
  514. mux {
  515. groups = "i2c_sck_a",
  516. "i2c_sda_a";
  517. function = "i2c_a";
  518. bias-disable;
  519. };
  520. };
  521. i2c_b_pins: i2c_b {
  522. mux {
  523. groups = "i2c_sck_b",
  524. "i2c_sda_b";
  525. function = "i2c_b";
  526. bias-disable;
  527. };
  528. };
  529. i2c_c_pins: i2c_c {
  530. mux {
  531. groups = "i2c_sck_c",
  532. "i2c_sda_c";
  533. function = "i2c_c";
  534. bias-disable;
  535. };
  536. };
  537. eth_rgmii_pins: eth-rgmii {
  538. mux {
  539. groups = "eth_mdio",
  540. "eth_mdc",
  541. "eth_clk_rx_clk",
  542. "eth_rx_dv",
  543. "eth_rxd0",
  544. "eth_rxd1",
  545. "eth_rxd2",
  546. "eth_rxd3",
  547. "eth_rgmii_tx_clk",
  548. "eth_tx_en",
  549. "eth_txd0",
  550. "eth_txd1",
  551. "eth_txd2",
  552. "eth_txd3";
  553. function = "eth";
  554. bias-disable;
  555. };
  556. };
  557. eth_rmii_pins: eth-rmii {
  558. mux {
  559. groups = "eth_mdio",
  560. "eth_mdc",
  561. "eth_clk_rx_clk",
  562. "eth_rx_dv",
  563. "eth_rxd0",
  564. "eth_rxd1",
  565. "eth_tx_en",
  566. "eth_txd0",
  567. "eth_txd1";
  568. function = "eth";
  569. bias-disable;
  570. };
  571. };
  572. pwm_a_x_pins: pwm_a_x {
  573. mux {
  574. groups = "pwm_a_x";
  575. function = "pwm_a_x";
  576. bias-disable;
  577. };
  578. };
  579. pwm_a_y_pins: pwm_a_y {
  580. mux {
  581. groups = "pwm_a_y";
  582. function = "pwm_a_y";
  583. bias-disable;
  584. };
  585. };
  586. pwm_b_pins: pwm_b {
  587. mux {
  588. groups = "pwm_b";
  589. function = "pwm_b";
  590. bias-disable;
  591. };
  592. };
  593. pwm_d_pins: pwm_d {
  594. mux {
  595. groups = "pwm_d";
  596. function = "pwm_d";
  597. bias-disable;
  598. };
  599. };
  600. pwm_e_pins: pwm_e {
  601. mux {
  602. groups = "pwm_e";
  603. function = "pwm_e";
  604. bias-disable;
  605. };
  606. };
  607. pwm_f_x_pins: pwm_f_x {
  608. mux {
  609. groups = "pwm_f_x";
  610. function = "pwm_f_x";
  611. bias-disable;
  612. };
  613. };
  614. pwm_f_y_pins: pwm_f_y {
  615. mux {
  616. groups = "pwm_f_y";
  617. function = "pwm_f_y";
  618. bias-disable;
  619. };
  620. };
  621. hdmi_hpd_pins: hdmi_hpd {
  622. mux {
  623. groups = "hdmi_hpd";
  624. function = "hdmi_hpd";
  625. bias-disable;
  626. };
  627. };
  628. hdmi_i2c_pins: hdmi_i2c {
  629. mux {
  630. groups = "hdmi_sda", "hdmi_scl";
  631. function = "hdmi_i2c";
  632. bias-disable;
  633. };
  634. };
  635. i2sout_ch23_y_pins: i2sout_ch23_y {
  636. mux {
  637. groups = "i2sout_ch23_y";
  638. function = "i2s_out";
  639. bias-disable;
  640. };
  641. };
  642. i2sout_ch45_y_pins: i2sout_ch45_y {
  643. mux {
  644. groups = "i2sout_ch45_y";
  645. function = "i2s_out";
  646. bias-disable;
  647. };
  648. };
  649. i2sout_ch67_y_pins: i2sout_ch67_y {
  650. mux {
  651. groups = "i2sout_ch67_y";
  652. function = "i2s_out";
  653. bias-disable;
  654. };
  655. };
  656. spdif_out_y_pins: spdif_out_y {
  657. mux {
  658. groups = "spdif_out_y";
  659. function = "spdif_out";
  660. bias-disable;
  661. };
  662. };
  663. };
  664. };
  665. &pwrc_vpu {
  666. resets = <&reset RESET_VIU>,
  667. <&reset RESET_VENC>,
  668. <&reset RESET_VCBUS>,
  669. <&reset RESET_BT656>,
  670. <&reset RESET_DVIN_RESET>,
  671. <&reset RESET_RDMA>,
  672. <&reset RESET_VENCI>,
  673. <&reset RESET_VENCP>,
  674. <&reset RESET_VDAC>,
  675. <&reset RESET_VDI6>,
  676. <&reset RESET_VENCL>,
  677. <&reset RESET_VID_LOCK>;
  678. clocks = <&clkc CLKID_VPU>,
  679. <&clkc CLKID_VAPB>;
  680. clock-names = "vpu", "vapb";
  681. /*
  682. * VPU clocking is provided by two identical clock paths
  683. * VPU_0 and VPU_1 muxed to a single clock by a glitch
  684. * free mux to safely change frequency while running.
  685. * Same for VAPB but with a final gate after the glitch free mux.
  686. */
  687. assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  688. <&clkc CLKID_VPU_0>,
  689. <&clkc CLKID_VPU>, /* Glitch free mux */
  690. <&clkc CLKID_VAPB_0_SEL>,
  691. <&clkc CLKID_VAPB_0>,
  692. <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  693. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  694. <0>, /* Do Nothing */
  695. <&clkc CLKID_VPU_0>,
  696. <&clkc CLKID_FCLK_DIV4>,
  697. <0>, /* Do Nothing */
  698. <&clkc CLKID_VAPB_0>;
  699. assigned-clock-rates = <0>, /* Do Nothing */
  700. <666666666>,
  701. <0>, /* Do Nothing */
  702. <0>, /* Do Nothing */
  703. <250000000>,
  704. <0>; /* Do Nothing */
  705. };
  706. &saradc {
  707. compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
  708. clocks = <&xtal>,
  709. <&clkc CLKID_SAR_ADC>,
  710. <&clkc CLKID_SAR_ADC_CLK>,
  711. <&clkc CLKID_SAR_ADC_SEL>;
  712. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  713. };
  714. &sd_emmc_a {
  715. clocks = <&clkc CLKID_SD_EMMC_A>,
  716. <&clkc CLKID_SD_EMMC_A_CLK0>,
  717. <&clkc CLKID_FCLK_DIV2>;
  718. clock-names = "core", "clkin0", "clkin1";
  719. resets = <&reset RESET_SD_EMMC_A>;
  720. };
  721. &sd_emmc_b {
  722. clocks = <&clkc CLKID_SD_EMMC_B>,
  723. <&clkc CLKID_SD_EMMC_B_CLK0>,
  724. <&clkc CLKID_FCLK_DIV2>;
  725. clock-names = "core", "clkin0", "clkin1";
  726. resets = <&reset RESET_SD_EMMC_B>;
  727. };
  728. &sd_emmc_c {
  729. clocks = <&clkc CLKID_SD_EMMC_C>,
  730. <&clkc CLKID_SD_EMMC_C_CLK0>,
  731. <&clkc CLKID_FCLK_DIV2>;
  732. clock-names = "core", "clkin0", "clkin1";
  733. resets = <&reset RESET_SD_EMMC_C>;
  734. };
  735. &simplefb_hdmi {
  736. clocks = <&clkc CLKID_HDMI_PCLK>,
  737. <&clkc CLKID_CLK81>,
  738. <&clkc CLKID_GCLK_VENCI_INT0>;
  739. };
  740. &spicc {
  741. clocks = <&clkc CLKID_SPICC>;
  742. clock-names = "core";
  743. resets = <&reset RESET_PERIPHS_SPICC>;
  744. num-cs = <1>;
  745. };
  746. &spifc {
  747. clocks = <&clkc CLKID_SPI>;
  748. };
  749. &uart_A {
  750. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  751. clock-names = "xtal", "pclk", "baud";
  752. };
  753. &uart_AO {
  754. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
  755. clock-names = "xtal", "pclk", "baud";
  756. };
  757. &uart_AO_B {
  758. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  759. clock-names = "xtal", "pclk", "baud";
  760. };
  761. &uart_B {
  762. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  763. clock-names = "xtal", "pclk", "baud";
  764. };
  765. &uart_C {
  766. clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  767. clock-names = "xtal", "pclk", "baud";
  768. };
  769. &vpu {
  770. compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
  771. power-domains = <&pwrc_vpu>;
  772. };
  773. &vdec {
  774. compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
  775. clocks = <&clkc CLKID_DOS_PARSER>,
  776. <&clkc CLKID_DOS>,
  777. <&clkc CLKID_VDEC_1>,
  778. <&clkc CLKID_VDEC_HEVC>;
  779. clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
  780. resets = <&reset RESET_PARSER>;
  781. reset-names = "esparser";
  782. };