meson-gx.dtsi 16 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Andreas Färber
  4. *
  5. * Copyright (c) 2016 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. *
  8. * Copyright (c) 2016 Endless Computers, Inc.
  9. * Author: Carlo Caione <carlo@endlessm.com>
  10. */
  11. #include <dt-bindings/gpio/gpio.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. #include <dt-bindings/interrupt-controller/arm-gic.h>
  14. #include <dt-bindings/thermal/thermal.h>
  15. / {
  16. interrupt-parent = <&gic>;
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19. reserved-memory {
  20. #address-cells = <2>;
  21. #size-cells = <2>;
  22. ranges;
  23. /* 16 MiB reserved for Hardware ROM Firmware */
  24. hwrom_reserved: hwrom@0 {
  25. reg = <0x0 0x0 0x0 0x1000000>;
  26. no-map;
  27. };
  28. /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
  29. secmon_reserved: secmon@10000000 {
  30. reg = <0x0 0x10000000 0x0 0x200000>;
  31. no-map;
  32. };
  33. /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  34. secmon_reserved_alt: secmon@5000000 {
  35. reg = <0x0 0x05000000 0x0 0x300000>;
  36. no-map;
  37. };
  38. linux,cma {
  39. compatible = "shared-dma-pool";
  40. reusable;
  41. size = <0x0 0x10000000>;
  42. alignment = <0x0 0x400000>;
  43. linux,cma-default;
  44. };
  45. };
  46. chosen {
  47. #address-cells = <2>;
  48. #size-cells = <2>;
  49. ranges;
  50. simplefb_cvbs: framebuffer-cvbs {
  51. compatible = "amlogic,simple-framebuffer",
  52. "simple-framebuffer";
  53. amlogic,pipeline = "vpu-cvbs";
  54. power-domains = <&pwrc_vpu>;
  55. status = "disabled";
  56. };
  57. simplefb_hdmi: framebuffer-hdmi {
  58. compatible = "amlogic,simple-framebuffer",
  59. "simple-framebuffer";
  60. amlogic,pipeline = "vpu-hdmi";
  61. power-domains = <&pwrc_vpu>;
  62. status = "disabled";
  63. };
  64. };
  65. cpus {
  66. #address-cells = <0x2>;
  67. #size-cells = <0x0>;
  68. cpu0: cpu@0 {
  69. device_type = "cpu";
  70. compatible = "arm,cortex-a53";
  71. reg = <0x0 0x0>;
  72. enable-method = "psci";
  73. next-level-cache = <&l2>;
  74. clocks = <&scpi_dvfs 0>;
  75. #cooling-cells = <2>;
  76. };
  77. cpu1: cpu@1 {
  78. device_type = "cpu";
  79. compatible = "arm,cortex-a53";
  80. reg = <0x0 0x1>;
  81. enable-method = "psci";
  82. next-level-cache = <&l2>;
  83. clocks = <&scpi_dvfs 0>;
  84. #cooling-cells = <2>;
  85. };
  86. cpu2: cpu@2 {
  87. device_type = "cpu";
  88. compatible = "arm,cortex-a53";
  89. reg = <0x0 0x2>;
  90. enable-method = "psci";
  91. next-level-cache = <&l2>;
  92. clocks = <&scpi_dvfs 0>;
  93. #cooling-cells = <2>;
  94. };
  95. cpu3: cpu@3 {
  96. device_type = "cpu";
  97. compatible = "arm,cortex-a53";
  98. reg = <0x0 0x3>;
  99. enable-method = "psci";
  100. next-level-cache = <&l2>;
  101. clocks = <&scpi_dvfs 0>;
  102. #cooling-cells = <2>;
  103. };
  104. l2: l2-cache0 {
  105. compatible = "cache";
  106. };
  107. };
  108. thermal-zones {
  109. cpu-thermal {
  110. polling-delay-passive = <250>; /* milliseconds */
  111. polling-delay = <1000>; /* milliseconds */
  112. thermal-sensors = <&scpi_sensors 0>;
  113. trips {
  114. cpu_passive: cpu-passive {
  115. temperature = <80000>; /* millicelsius */
  116. hysteresis = <2000>; /* millicelsius */
  117. type = "passive";
  118. };
  119. cpu_hot: cpu-hot {
  120. temperature = <90000>; /* millicelsius */
  121. hysteresis = <2000>; /* millicelsius */
  122. type = "hot";
  123. };
  124. cpu_critical: cpu-critical {
  125. temperature = <110000>; /* millicelsius */
  126. hysteresis = <2000>; /* millicelsius */
  127. type = "critical";
  128. };
  129. };
  130. cpu_cooling_maps: cooling-maps {
  131. map0 {
  132. trip = <&cpu_passive>;
  133. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  134. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  135. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  136. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  137. };
  138. map1 {
  139. trip = <&cpu_hot>;
  140. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  141. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  142. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  143. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  144. };
  145. };
  146. };
  147. };
  148. arm-pmu {
  149. compatible = "arm,cortex-a53-pmu";
  150. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  151. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  152. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  153. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  154. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  155. };
  156. psci {
  157. compatible = "arm,psci-0.2";
  158. method = "smc";
  159. };
  160. timer {
  161. compatible = "arm,armv8-timer";
  162. interrupts = <GIC_PPI 13
  163. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  164. <GIC_PPI 14
  165. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  166. <GIC_PPI 11
  167. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  168. <GIC_PPI 10
  169. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  170. };
  171. xtal: xtal-clk {
  172. compatible = "fixed-clock";
  173. clock-frequency = <24000000>;
  174. clock-output-names = "xtal";
  175. #clock-cells = <0>;
  176. };
  177. firmware {
  178. sm: secure-monitor {
  179. compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
  180. };
  181. };
  182. efuse: efuse {
  183. compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. read-only;
  187. secure-monitor = <&sm>;
  188. sn: sn@14 {
  189. reg = <0x14 0x10>;
  190. };
  191. eth_mac: eth_mac@34 {
  192. reg = <0x34 0x10>;
  193. };
  194. bid: bid@46 {
  195. reg = <0x46 0x30>;
  196. };
  197. };
  198. scpi {
  199. compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
  200. mboxes = <&mailbox 1 &mailbox 2>;
  201. shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
  202. scpi_clocks: clocks {
  203. compatible = "arm,scpi-clocks";
  204. scpi_dvfs: scpi_clocks@0 {
  205. compatible = "arm,scpi-dvfs-clocks";
  206. #clock-cells = <1>;
  207. clock-indices = <0>;
  208. clock-output-names = "vcpu";
  209. };
  210. };
  211. scpi_sensors: sensors {
  212. compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
  213. #thermal-sensor-cells = <1>;
  214. };
  215. };
  216. soc {
  217. compatible = "simple-bus";
  218. #address-cells = <2>;
  219. #size-cells = <2>;
  220. ranges;
  221. cbus: bus@c1100000 {
  222. compatible = "simple-bus";
  223. reg = <0x0 0xc1100000 0x0 0x100000>;
  224. #address-cells = <2>;
  225. #size-cells = <2>;
  226. ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
  227. gpio_intc: interrupt-controller@9880 {
  228. compatible = "amlogic,meson-gpio-intc";
  229. reg = <0x0 0x9880 0x0 0x10>;
  230. interrupt-controller;
  231. #interrupt-cells = <2>;
  232. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  233. status = "disabled";
  234. };
  235. reset: reset-controller@4404 {
  236. compatible = "amlogic,meson-gxbb-reset";
  237. reg = <0x0 0x04404 0x0 0x9c>;
  238. #reset-cells = <1>;
  239. };
  240. aiu: audio-controller@5400 {
  241. compatible = "amlogic,aiu";
  242. #sound-dai-cells = <2>;
  243. sound-name-prefix = "AIU";
  244. reg = <0x0 0x5400 0x0 0x2ac>;
  245. interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
  246. <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
  247. interrupt-names = "i2s", "spdif";
  248. status = "disabled";
  249. };
  250. uart_A: serial@84c0 {
  251. compatible = "amlogic,meson-gx-uart";
  252. reg = <0x0 0x84c0 0x0 0x18>;
  253. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  254. status = "disabled";
  255. };
  256. uart_B: serial@84dc {
  257. compatible = "amlogic,meson-gx-uart";
  258. reg = <0x0 0x84dc 0x0 0x18>;
  259. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  260. status = "disabled";
  261. };
  262. i2c_A: i2c@8500 {
  263. compatible = "amlogic,meson-gxbb-i2c";
  264. reg = <0x0 0x08500 0x0 0x20>;
  265. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. status = "disabled";
  269. };
  270. pwm_ab: pwm@8550 {
  271. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  272. reg = <0x0 0x08550 0x0 0x10>;
  273. #pwm-cells = <3>;
  274. status = "disabled";
  275. };
  276. pwm_cd: pwm@8650 {
  277. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  278. reg = <0x0 0x08650 0x0 0x10>;
  279. #pwm-cells = <3>;
  280. status = "disabled";
  281. };
  282. saradc: adc@8680 {
  283. compatible = "amlogic,meson-saradc";
  284. reg = <0x0 0x8680 0x0 0x34>;
  285. #io-channel-cells = <1>;
  286. interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
  287. status = "disabled";
  288. };
  289. pwm_ef: pwm@86c0 {
  290. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  291. reg = <0x0 0x086c0 0x0 0x10>;
  292. #pwm-cells = <3>;
  293. status = "disabled";
  294. };
  295. uart_C: serial@8700 {
  296. compatible = "amlogic,meson-gx-uart";
  297. reg = <0x0 0x8700 0x0 0x18>;
  298. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  299. status = "disabled";
  300. };
  301. clock-measure@8758 {
  302. compatible = "amlogic,meson-gx-clk-measure";
  303. reg = <0x0 0x8758 0x0 0x10>;
  304. };
  305. i2c_B: i2c@87c0 {
  306. compatible = "amlogic,meson-gxbb-i2c";
  307. reg = <0x0 0x087c0 0x0 0x20>;
  308. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  309. #address-cells = <1>;
  310. #size-cells = <0>;
  311. status = "disabled";
  312. };
  313. i2c_C: i2c@87e0 {
  314. compatible = "amlogic,meson-gxbb-i2c";
  315. reg = <0x0 0x087e0 0x0 0x20>;
  316. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. status = "disabled";
  320. };
  321. spicc: spi@8d80 {
  322. compatible = "amlogic,meson-gx-spicc";
  323. reg = <0x0 0x08d80 0x0 0x80>;
  324. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  325. #address-cells = <1>;
  326. #size-cells = <0>;
  327. status = "disabled";
  328. };
  329. spifc: spi@8c80 {
  330. compatible = "amlogic,meson-gxbb-spifc";
  331. reg = <0x0 0x08c80 0x0 0x80>;
  332. #address-cells = <1>;
  333. #size-cells = <0>;
  334. status = "disabled";
  335. };
  336. watchdog@98d0 {
  337. compatible = "amlogic,meson-gxbb-wdt";
  338. reg = <0x0 0x098d0 0x0 0x10>;
  339. clocks = <&xtal>;
  340. };
  341. };
  342. gic: interrupt-controller@c4301000 {
  343. compatible = "arm,gic-400";
  344. reg = <0x0 0xc4301000 0 0x1000>,
  345. <0x0 0xc4302000 0 0x2000>,
  346. <0x0 0xc4304000 0 0x2000>,
  347. <0x0 0xc4306000 0 0x2000>;
  348. interrupt-controller;
  349. interrupts = <GIC_PPI 9
  350. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  351. #interrupt-cells = <3>;
  352. #address-cells = <0>;
  353. };
  354. sram: sram@c8000000 {
  355. compatible = "mmio-sram";
  356. reg = <0x0 0xc8000000 0x0 0x14000>;
  357. #address-cells = <1>;
  358. #size-cells = <1>;
  359. ranges = <0 0x0 0xc8000000 0x14000>;
  360. cpu_scp_lpri: scp-sram@0 {
  361. compatible = "amlogic,meson-gxbb-scp-shmem";
  362. reg = <0x13000 0x400>;
  363. };
  364. cpu_scp_hpri: scp-sram@200 {
  365. compatible = "amlogic,meson-gxbb-scp-shmem";
  366. reg = <0x13400 0x400>;
  367. };
  368. };
  369. aobus: bus@c8100000 {
  370. compatible = "simple-bus";
  371. reg = <0x0 0xc8100000 0x0 0x100000>;
  372. #address-cells = <2>;
  373. #size-cells = <2>;
  374. ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
  375. sysctrl_AO: sys-ctrl@0 {
  376. compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
  377. reg = <0x0 0x0 0x0 0x100>;
  378. pwrc_vpu: power-controller-vpu {
  379. compatible = "amlogic,meson-gx-pwrc-vpu";
  380. #power-domain-cells = <0>;
  381. amlogic,hhi-sysctrl = <&sysctrl>;
  382. };
  383. clkc_AO: clock-controller {
  384. compatible = "amlogic,meson-gx-aoclkc";
  385. #clock-cells = <1>;
  386. #reset-cells = <1>;
  387. };
  388. };
  389. cec_AO: cec@100 {
  390. compatible = "amlogic,meson-gx-ao-cec";
  391. reg = <0x0 0x00100 0x0 0x14>;
  392. interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
  393. status = "disabled";
  394. };
  395. sec_AO: ao-secure@140 {
  396. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  397. reg = <0x0 0x140 0x0 0x140>;
  398. amlogic,has-chip-id;
  399. };
  400. uart_AO: serial@4c0 {
  401. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  402. reg = <0x0 0x004c0 0x0 0x18>;
  403. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  404. status = "disabled";
  405. };
  406. uart_AO_B: serial@4e0 {
  407. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  408. reg = <0x0 0x004e0 0x0 0x18>;
  409. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  410. status = "disabled";
  411. };
  412. i2c_AO: i2c@500 {
  413. compatible = "amlogic,meson-gxbb-i2c";
  414. reg = <0x0 0x500 0x0 0x20>;
  415. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  416. #address-cells = <1>;
  417. #size-cells = <0>;
  418. status = "disabled";
  419. };
  420. pwm_AO_ab: pwm@550 {
  421. compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
  422. reg = <0x0 0x00550 0x0 0x10>;
  423. #pwm-cells = <3>;
  424. status = "disabled";
  425. };
  426. ir: ir@580 {
  427. compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
  428. reg = <0x0 0x00580 0x0 0x40>;
  429. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  430. status = "disabled";
  431. };
  432. };
  433. vdec: video-codec@c8820000 {
  434. compatible = "amlogic,gx-vdec";
  435. reg = <0x0 0xc8820000 0x0 0x10000>,
  436. <0x0 0xc110a580 0x0 0xe4>;
  437. reg-names = "dos", "esparser";
  438. interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
  439. <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
  440. interrupt-names = "vdec", "esparser";
  441. amlogic,ao-sysctrl = <&sysctrl_AO>;
  442. amlogic,canvas = <&canvas>;
  443. };
  444. periphs: bus@c8834000 {
  445. compatible = "simple-bus";
  446. reg = <0x0 0xc8834000 0x0 0x2000>;
  447. #address-cells = <2>;
  448. #size-cells = <2>;
  449. ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
  450. hwrng: rng {
  451. compatible = "amlogic,meson-rng";
  452. reg = <0x0 0x0 0x0 0x4>;
  453. };
  454. };
  455. dmcbus: bus@c8838000 {
  456. compatible = "simple-bus";
  457. reg = <0x0 0xc8838000 0x0 0x400>;
  458. #address-cells = <2>;
  459. #size-cells = <2>;
  460. ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
  461. canvas: video-lut@48 {
  462. compatible = "amlogic,canvas";
  463. reg = <0x0 0x48 0x0 0x14>;
  464. };
  465. };
  466. hiubus: bus@c883c000 {
  467. compatible = "simple-bus";
  468. reg = <0x0 0xc883c000 0x0 0x2000>;
  469. #address-cells = <2>;
  470. #size-cells = <2>;
  471. ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
  472. sysctrl: system-controller@0 {
  473. compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
  474. reg = <0 0 0 0x400>;
  475. };
  476. mailbox: mailbox@404 {
  477. compatible = "amlogic,meson-gxbb-mhu";
  478. reg = <0 0x404 0 0x4c>;
  479. interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
  480. <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
  481. <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
  482. #mbox-cells = <1>;
  483. };
  484. };
  485. ethmac: ethernet@c9410000 {
  486. compatible = "amlogic,meson-gxbb-dwmac",
  487. "snps,dwmac-3.70a",
  488. "snps,dwmac";
  489. reg = <0x0 0xc9410000 0x0 0x10000>,
  490. <0x0 0xc8834540 0x0 0x4>;
  491. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  492. interrupt-names = "macirq";
  493. rx-fifo-depth = <4096>;
  494. tx-fifo-depth = <2048>;
  495. status = "disabled";
  496. };
  497. apb: apb@d0000000 {
  498. compatible = "simple-bus";
  499. reg = <0x0 0xd0000000 0x0 0x200000>;
  500. #address-cells = <2>;
  501. #size-cells = <2>;
  502. ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
  503. sd_emmc_a: mmc@70000 {
  504. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  505. reg = <0x0 0x70000 0x0 0x800>;
  506. interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
  507. status = "disabled";
  508. };
  509. sd_emmc_b: mmc@72000 {
  510. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  511. reg = <0x0 0x72000 0x0 0x800>;
  512. interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
  513. status = "disabled";
  514. };
  515. sd_emmc_c: mmc@74000 {
  516. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  517. reg = <0x0 0x74000 0x0 0x800>;
  518. interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
  519. status = "disabled";
  520. };
  521. };
  522. vpu: vpu@d0100000 {
  523. compatible = "amlogic,meson-gx-vpu";
  524. reg = <0x0 0xd0100000 0x0 0x100000>,
  525. <0x0 0xc883c000 0x0 0x1000>;
  526. reg-names = "vpu", "hhi";
  527. interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  528. #address-cells = <1>;
  529. #size-cells = <0>;
  530. amlogic,canvas = <&canvas>;
  531. /* CVBS VDAC output port */
  532. cvbs_vdac_port: port@0 {
  533. reg = <0>;
  534. };
  535. /* HDMI-TX output port */
  536. hdmi_tx_port: port@1 {
  537. reg = <1>;
  538. hdmi_tx_out: endpoint {
  539. remote-endpoint = <&hdmi_tx_in>;
  540. };
  541. };
  542. };
  543. hdmi_tx: hdmi-tx@c883a000 {
  544. compatible = "amlogic,meson-gx-dw-hdmi";
  545. reg = <0x0 0xc883a000 0x0 0x1c>;
  546. interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
  547. #address-cells = <1>;
  548. #size-cells = <0>;
  549. #sound-dai-cells = <0>;
  550. sound-name-prefix = "HDMITX";
  551. status = "disabled";
  552. /* VPU VENC Input */
  553. hdmi_tx_venc_port: port@0 {
  554. reg = <0>;
  555. hdmi_tx_in: endpoint {
  556. remote-endpoint = <&hdmi_tx_out>;
  557. };
  558. };
  559. /* TMDS Output */
  560. hdmi_tx_tmds_port: port@1 {
  561. reg = <1>;
  562. };
  563. };
  564. };
  565. };