meson-g12-common.dtsi 53 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  4. */
  5. #include <dt-bindings/phy/phy.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/clock/g12a-clkc.h>
  8. #include <dt-bindings/clock/g12a-aoclkc.h>
  9. #include <dt-bindings/interrupt-controller/irq.h>
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
  12. #include <dt-bindings/thermal/thermal.h>
  13. / {
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. chosen {
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. ranges;
  21. simplefb_cvbs: framebuffer-cvbs {
  22. compatible = "amlogic,simple-framebuffer",
  23. "simple-framebuffer";
  24. amlogic,pipeline = "vpu-cvbs";
  25. clocks = <&clkc CLKID_HDMI>,
  26. <&clkc CLKID_HTX_PCLK>,
  27. <&clkc CLKID_VPU_INTR>;
  28. status = "disabled";
  29. };
  30. simplefb_hdmi: framebuffer-hdmi {
  31. compatible = "amlogic,simple-framebuffer",
  32. "simple-framebuffer";
  33. amlogic,pipeline = "vpu-hdmi";
  34. clocks = <&clkc CLKID_HDMI>,
  35. <&clkc CLKID_HTX_PCLK>,
  36. <&clkc CLKID_VPU_INTR>;
  37. status = "disabled";
  38. };
  39. };
  40. efuse: efuse {
  41. compatible = "amlogic,meson-gxbb-efuse";
  42. clocks = <&clkc CLKID_EFUSE>;
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. read-only;
  46. secure-monitor = <&sm>;
  47. };
  48. gpu_opp_table: gpu-opp-table {
  49. compatible = "operating-points-v2";
  50. opp-124999998 {
  51. opp-hz = /bits/ 64 <124999998>;
  52. opp-microvolt = <800000>;
  53. };
  54. opp-249999996 {
  55. opp-hz = /bits/ 64 <249999996>;
  56. opp-microvolt = <800000>;
  57. };
  58. opp-285714281 {
  59. opp-hz = /bits/ 64 <285714281>;
  60. opp-microvolt = <800000>;
  61. };
  62. opp-399999994 {
  63. opp-hz = /bits/ 64 <399999994>;
  64. opp-microvolt = <800000>;
  65. };
  66. opp-499999992 {
  67. opp-hz = /bits/ 64 <499999992>;
  68. opp-microvolt = <800000>;
  69. };
  70. opp-666666656 {
  71. opp-hz = /bits/ 64 <666666656>;
  72. opp-microvolt = <800000>;
  73. };
  74. opp-799999987 {
  75. opp-hz = /bits/ 64 <799999987>;
  76. opp-microvolt = <800000>;
  77. };
  78. };
  79. psci {
  80. compatible = "arm,psci-1.0";
  81. method = "smc";
  82. };
  83. reserved-memory {
  84. #address-cells = <2>;
  85. #size-cells = <2>;
  86. ranges;
  87. /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
  88. secmon_reserved: secmon@5000000 {
  89. reg = <0x0 0x05000000 0x0 0x300000>;
  90. no-map;
  91. };
  92. linux,cma {
  93. compatible = "shared-dma-pool";
  94. reusable;
  95. size = <0x0 0x10000000>;
  96. alignment = <0x0 0x400000>;
  97. linux,cma-default;
  98. };
  99. };
  100. sm: secure-monitor {
  101. compatible = "amlogic,meson-gxbb-sm";
  102. };
  103. soc {
  104. compatible = "simple-bus";
  105. #address-cells = <2>;
  106. #size-cells = <2>;
  107. ranges;
  108. pcie: pcie@fc000000 {
  109. compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
  110. reg = <0x0 0xfc000000 0x0 0x400000
  111. 0x0 0xff648000 0x0 0x2000
  112. 0x0 0xfc400000 0x0 0x200000>;
  113. reg-names = "elbi", "cfg", "config";
  114. interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  115. #interrupt-cells = <1>;
  116. interrupt-map-mask = <0 0 0 0>;
  117. interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
  118. bus-range = <0x0 0xff>;
  119. #address-cells = <3>;
  120. #size-cells = <2>;
  121. device_type = "pci";
  122. ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
  123. 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
  124. clocks = <&clkc CLKID_PCIE_PHY
  125. &clkc CLKID_PCIE_COMB
  126. &clkc CLKID_PCIE_PLL>;
  127. clock-names = "general",
  128. "pclk",
  129. "port";
  130. resets = <&reset RESET_PCIE_CTRL_A>,
  131. <&reset RESET_PCIE_APB>;
  132. reset-names = "port",
  133. "apb";
  134. num-lanes = <1>;
  135. phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
  136. phy-names = "pcie";
  137. status = "disabled";
  138. };
  139. thermal-zones {
  140. cpu_thermal: cpu-thermal {
  141. polling-delay = <1000>;
  142. polling-delay-passive = <100>;
  143. thermal-sensors = <&cpu_temp>;
  144. trips {
  145. cpu_passive: cpu-passive {
  146. temperature = <85000>; /* millicelsius */
  147. hysteresis = <2000>; /* millicelsius */
  148. type = "passive";
  149. };
  150. cpu_hot: cpu-hot {
  151. temperature = <95000>; /* millicelsius */
  152. hysteresis = <2000>; /* millicelsius */
  153. type = "hot";
  154. };
  155. cpu_critical: cpu-critical {
  156. temperature = <110000>; /* millicelsius */
  157. hysteresis = <2000>; /* millicelsius */
  158. type = "critical";
  159. };
  160. };
  161. };
  162. ddr_thermal: ddr-thermal {
  163. polling-delay = <1000>;
  164. polling-delay-passive = <100>;
  165. thermal-sensors = <&ddr_temp>;
  166. trips {
  167. ddr_passive: ddr-passive {
  168. temperature = <85000>; /* millicelsius */
  169. hysteresis = <2000>; /* millicelsius */
  170. type = "passive";
  171. };
  172. ddr_critical: ddr-critical {
  173. temperature = <110000>; /* millicelsius */
  174. hysteresis = <2000>; /* millicelsius */
  175. type = "critical";
  176. };
  177. };
  178. cooling-maps {
  179. map {
  180. trip = <&ddr_passive>;
  181. cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  182. };
  183. };
  184. };
  185. };
  186. ethmac: ethernet@ff3f0000 {
  187. compatible = "amlogic,meson-axg-dwmac",
  188. "snps,dwmac-3.70a",
  189. "snps,dwmac";
  190. reg = <0x0 0xff3f0000 0x0 0x10000>,
  191. <0x0 0xff634540 0x0 0x8>;
  192. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  193. interrupt-names = "macirq";
  194. clocks = <&clkc CLKID_ETH>,
  195. <&clkc CLKID_FCLK_DIV2>,
  196. <&clkc CLKID_MPLL2>,
  197. <&clkc CLKID_FCLK_DIV2>;
  198. clock-names = "stmmaceth", "clkin0", "clkin1",
  199. "timing-adjustment";
  200. rx-fifo-depth = <4096>;
  201. tx-fifo-depth = <2048>;
  202. status = "disabled";
  203. mdio0: mdio {
  204. #address-cells = <1>;
  205. #size-cells = <0>;
  206. compatible = "snps,dwmac-mdio";
  207. };
  208. };
  209. apb: bus@ff600000 {
  210. compatible = "simple-bus";
  211. reg = <0x0 0xff600000 0x0 0x200000>;
  212. #address-cells = <2>;
  213. #size-cells = <2>;
  214. ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
  215. hdmi_tx: hdmi-tx@0 {
  216. compatible = "amlogic,meson-g12a-dw-hdmi";
  217. reg = <0x0 0x0 0x0 0x10000>;
  218. interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
  219. resets = <&reset RESET_HDMITX_CAPB3>,
  220. <&reset RESET_HDMITX_PHY>,
  221. <&reset RESET_HDMITX>;
  222. reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  223. clocks = <&clkc CLKID_HDMI>,
  224. <&clkc CLKID_HTX_PCLK>,
  225. <&clkc CLKID_VPU_INTR>;
  226. clock-names = "isfr", "iahb", "venci";
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. #sound-dai-cells = <0>;
  230. status = "disabled";
  231. /* VPU VENC Input */
  232. hdmi_tx_venc_port: port@0 {
  233. reg = <0>;
  234. hdmi_tx_in: endpoint {
  235. remote-endpoint = <&hdmi_tx_out>;
  236. };
  237. };
  238. /* TMDS Output */
  239. hdmi_tx_tmds_port: port@1 {
  240. reg = <1>;
  241. };
  242. };
  243. apb_efuse: bus@30000 {
  244. compatible = "simple-bus";
  245. reg = <0x0 0x30000 0x0 0x2000>;
  246. #address-cells = <2>;
  247. #size-cells = <2>;
  248. ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
  249. hwrng: rng@218 {
  250. compatible = "amlogic,meson-rng";
  251. reg = <0x0 0x218 0x0 0x4>;
  252. };
  253. };
  254. acodec: audio-controller@32000 {
  255. compatible = "amlogic,t9015";
  256. reg = <0x0 0x32000 0x0 0x14>;
  257. #sound-dai-cells = <0>;
  258. sound-name-prefix = "ACODEC";
  259. clocks = <&clkc CLKID_AUDIO_CODEC>;
  260. clock-names = "pclk";
  261. resets = <&reset RESET_AUDIO_CODEC>;
  262. status = "disabled";
  263. };
  264. periphs: bus@34400 {
  265. compatible = "simple-bus";
  266. reg = <0x0 0x34400 0x0 0x400>;
  267. #address-cells = <2>;
  268. #size-cells = <2>;
  269. ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
  270. periphs_pinctrl: pinctrl@40 {
  271. compatible = "amlogic,meson-g12a-periphs-pinctrl";
  272. #address-cells = <2>;
  273. #size-cells = <2>;
  274. ranges;
  275. gpio: bank@40 {
  276. reg = <0x0 0x40 0x0 0x4c>,
  277. <0x0 0xe8 0x0 0x18>,
  278. <0x0 0x120 0x0 0x18>,
  279. <0x0 0x2c0 0x0 0x40>,
  280. <0x0 0x340 0x0 0x1c>;
  281. reg-names = "gpio",
  282. "pull",
  283. "pull-enable",
  284. "mux",
  285. "ds";
  286. gpio-controller;
  287. #gpio-cells = <2>;
  288. gpio-ranges = <&periphs_pinctrl 0 0 86>;
  289. };
  290. cec_ao_a_h_pins: cec_ao_a_h {
  291. mux {
  292. groups = "cec_ao_a_h";
  293. function = "cec_ao_a_h";
  294. bias-disable;
  295. };
  296. };
  297. cec_ao_b_h_pins: cec_ao_b_h {
  298. mux {
  299. groups = "cec_ao_b_h";
  300. function = "cec_ao_b_h";
  301. bias-disable;
  302. };
  303. };
  304. emmc_ctrl_pins: emmc-ctrl {
  305. mux-0 {
  306. groups = "emmc_cmd";
  307. function = "emmc";
  308. bias-pull-up;
  309. drive-strength-microamp = <4000>;
  310. };
  311. mux-1 {
  312. groups = "emmc_clk";
  313. function = "emmc";
  314. bias-disable;
  315. drive-strength-microamp = <4000>;
  316. };
  317. };
  318. emmc_data_4b_pins: emmc-data-4b {
  319. mux-0 {
  320. groups = "emmc_nand_d0",
  321. "emmc_nand_d1",
  322. "emmc_nand_d2",
  323. "emmc_nand_d3";
  324. function = "emmc";
  325. bias-pull-up;
  326. drive-strength-microamp = <4000>;
  327. };
  328. };
  329. emmc_data_8b_pins: emmc-data-8b {
  330. mux-0 {
  331. groups = "emmc_nand_d0",
  332. "emmc_nand_d1",
  333. "emmc_nand_d2",
  334. "emmc_nand_d3",
  335. "emmc_nand_d4",
  336. "emmc_nand_d5",
  337. "emmc_nand_d6",
  338. "emmc_nand_d7";
  339. function = "emmc";
  340. bias-pull-up;
  341. drive-strength-microamp = <4000>;
  342. };
  343. };
  344. emmc_ds_pins: emmc-ds {
  345. mux {
  346. groups = "emmc_nand_ds";
  347. function = "emmc";
  348. bias-pull-down;
  349. drive-strength-microamp = <4000>;
  350. };
  351. };
  352. emmc_clk_gate_pins: emmc_clk_gate {
  353. mux {
  354. groups = "BOOT_8";
  355. function = "gpio_periphs";
  356. bias-pull-down;
  357. drive-strength-microamp = <4000>;
  358. };
  359. };
  360. hdmitx_ddc_pins: hdmitx_ddc {
  361. mux {
  362. groups = "hdmitx_sda",
  363. "hdmitx_sck";
  364. function = "hdmitx";
  365. bias-disable;
  366. drive-strength-microamp = <4000>;
  367. };
  368. };
  369. hdmitx_hpd_pins: hdmitx_hpd {
  370. mux {
  371. groups = "hdmitx_hpd_in";
  372. function = "hdmitx";
  373. bias-disable;
  374. };
  375. };
  376. i2c0_sda_c_pins: i2c0-sda-c {
  377. mux {
  378. groups = "i2c0_sda_c";
  379. function = "i2c0";
  380. bias-disable;
  381. drive-strength-microamp = <3000>;
  382. };
  383. };
  384. i2c0_sck_c_pins: i2c0-sck-c {
  385. mux {
  386. groups = "i2c0_sck_c";
  387. function = "i2c0";
  388. bias-disable;
  389. drive-strength-microamp = <3000>;
  390. };
  391. };
  392. i2c0_sda_z0_pins: i2c0-sda-z0 {
  393. mux {
  394. groups = "i2c0_sda_z0";
  395. function = "i2c0";
  396. bias-disable;
  397. drive-strength-microamp = <3000>;
  398. };
  399. };
  400. i2c0_sck_z1_pins: i2c0-sck-z1 {
  401. mux {
  402. groups = "i2c0_sck_z1";
  403. function = "i2c0";
  404. bias-disable;
  405. drive-strength-microamp = <3000>;
  406. };
  407. };
  408. i2c0_sda_z7_pins: i2c0-sda-z7 {
  409. mux {
  410. groups = "i2c0_sda_z7";
  411. function = "i2c0";
  412. bias-disable;
  413. drive-strength-microamp = <3000>;
  414. };
  415. };
  416. i2c0_sda_z8_pins: i2c0-sda-z8 {
  417. mux {
  418. groups = "i2c0_sda_z8";
  419. function = "i2c0";
  420. bias-disable;
  421. drive-strength-microamp = <3000>;
  422. };
  423. };
  424. i2c1_sda_x_pins: i2c1-sda-x {
  425. mux {
  426. groups = "i2c1_sda_x";
  427. function = "i2c1";
  428. bias-disable;
  429. drive-strength-microamp = <3000>;
  430. };
  431. };
  432. i2c1_sck_x_pins: i2c1-sck-x {
  433. mux {
  434. groups = "i2c1_sck_x";
  435. function = "i2c1";
  436. bias-disable;
  437. drive-strength-microamp = <3000>;
  438. };
  439. };
  440. i2c1_sda_h2_pins: i2c1-sda-h2 {
  441. mux {
  442. groups = "i2c1_sda_h2";
  443. function = "i2c1";
  444. bias-disable;
  445. drive-strength-microamp = <3000>;
  446. };
  447. };
  448. i2c1_sck_h3_pins: i2c1-sck-h3 {
  449. mux {
  450. groups = "i2c1_sck_h3";
  451. function = "i2c1";
  452. bias-disable;
  453. drive-strength-microamp = <3000>;
  454. };
  455. };
  456. i2c1_sda_h6_pins: i2c1-sda-h6 {
  457. mux {
  458. groups = "i2c1_sda_h6";
  459. function = "i2c1";
  460. bias-disable;
  461. drive-strength-microamp = <3000>;
  462. };
  463. };
  464. i2c1_sck_h7_pins: i2c1-sck-h7 {
  465. mux {
  466. groups = "i2c1_sck_h7";
  467. function = "i2c1";
  468. bias-disable;
  469. drive-strength-microamp = <3000>;
  470. };
  471. };
  472. i2c2_sda_x_pins: i2c2-sda-x {
  473. mux {
  474. groups = "i2c2_sda_x";
  475. function = "i2c2";
  476. bias-disable;
  477. drive-strength-microamp = <3000>;
  478. };
  479. };
  480. i2c2_sck_x_pins: i2c2-sck-x {
  481. mux {
  482. groups = "i2c2_sck_x";
  483. function = "i2c2";
  484. bias-disable;
  485. drive-strength-microamp = <3000>;
  486. };
  487. };
  488. i2c2_sda_z_pins: i2c2-sda-z {
  489. mux {
  490. groups = "i2c2_sda_z";
  491. function = "i2c2";
  492. bias-disable;
  493. drive-strength-microamp = <3000>;
  494. };
  495. };
  496. i2c2_sck_z_pins: i2c2-sck-z {
  497. mux {
  498. groups = "i2c2_sck_z";
  499. function = "i2c2";
  500. bias-disable;
  501. drive-strength-microamp = <3000>;
  502. };
  503. };
  504. i2c3_sda_h_pins: i2c3-sda-h {
  505. mux {
  506. groups = "i2c3_sda_h";
  507. function = "i2c3";
  508. bias-disable;
  509. drive-strength-microamp = <3000>;
  510. };
  511. };
  512. i2c3_sck_h_pins: i2c3-sck-h {
  513. mux {
  514. groups = "i2c3_sck_h";
  515. function = "i2c3";
  516. bias-disable;
  517. drive-strength-microamp = <3000>;
  518. };
  519. };
  520. i2c3_sda_a_pins: i2c3-sda-a {
  521. mux {
  522. groups = "i2c3_sda_a";
  523. function = "i2c3";
  524. bias-disable;
  525. drive-strength-microamp = <3000>;
  526. };
  527. };
  528. i2c3_sck_a_pins: i2c3-sck-a {
  529. mux {
  530. groups = "i2c3_sck_a";
  531. function = "i2c3";
  532. bias-disable;
  533. drive-strength-microamp = <3000>;
  534. };
  535. };
  536. mclk0_a_pins: mclk0-a {
  537. mux {
  538. groups = "mclk0_a";
  539. function = "mclk0";
  540. bias-disable;
  541. drive-strength-microamp = <3000>;
  542. };
  543. };
  544. mclk1_a_pins: mclk1-a {
  545. mux {
  546. groups = "mclk1_a";
  547. function = "mclk1";
  548. bias-disable;
  549. drive-strength-microamp = <3000>;
  550. };
  551. };
  552. mclk1_x_pins: mclk1-x {
  553. mux {
  554. groups = "mclk1_x";
  555. function = "mclk1";
  556. bias-disable;
  557. drive-strength-microamp = <3000>;
  558. };
  559. };
  560. mclk1_z_pins: mclk1-z {
  561. mux {
  562. groups = "mclk1_z";
  563. function = "mclk1";
  564. bias-disable;
  565. drive-strength-microamp = <3000>;
  566. };
  567. };
  568. nor_pins: nor {
  569. mux {
  570. groups = "nor_d",
  571. "nor_q",
  572. "nor_c",
  573. "nor_cs";
  574. function = "nor";
  575. bias-disable;
  576. };
  577. };
  578. pdm_din0_a_pins: pdm-din0-a {
  579. mux {
  580. groups = "pdm_din0_a";
  581. function = "pdm";
  582. bias-disable;
  583. };
  584. };
  585. pdm_din0_c_pins: pdm-din0-c {
  586. mux {
  587. groups = "pdm_din0_c";
  588. function = "pdm";
  589. bias-disable;
  590. };
  591. };
  592. pdm_din0_x_pins: pdm-din0-x {
  593. mux {
  594. groups = "pdm_din0_x";
  595. function = "pdm";
  596. bias-disable;
  597. };
  598. };
  599. pdm_din0_z_pins: pdm-din0-z {
  600. mux {
  601. groups = "pdm_din0_z";
  602. function = "pdm";
  603. bias-disable;
  604. };
  605. };
  606. pdm_din1_a_pins: pdm-din1-a {
  607. mux {
  608. groups = "pdm_din1_a";
  609. function = "pdm";
  610. bias-disable;
  611. };
  612. };
  613. pdm_din1_c_pins: pdm-din1-c {
  614. mux {
  615. groups = "pdm_din1_c";
  616. function = "pdm";
  617. bias-disable;
  618. };
  619. };
  620. pdm_din1_x_pins: pdm-din1-x {
  621. mux {
  622. groups = "pdm_din1_x";
  623. function = "pdm";
  624. bias-disable;
  625. };
  626. };
  627. pdm_din1_z_pins: pdm-din1-z {
  628. mux {
  629. groups = "pdm_din1_z";
  630. function = "pdm";
  631. bias-disable;
  632. };
  633. };
  634. pdm_din2_a_pins: pdm-din2-a {
  635. mux {
  636. groups = "pdm_din2_a";
  637. function = "pdm";
  638. bias-disable;
  639. };
  640. };
  641. pdm_din2_c_pins: pdm-din2-c {
  642. mux {
  643. groups = "pdm_din2_c";
  644. function = "pdm";
  645. bias-disable;
  646. };
  647. };
  648. pdm_din2_x_pins: pdm-din2-x {
  649. mux {
  650. groups = "pdm_din2_x";
  651. function = "pdm";
  652. bias-disable;
  653. };
  654. };
  655. pdm_din2_z_pins: pdm-din2-z {
  656. mux {
  657. groups = "pdm_din2_z";
  658. function = "pdm";
  659. bias-disable;
  660. };
  661. };
  662. pdm_din3_a_pins: pdm-din3-a {
  663. mux {
  664. groups = "pdm_din3_a";
  665. function = "pdm";
  666. bias-disable;
  667. };
  668. };
  669. pdm_din3_c_pins: pdm-din3-c {
  670. mux {
  671. groups = "pdm_din3_c";
  672. function = "pdm";
  673. bias-disable;
  674. };
  675. };
  676. pdm_din3_x_pins: pdm-din3-x {
  677. mux {
  678. groups = "pdm_din3_x";
  679. function = "pdm";
  680. bias-disable;
  681. };
  682. };
  683. pdm_din3_z_pins: pdm-din3-z {
  684. mux {
  685. groups = "pdm_din3_z";
  686. function = "pdm";
  687. bias-disable;
  688. };
  689. };
  690. pdm_dclk_a_pins: pdm-dclk-a {
  691. mux {
  692. groups = "pdm_dclk_a";
  693. function = "pdm";
  694. bias-disable;
  695. drive-strength-microamp = <500>;
  696. };
  697. };
  698. pdm_dclk_c_pins: pdm-dclk-c {
  699. mux {
  700. groups = "pdm_dclk_c";
  701. function = "pdm";
  702. bias-disable;
  703. drive-strength-microamp = <500>;
  704. };
  705. };
  706. pdm_dclk_x_pins: pdm-dclk-x {
  707. mux {
  708. groups = "pdm_dclk_x";
  709. function = "pdm";
  710. bias-disable;
  711. drive-strength-microamp = <500>;
  712. };
  713. };
  714. pdm_dclk_z_pins: pdm-dclk-z {
  715. mux {
  716. groups = "pdm_dclk_z";
  717. function = "pdm";
  718. bias-disable;
  719. drive-strength-microamp = <500>;
  720. };
  721. };
  722. pwm_a_pins: pwm-a {
  723. mux {
  724. groups = "pwm_a";
  725. function = "pwm_a";
  726. bias-disable;
  727. };
  728. };
  729. pwm_b_x7_pins: pwm-b-x7 {
  730. mux {
  731. groups = "pwm_b_x7";
  732. function = "pwm_b";
  733. bias-disable;
  734. };
  735. };
  736. pwm_b_x19_pins: pwm-b-x19 {
  737. mux {
  738. groups = "pwm_b_x19";
  739. function = "pwm_b";
  740. bias-disable;
  741. };
  742. };
  743. pwm_c_c_pins: pwm-c-c {
  744. mux {
  745. groups = "pwm_c_c";
  746. function = "pwm_c";
  747. bias-disable;
  748. };
  749. };
  750. pwm_c_x5_pins: pwm-c-x5 {
  751. mux {
  752. groups = "pwm_c_x5";
  753. function = "pwm_c";
  754. bias-disable;
  755. };
  756. };
  757. pwm_c_x8_pins: pwm-c-x8 {
  758. mux {
  759. groups = "pwm_c_x8";
  760. function = "pwm_c";
  761. bias-disable;
  762. };
  763. };
  764. pwm_d_x3_pins: pwm-d-x3 {
  765. mux {
  766. groups = "pwm_d_x3";
  767. function = "pwm_d";
  768. bias-disable;
  769. };
  770. };
  771. pwm_d_x6_pins: pwm-d-x6 {
  772. mux {
  773. groups = "pwm_d_x6";
  774. function = "pwm_d";
  775. bias-disable;
  776. };
  777. };
  778. pwm_e_pins: pwm-e {
  779. mux {
  780. groups = "pwm_e";
  781. function = "pwm_e";
  782. bias-disable;
  783. };
  784. };
  785. pwm_f_x_pins: pwm-f-x {
  786. mux {
  787. groups = "pwm_f_x";
  788. function = "pwm_f";
  789. bias-disable;
  790. };
  791. };
  792. pwm_f_h_pins: pwm-f-h {
  793. mux {
  794. groups = "pwm_f_h";
  795. function = "pwm_f";
  796. bias-disable;
  797. };
  798. };
  799. sdcard_c_pins: sdcard_c {
  800. mux-0 {
  801. groups = "sdcard_d0_c",
  802. "sdcard_d1_c",
  803. "sdcard_d2_c",
  804. "sdcard_d3_c",
  805. "sdcard_cmd_c";
  806. function = "sdcard";
  807. bias-pull-up;
  808. drive-strength-microamp = <4000>;
  809. };
  810. mux-1 {
  811. groups = "sdcard_clk_c";
  812. function = "sdcard";
  813. bias-disable;
  814. drive-strength-microamp = <4000>;
  815. };
  816. };
  817. sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
  818. mux {
  819. groups = "GPIOC_4";
  820. function = "gpio_periphs";
  821. bias-pull-down;
  822. drive-strength-microamp = <4000>;
  823. };
  824. };
  825. sdcard_z_pins: sdcard_z {
  826. mux-0 {
  827. groups = "sdcard_d0_z",
  828. "sdcard_d1_z",
  829. "sdcard_d2_z",
  830. "sdcard_d3_z",
  831. "sdcard_cmd_z";
  832. function = "sdcard";
  833. bias-pull-up;
  834. drive-strength-microamp = <4000>;
  835. };
  836. mux-1 {
  837. groups = "sdcard_clk_z";
  838. function = "sdcard";
  839. bias-disable;
  840. drive-strength-microamp = <4000>;
  841. };
  842. };
  843. sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
  844. mux {
  845. groups = "GPIOZ_6";
  846. function = "gpio_periphs";
  847. bias-pull-down;
  848. drive-strength-microamp = <4000>;
  849. };
  850. };
  851. sdio_pins: sdio {
  852. mux {
  853. groups = "sdio_d0",
  854. "sdio_d1",
  855. "sdio_d2",
  856. "sdio_d3",
  857. "sdio_clk",
  858. "sdio_cmd";
  859. function = "sdio";
  860. bias-disable;
  861. drive-strength-microamp = <4000>;
  862. };
  863. };
  864. sdio_clk_gate_pins: sdio_clk_gate {
  865. mux {
  866. groups = "GPIOX_4";
  867. function = "gpio_periphs";
  868. bias-pull-down;
  869. drive-strength-microamp = <4000>;
  870. };
  871. };
  872. spdif_in_a10_pins: spdif-in-a10 {
  873. mux {
  874. groups = "spdif_in_a10";
  875. function = "spdif_in";
  876. bias-disable;
  877. };
  878. };
  879. spdif_in_a12_pins: spdif-in-a12 {
  880. mux {
  881. groups = "spdif_in_a12";
  882. function = "spdif_in";
  883. bias-disable;
  884. };
  885. };
  886. spdif_in_h_pins: spdif-in-h {
  887. mux {
  888. groups = "spdif_in_h";
  889. function = "spdif_in";
  890. bias-disable;
  891. };
  892. };
  893. spdif_out_h_pins: spdif-out-h {
  894. mux {
  895. groups = "spdif_out_h";
  896. function = "spdif_out";
  897. drive-strength-microamp = <500>;
  898. bias-disable;
  899. };
  900. };
  901. spdif_out_a11_pins: spdif-out-a11 {
  902. mux {
  903. groups = "spdif_out_a11";
  904. function = "spdif_out";
  905. drive-strength-microamp = <500>;
  906. bias-disable;
  907. };
  908. };
  909. spdif_out_a13_pins: spdif-out-a13 {
  910. mux {
  911. groups = "spdif_out_a13";
  912. function = "spdif_out";
  913. drive-strength-microamp = <500>;
  914. bias-disable;
  915. };
  916. };
  917. spicc0_x_pins: spicc0-x {
  918. mux {
  919. groups = "spi0_mosi_x",
  920. "spi0_miso_x",
  921. "spi0_clk_x";
  922. function = "spi0";
  923. drive-strength-microamp = <4000>;
  924. bias-disable;
  925. };
  926. };
  927. spicc0_ss0_x_pins: spicc0-ss0-x {
  928. mux {
  929. groups = "spi0_ss0_x";
  930. function = "spi0";
  931. drive-strength-microamp = <4000>;
  932. bias-disable;
  933. };
  934. };
  935. spicc0_c_pins: spicc0-c {
  936. mux {
  937. groups = "spi0_mosi_c",
  938. "spi0_miso_c",
  939. "spi0_ss0_c",
  940. "spi0_clk_c";
  941. function = "spi0";
  942. drive-strength-microamp = <4000>;
  943. bias-disable;
  944. };
  945. };
  946. spicc1_pins: spicc1 {
  947. mux {
  948. groups = "spi1_mosi",
  949. "spi1_miso",
  950. "spi1_clk";
  951. function = "spi1";
  952. drive-strength-microamp = <4000>;
  953. };
  954. };
  955. spicc1_ss0_pins: spicc1-ss0 {
  956. mux {
  957. groups = "spi1_ss0";
  958. function = "spi1";
  959. drive-strength-microamp = <4000>;
  960. bias-disable;
  961. };
  962. };
  963. tdm_a_din0_pins: tdm-a-din0 {
  964. mux {
  965. groups = "tdm_a_din0";
  966. function = "tdm_a";
  967. bias-disable;
  968. };
  969. };
  970. tdm_a_din1_pins: tdm-a-din1 {
  971. mux {
  972. groups = "tdm_a_din1";
  973. function = "tdm_a";
  974. bias-disable;
  975. };
  976. };
  977. tdm_a_dout0_pins: tdm-a-dout0 {
  978. mux {
  979. groups = "tdm_a_dout0";
  980. function = "tdm_a";
  981. bias-disable;
  982. drive-strength-microamp = <3000>;
  983. };
  984. };
  985. tdm_a_dout1_pins: tdm-a-dout1 {
  986. mux {
  987. groups = "tdm_a_dout1";
  988. function = "tdm_a";
  989. bias-disable;
  990. drive-strength-microamp = <3000>;
  991. };
  992. };
  993. tdm_a_fs_pins: tdm-a-fs {
  994. mux {
  995. groups = "tdm_a_fs";
  996. function = "tdm_a";
  997. bias-disable;
  998. drive-strength-microamp = <3000>;
  999. };
  1000. };
  1001. tdm_a_sclk_pins: tdm-a-sclk {
  1002. mux {
  1003. groups = "tdm_a_sclk";
  1004. function = "tdm_a";
  1005. bias-disable;
  1006. drive-strength-microamp = <3000>;
  1007. };
  1008. };
  1009. tdm_a_slv_fs_pins: tdm-a-slv-fs {
  1010. mux {
  1011. groups = "tdm_a_slv_fs";
  1012. function = "tdm_a";
  1013. bias-disable;
  1014. };
  1015. };
  1016. tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
  1017. mux {
  1018. groups = "tdm_a_slv_sclk";
  1019. function = "tdm_a";
  1020. bias-disable;
  1021. };
  1022. };
  1023. tdm_b_din0_pins: tdm-b-din0 {
  1024. mux {
  1025. groups = "tdm_b_din0";
  1026. function = "tdm_b";
  1027. bias-disable;
  1028. };
  1029. };
  1030. tdm_b_din1_pins: tdm-b-din1 {
  1031. mux {
  1032. groups = "tdm_b_din1";
  1033. function = "tdm_b";
  1034. bias-disable;
  1035. };
  1036. };
  1037. tdm_b_din2_pins: tdm-b-din2 {
  1038. mux {
  1039. groups = "tdm_b_din2";
  1040. function = "tdm_b";
  1041. bias-disable;
  1042. };
  1043. };
  1044. tdm_b_din3_a_pins: tdm-b-din3-a {
  1045. mux {
  1046. groups = "tdm_b_din3_a";
  1047. function = "tdm_b";
  1048. bias-disable;
  1049. };
  1050. };
  1051. tdm_b_din3_h_pins: tdm-b-din3-h {
  1052. mux {
  1053. groups = "tdm_b_din3_h";
  1054. function = "tdm_b";
  1055. bias-disable;
  1056. };
  1057. };
  1058. tdm_b_dout0_pins: tdm-b-dout0 {
  1059. mux {
  1060. groups = "tdm_b_dout0";
  1061. function = "tdm_b";
  1062. bias-disable;
  1063. drive-strength-microamp = <3000>;
  1064. };
  1065. };
  1066. tdm_b_dout1_pins: tdm-b-dout1 {
  1067. mux {
  1068. groups = "tdm_b_dout1";
  1069. function = "tdm_b";
  1070. bias-disable;
  1071. drive-strength-microamp = <3000>;
  1072. };
  1073. };
  1074. tdm_b_dout2_pins: tdm-b-dout2 {
  1075. mux {
  1076. groups = "tdm_b_dout2";
  1077. function = "tdm_b";
  1078. bias-disable;
  1079. drive-strength-microamp = <3000>;
  1080. };
  1081. };
  1082. tdm_b_dout3_a_pins: tdm-b-dout3-a {
  1083. mux {
  1084. groups = "tdm_b_dout3_a";
  1085. function = "tdm_b";
  1086. bias-disable;
  1087. drive-strength-microamp = <3000>;
  1088. };
  1089. };
  1090. tdm_b_dout3_h_pins: tdm-b-dout3-h {
  1091. mux {
  1092. groups = "tdm_b_dout3_h";
  1093. function = "tdm_b";
  1094. bias-disable;
  1095. drive-strength-microamp = <3000>;
  1096. };
  1097. };
  1098. tdm_b_fs_pins: tdm-b-fs {
  1099. mux {
  1100. groups = "tdm_b_fs";
  1101. function = "tdm_b";
  1102. bias-disable;
  1103. drive-strength-microamp = <3000>;
  1104. };
  1105. };
  1106. tdm_b_sclk_pins: tdm-b-sclk {
  1107. mux {
  1108. groups = "tdm_b_sclk";
  1109. function = "tdm_b";
  1110. bias-disable;
  1111. drive-strength-microamp = <3000>;
  1112. };
  1113. };
  1114. tdm_b_slv_fs_pins: tdm-b-slv-fs {
  1115. mux {
  1116. groups = "tdm_b_slv_fs";
  1117. function = "tdm_b";
  1118. bias-disable;
  1119. };
  1120. };
  1121. tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
  1122. mux {
  1123. groups = "tdm_b_slv_sclk";
  1124. function = "tdm_b";
  1125. bias-disable;
  1126. };
  1127. };
  1128. tdm_c_din0_a_pins: tdm-c-din0-a {
  1129. mux {
  1130. groups = "tdm_c_din0_a";
  1131. function = "tdm_c";
  1132. bias-disable;
  1133. };
  1134. };
  1135. tdm_c_din0_z_pins: tdm-c-din0-z {
  1136. mux {
  1137. groups = "tdm_c_din0_z";
  1138. function = "tdm_c";
  1139. bias-disable;
  1140. };
  1141. };
  1142. tdm_c_din1_a_pins: tdm-c-din1-a {
  1143. mux {
  1144. groups = "tdm_c_din1_a";
  1145. function = "tdm_c";
  1146. bias-disable;
  1147. };
  1148. };
  1149. tdm_c_din1_z_pins: tdm-c-din1-z {
  1150. mux {
  1151. groups = "tdm_c_din1_z";
  1152. function = "tdm_c";
  1153. bias-disable;
  1154. };
  1155. };
  1156. tdm_c_din2_a_pins: tdm-c-din2-a {
  1157. mux {
  1158. groups = "tdm_c_din2_a";
  1159. function = "tdm_c";
  1160. bias-disable;
  1161. };
  1162. };
  1163. eth_leds_pins: eth-leds {
  1164. mux {
  1165. groups = "eth_link_led",
  1166. "eth_act_led";
  1167. function = "eth";
  1168. bias-disable;
  1169. };
  1170. };
  1171. eth_pins: eth {
  1172. mux {
  1173. groups = "eth_mdio",
  1174. "eth_mdc",
  1175. "eth_rgmii_rx_clk",
  1176. "eth_rx_dv",
  1177. "eth_rxd0",
  1178. "eth_rxd1",
  1179. "eth_txen",
  1180. "eth_txd0",
  1181. "eth_txd1";
  1182. function = "eth";
  1183. drive-strength-microamp = <4000>;
  1184. bias-disable;
  1185. };
  1186. };
  1187. eth_rgmii_pins: eth-rgmii {
  1188. mux {
  1189. groups = "eth_rxd2_rgmii",
  1190. "eth_rxd3_rgmii",
  1191. "eth_rgmii_tx_clk",
  1192. "eth_txd2_rgmii",
  1193. "eth_txd3_rgmii";
  1194. function = "eth";
  1195. drive-strength-microamp = <4000>;
  1196. bias-disable;
  1197. };
  1198. };
  1199. tdm_c_din2_z_pins: tdm-c-din2-z {
  1200. mux {
  1201. groups = "tdm_c_din2_z";
  1202. function = "tdm_c";
  1203. bias-disable;
  1204. };
  1205. };
  1206. tdm_c_din3_a_pins: tdm-c-din3-a {
  1207. mux {
  1208. groups = "tdm_c_din3_a";
  1209. function = "tdm_c";
  1210. bias-disable;
  1211. };
  1212. };
  1213. tdm_c_din3_z_pins: tdm-c-din3-z {
  1214. mux {
  1215. groups = "tdm_c_din3_z";
  1216. function = "tdm_c";
  1217. bias-disable;
  1218. };
  1219. };
  1220. tdm_c_dout0_a_pins: tdm-c-dout0-a {
  1221. mux {
  1222. groups = "tdm_c_dout0_a";
  1223. function = "tdm_c";
  1224. bias-disable;
  1225. drive-strength-microamp = <3000>;
  1226. };
  1227. };
  1228. tdm_c_dout0_z_pins: tdm-c-dout0-z {
  1229. mux {
  1230. groups = "tdm_c_dout0_z";
  1231. function = "tdm_c";
  1232. bias-disable;
  1233. drive-strength-microamp = <3000>;
  1234. };
  1235. };
  1236. tdm_c_dout1_a_pins: tdm-c-dout1-a {
  1237. mux {
  1238. groups = "tdm_c_dout1_a";
  1239. function = "tdm_c";
  1240. bias-disable;
  1241. drive-strength-microamp = <3000>;
  1242. };
  1243. };
  1244. tdm_c_dout1_z_pins: tdm-c-dout1-z {
  1245. mux {
  1246. groups = "tdm_c_dout1_z";
  1247. function = "tdm_c";
  1248. bias-disable;
  1249. drive-strength-microamp = <3000>;
  1250. };
  1251. };
  1252. tdm_c_dout2_a_pins: tdm-c-dout2-a {
  1253. mux {
  1254. groups = "tdm_c_dout2_a";
  1255. function = "tdm_c";
  1256. bias-disable;
  1257. drive-strength-microamp = <3000>;
  1258. };
  1259. };
  1260. tdm_c_dout2_z_pins: tdm-c-dout2-z {
  1261. mux {
  1262. groups = "tdm_c_dout2_z";
  1263. function = "tdm_c";
  1264. bias-disable;
  1265. drive-strength-microamp = <3000>;
  1266. };
  1267. };
  1268. tdm_c_dout3_a_pins: tdm-c-dout3-a {
  1269. mux {
  1270. groups = "tdm_c_dout3_a";
  1271. function = "tdm_c";
  1272. bias-disable;
  1273. drive-strength-microamp = <3000>;
  1274. };
  1275. };
  1276. tdm_c_dout3_z_pins: tdm-c-dout3-z {
  1277. mux {
  1278. groups = "tdm_c_dout3_z";
  1279. function = "tdm_c";
  1280. bias-disable;
  1281. drive-strength-microamp = <3000>;
  1282. };
  1283. };
  1284. tdm_c_fs_a_pins: tdm-c-fs-a {
  1285. mux {
  1286. groups = "tdm_c_fs_a";
  1287. function = "tdm_c";
  1288. bias-disable;
  1289. drive-strength-microamp = <3000>;
  1290. };
  1291. };
  1292. tdm_c_fs_z_pins: tdm-c-fs-z {
  1293. mux {
  1294. groups = "tdm_c_fs_z";
  1295. function = "tdm_c";
  1296. bias-disable;
  1297. drive-strength-microamp = <3000>;
  1298. };
  1299. };
  1300. tdm_c_sclk_a_pins: tdm-c-sclk-a {
  1301. mux {
  1302. groups = "tdm_c_sclk_a";
  1303. function = "tdm_c";
  1304. bias-disable;
  1305. drive-strength-microamp = <3000>;
  1306. };
  1307. };
  1308. tdm_c_sclk_z_pins: tdm-c-sclk-z {
  1309. mux {
  1310. groups = "tdm_c_sclk_z";
  1311. function = "tdm_c";
  1312. bias-disable;
  1313. drive-strength-microamp = <3000>;
  1314. };
  1315. };
  1316. tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
  1317. mux {
  1318. groups = "tdm_c_slv_fs_a";
  1319. function = "tdm_c";
  1320. bias-disable;
  1321. };
  1322. };
  1323. tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
  1324. mux {
  1325. groups = "tdm_c_slv_fs_z";
  1326. function = "tdm_c";
  1327. bias-disable;
  1328. };
  1329. };
  1330. tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
  1331. mux {
  1332. groups = "tdm_c_slv_sclk_a";
  1333. function = "tdm_c";
  1334. bias-disable;
  1335. };
  1336. };
  1337. tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
  1338. mux {
  1339. groups = "tdm_c_slv_sclk_z";
  1340. function = "tdm_c";
  1341. bias-disable;
  1342. };
  1343. };
  1344. uart_a_pins: uart-a {
  1345. mux {
  1346. groups = "uart_a_tx",
  1347. "uart_a_rx";
  1348. function = "uart_a";
  1349. bias-disable;
  1350. };
  1351. };
  1352. uart_a_cts_rts_pins: uart-a-cts-rts {
  1353. mux {
  1354. groups = "uart_a_cts",
  1355. "uart_a_rts";
  1356. function = "uart_a";
  1357. bias-disable;
  1358. };
  1359. };
  1360. uart_b_pins: uart-b {
  1361. mux {
  1362. groups = "uart_b_tx",
  1363. "uart_b_rx";
  1364. function = "uart_b";
  1365. bias-disable;
  1366. };
  1367. };
  1368. uart_c_pins: uart-c {
  1369. mux {
  1370. groups = "uart_c_tx",
  1371. "uart_c_rx";
  1372. function = "uart_c";
  1373. bias-disable;
  1374. };
  1375. };
  1376. uart_c_cts_rts_pins: uart-c-cts-rts {
  1377. mux {
  1378. groups = "uart_c_cts",
  1379. "uart_c_rts";
  1380. function = "uart_c";
  1381. bias-disable;
  1382. };
  1383. };
  1384. };
  1385. };
  1386. cpu_temp: temperature-sensor@34800 {
  1387. compatible = "amlogic,g12a-cpu-thermal",
  1388. "amlogic,g12a-thermal";
  1389. reg = <0x0 0x34800 0x0 0x50>;
  1390. interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
  1391. clocks = <&clkc CLKID_TS>;
  1392. #thermal-sensor-cells = <0>;
  1393. amlogic,ao-secure = <&sec_AO>;
  1394. };
  1395. ddr_temp: temperature-sensor@34c00 {
  1396. compatible = "amlogic,g12a-ddr-thermal",
  1397. "amlogic,g12a-thermal";
  1398. reg = <0x0 0x34c00 0x0 0x50>;
  1399. interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
  1400. clocks = <&clkc CLKID_TS>;
  1401. #thermal-sensor-cells = <0>;
  1402. amlogic,ao-secure = <&sec_AO>;
  1403. };
  1404. usb2_phy0: phy@36000 {
  1405. compatible = "amlogic,g12a-usb2-phy";
  1406. reg = <0x0 0x36000 0x0 0x2000>;
  1407. clocks = <&xtal>;
  1408. clock-names = "xtal";
  1409. resets = <&reset RESET_USB_PHY20>;
  1410. reset-names = "phy";
  1411. #phy-cells = <0>;
  1412. };
  1413. dmc: bus@38000 {
  1414. compatible = "simple-bus";
  1415. reg = <0x0 0x38000 0x0 0x400>;
  1416. #address-cells = <2>;
  1417. #size-cells = <2>;
  1418. ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
  1419. canvas: video-lut@48 {
  1420. compatible = "amlogic,canvas";
  1421. reg = <0x0 0x48 0x0 0x14>;
  1422. };
  1423. };
  1424. usb2_phy1: phy@3a000 {
  1425. compatible = "amlogic,g12a-usb2-phy";
  1426. reg = <0x0 0x3a000 0x0 0x2000>;
  1427. clocks = <&xtal>;
  1428. clock-names = "xtal";
  1429. resets = <&reset RESET_USB_PHY21>;
  1430. reset-names = "phy";
  1431. #phy-cells = <0>;
  1432. };
  1433. hiu: bus@3c000 {
  1434. compatible = "simple-bus";
  1435. reg = <0x0 0x3c000 0x0 0x1400>;
  1436. #address-cells = <2>;
  1437. #size-cells = <2>;
  1438. ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
  1439. hhi: system-controller@0 {
  1440. compatible = "amlogic,meson-gx-hhi-sysctrl",
  1441. "simple-mfd", "syscon";
  1442. reg = <0 0 0 0x400>;
  1443. clkc: clock-controller {
  1444. compatible = "amlogic,g12a-clkc";
  1445. #clock-cells = <1>;
  1446. clocks = <&xtal>;
  1447. clock-names = "xtal";
  1448. };
  1449. pwrc: power-controller {
  1450. compatible = "amlogic,meson-g12a-pwrc";
  1451. #power-domain-cells = <1>;
  1452. amlogic,ao-sysctrl = <&rti>;
  1453. resets = <&reset RESET_VIU>,
  1454. <&reset RESET_VENC>,
  1455. <&reset RESET_VCBUS>,
  1456. <&reset RESET_BT656>,
  1457. <&reset RESET_RDMA>,
  1458. <&reset RESET_VENCI>,
  1459. <&reset RESET_VENCP>,
  1460. <&reset RESET_VDAC>,
  1461. <&reset RESET_VDI6>,
  1462. <&reset RESET_VENCL>,
  1463. <&reset RESET_VID_LOCK>;
  1464. reset-names = "viu", "venc", "vcbus", "bt656",
  1465. "rdma", "venci", "vencp", "vdac",
  1466. "vdi6", "vencl", "vid_lock";
  1467. clocks = <&clkc CLKID_VPU>,
  1468. <&clkc CLKID_VAPB>;
  1469. clock-names = "vpu", "vapb";
  1470. /*
  1471. * VPU clocking is provided by two identical clock paths
  1472. * VPU_0 and VPU_1 muxed to a single clock by a glitch
  1473. * free mux to safely change frequency while running.
  1474. * Same for VAPB but with a final gate after the glitch free mux.
  1475. */
  1476. assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  1477. <&clkc CLKID_VPU_0>,
  1478. <&clkc CLKID_VPU>, /* Glitch free mux */
  1479. <&clkc CLKID_VAPB_0_SEL>,
  1480. <&clkc CLKID_VAPB_0>,
  1481. <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  1482. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  1483. <0>, /* Do Nothing */
  1484. <&clkc CLKID_VPU_0>,
  1485. <&clkc CLKID_FCLK_DIV4>,
  1486. <0>, /* Do Nothing */
  1487. <&clkc CLKID_VAPB_0>;
  1488. assigned-clock-rates = <0>, /* Do Nothing */
  1489. <666666666>,
  1490. <0>, /* Do Nothing */
  1491. <0>, /* Do Nothing */
  1492. <250000000>,
  1493. <0>; /* Do Nothing */
  1494. };
  1495. };
  1496. };
  1497. usb3_pcie_phy: phy@46000 {
  1498. compatible = "amlogic,g12a-usb3-pcie-phy";
  1499. reg = <0x0 0x46000 0x0 0x2000>;
  1500. clocks = <&clkc CLKID_PCIE_PLL>;
  1501. clock-names = "ref_clk";
  1502. resets = <&reset RESET_PCIE_PHY>;
  1503. reset-names = "phy";
  1504. assigned-clocks = <&clkc CLKID_PCIE_PLL>;
  1505. assigned-clock-rates = <100000000>;
  1506. #phy-cells = <1>;
  1507. };
  1508. eth_phy: mdio-multiplexer@4c000 {
  1509. compatible = "amlogic,g12a-mdio-mux";
  1510. reg = <0x0 0x4c000 0x0 0xa4>;
  1511. clocks = <&clkc CLKID_ETH_PHY>,
  1512. <&xtal>,
  1513. <&clkc CLKID_MPLL_50M>;
  1514. clock-names = "pclk", "clkin0", "clkin1";
  1515. mdio-parent-bus = <&mdio0>;
  1516. #address-cells = <1>;
  1517. #size-cells = <0>;
  1518. ext_mdio: mdio@0 {
  1519. reg = <0>;
  1520. #address-cells = <1>;
  1521. #size-cells = <0>;
  1522. };
  1523. int_mdio: mdio@1 {
  1524. reg = <1>;
  1525. #address-cells = <1>;
  1526. #size-cells = <0>;
  1527. internal_ephy: ethernet_phy@8 {
  1528. compatible = "ethernet-phy-id0180.3301",
  1529. "ethernet-phy-ieee802.3-c22";
  1530. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  1531. reg = <8>;
  1532. max-speed = <100>;
  1533. };
  1534. };
  1535. };
  1536. };
  1537. aobus: bus@ff800000 {
  1538. compatible = "simple-bus";
  1539. reg = <0x0 0xff800000 0x0 0x100000>;
  1540. #address-cells = <2>;
  1541. #size-cells = <2>;
  1542. ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
  1543. rti: sys-ctrl@0 {
  1544. compatible = "amlogic,meson-gx-ao-sysctrl",
  1545. "simple-mfd", "syscon";
  1546. reg = <0x0 0x0 0x0 0x100>;
  1547. #address-cells = <2>;
  1548. #size-cells = <2>;
  1549. ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
  1550. clkc_AO: clock-controller {
  1551. compatible = "amlogic,meson-g12a-aoclkc";
  1552. #clock-cells = <1>;
  1553. #reset-cells = <1>;
  1554. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  1555. clock-names = "xtal", "mpeg-clk";
  1556. };
  1557. ao_pinctrl: pinctrl@14 {
  1558. compatible = "amlogic,meson-g12a-aobus-pinctrl";
  1559. #address-cells = <2>;
  1560. #size-cells = <2>;
  1561. ranges;
  1562. gpio_ao: bank@14 {
  1563. reg = <0x0 0x14 0x0 0x8>,
  1564. <0x0 0x1c 0x0 0x8>,
  1565. <0x0 0x24 0x0 0x14>;
  1566. reg-names = "mux",
  1567. "ds",
  1568. "gpio";
  1569. gpio-controller;
  1570. #gpio-cells = <2>;
  1571. gpio-ranges = <&ao_pinctrl 0 0 15>;
  1572. };
  1573. i2c_ao_sck_pins: i2c_ao_sck_pins {
  1574. mux {
  1575. groups = "i2c_ao_sck";
  1576. function = "i2c_ao";
  1577. bias-disable;
  1578. drive-strength-microamp = <3000>;
  1579. };
  1580. };
  1581. i2c_ao_sda_pins: i2c_ao_sda {
  1582. mux {
  1583. groups = "i2c_ao_sda";
  1584. function = "i2c_ao";
  1585. bias-disable;
  1586. drive-strength-microamp = <3000>;
  1587. };
  1588. };
  1589. i2c_ao_sck_e_pins: i2c_ao_sck_e {
  1590. mux {
  1591. groups = "i2c_ao_sck_e";
  1592. function = "i2c_ao";
  1593. bias-disable;
  1594. drive-strength-microamp = <3000>;
  1595. };
  1596. };
  1597. i2c_ao_sda_e_pins: i2c_ao_sda_e {
  1598. mux {
  1599. groups = "i2c_ao_sda_e";
  1600. function = "i2c_ao";
  1601. bias-disable;
  1602. drive-strength-microamp = <3000>;
  1603. };
  1604. };
  1605. mclk0_ao_pins: mclk0-ao {
  1606. mux {
  1607. groups = "mclk0_ao";
  1608. function = "mclk0_ao";
  1609. bias-disable;
  1610. drive-strength-microamp = <3000>;
  1611. };
  1612. };
  1613. tdm_ao_b_din0_pins: tdm-ao-b-din0 {
  1614. mux {
  1615. groups = "tdm_ao_b_din0";
  1616. function = "tdm_ao_b";
  1617. bias-disable;
  1618. };
  1619. };
  1620. spdif_ao_out_pins: spdif-ao-out {
  1621. mux {
  1622. groups = "spdif_ao_out";
  1623. function = "spdif_ao_out";
  1624. drive-strength-microamp = <500>;
  1625. bias-disable;
  1626. };
  1627. };
  1628. tdm_ao_b_din1_pins: tdm-ao-b-din1 {
  1629. mux {
  1630. groups = "tdm_ao_b_din1";
  1631. function = "tdm_ao_b";
  1632. bias-disable;
  1633. };
  1634. };
  1635. tdm_ao_b_din2_pins: tdm-ao-b-din2 {
  1636. mux {
  1637. groups = "tdm_ao_b_din2";
  1638. function = "tdm_ao_b";
  1639. bias-disable;
  1640. };
  1641. };
  1642. tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
  1643. mux {
  1644. groups = "tdm_ao_b_dout0";
  1645. function = "tdm_ao_b";
  1646. bias-disable;
  1647. drive-strength-microamp = <3000>;
  1648. };
  1649. };
  1650. tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
  1651. mux {
  1652. groups = "tdm_ao_b_dout1";
  1653. function = "tdm_ao_b";
  1654. bias-disable;
  1655. drive-strength-microamp = <3000>;
  1656. };
  1657. };
  1658. tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
  1659. mux {
  1660. groups = "tdm_ao_b_dout2";
  1661. function = "tdm_ao_b";
  1662. bias-disable;
  1663. drive-strength-microamp = <3000>;
  1664. };
  1665. };
  1666. tdm_ao_b_fs_pins: tdm-ao-b-fs {
  1667. mux {
  1668. groups = "tdm_ao_b_fs";
  1669. function = "tdm_ao_b";
  1670. bias-disable;
  1671. drive-strength-microamp = <3000>;
  1672. };
  1673. };
  1674. tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
  1675. mux {
  1676. groups = "tdm_ao_b_sclk";
  1677. function = "tdm_ao_b";
  1678. bias-disable;
  1679. drive-strength-microamp = <3000>;
  1680. };
  1681. };
  1682. tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
  1683. mux {
  1684. groups = "tdm_ao_b_slv_fs";
  1685. function = "tdm_ao_b";
  1686. bias-disable;
  1687. };
  1688. };
  1689. tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
  1690. mux {
  1691. groups = "tdm_ao_b_slv_sclk";
  1692. function = "tdm_ao_b";
  1693. bias-disable;
  1694. };
  1695. };
  1696. uart_ao_a_pins: uart-a-ao {
  1697. mux {
  1698. groups = "uart_ao_a_tx",
  1699. "uart_ao_a_rx";
  1700. function = "uart_ao_a";
  1701. bias-disable;
  1702. };
  1703. };
  1704. uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
  1705. mux {
  1706. groups = "uart_ao_a_cts",
  1707. "uart_ao_a_rts";
  1708. function = "uart_ao_a";
  1709. bias-disable;
  1710. };
  1711. };
  1712. pwm_a_e_pins: pwm-a-e {
  1713. mux {
  1714. groups = "pwm_a_e";
  1715. function = "pwm_a_e";
  1716. bias-disable;
  1717. };
  1718. };
  1719. pwm_ao_a_pins: pwm-ao-a {
  1720. mux {
  1721. groups = "pwm_ao_a";
  1722. function = "pwm_ao_a";
  1723. bias-disable;
  1724. };
  1725. };
  1726. pwm_ao_b_pins: pwm-ao-b {
  1727. mux {
  1728. groups = "pwm_ao_b";
  1729. function = "pwm_ao_b";
  1730. bias-disable;
  1731. };
  1732. };
  1733. pwm_ao_c_4_pins: pwm-ao-c-4 {
  1734. mux {
  1735. groups = "pwm_ao_c_4";
  1736. function = "pwm_ao_c";
  1737. bias-disable;
  1738. };
  1739. };
  1740. pwm_ao_c_6_pins: pwm-ao-c-6 {
  1741. mux {
  1742. groups = "pwm_ao_c_6";
  1743. function = "pwm_ao_c";
  1744. bias-disable;
  1745. };
  1746. };
  1747. pwm_ao_d_5_pins: pwm-ao-d-5 {
  1748. mux {
  1749. groups = "pwm_ao_d_5";
  1750. function = "pwm_ao_d";
  1751. bias-disable;
  1752. };
  1753. };
  1754. pwm_ao_d_10_pins: pwm-ao-d-10 {
  1755. mux {
  1756. groups = "pwm_ao_d_10";
  1757. function = "pwm_ao_d";
  1758. bias-disable;
  1759. };
  1760. };
  1761. pwm_ao_d_e_pins: pwm-ao-d-e {
  1762. mux {
  1763. groups = "pwm_ao_d_e";
  1764. function = "pwm_ao_d";
  1765. };
  1766. };
  1767. remote_input_ao_pins: remote-input-ao {
  1768. mux {
  1769. groups = "remote_ao_input";
  1770. function = "remote_ao_input";
  1771. bias-disable;
  1772. };
  1773. };
  1774. };
  1775. };
  1776. vrtc: rtc@0a8 {
  1777. compatible = "amlogic,meson-vrtc";
  1778. reg = <0x0 0x000a8 0x0 0x4>;
  1779. };
  1780. cec_AO: cec@100 {
  1781. compatible = "amlogic,meson-gx-ao-cec";
  1782. reg = <0x0 0x00100 0x0 0x14>;
  1783. interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
  1784. clocks = <&clkc_AO CLKID_AO_CEC>;
  1785. clock-names = "core";
  1786. status = "disabled";
  1787. };
  1788. sec_AO: ao-secure@140 {
  1789. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  1790. reg = <0x0 0x140 0x0 0x140>;
  1791. amlogic,has-chip-id;
  1792. };
  1793. cecb_AO: cec@280 {
  1794. compatible = "amlogic,meson-g12a-ao-cec";
  1795. reg = <0x0 0x00280 0x0 0x1c>;
  1796. interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
  1797. clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
  1798. clock-names = "oscin";
  1799. status = "disabled";
  1800. };
  1801. pwm_AO_cd: pwm@2000 {
  1802. compatible = "amlogic,meson-g12a-ao-pwm-cd";
  1803. reg = <0x0 0x2000 0x0 0x20>;
  1804. #pwm-cells = <3>;
  1805. status = "disabled";
  1806. };
  1807. uart_AO: serial@3000 {
  1808. compatible = "amlogic,meson-gx-uart",
  1809. "amlogic,meson-ao-uart";
  1810. reg = <0x0 0x3000 0x0 0x18>;
  1811. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  1812. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
  1813. clock-names = "xtal", "pclk", "baud";
  1814. status = "disabled";
  1815. };
  1816. uart_AO_B: serial@4000 {
  1817. compatible = "amlogic,meson-gx-uart",
  1818. "amlogic,meson-ao-uart";
  1819. reg = <0x0 0x4000 0x0 0x18>;
  1820. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  1821. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  1822. clock-names = "xtal", "pclk", "baud";
  1823. status = "disabled";
  1824. };
  1825. i2c_AO: i2c@5000 {
  1826. compatible = "amlogic,meson-axg-i2c";
  1827. status = "disabled";
  1828. reg = <0x0 0x05000 0x0 0x20>;
  1829. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  1830. #address-cells = <1>;
  1831. #size-cells = <0>;
  1832. clocks = <&clkc CLKID_I2C>;
  1833. };
  1834. pwm_AO_ab: pwm@7000 {
  1835. compatible = "amlogic,meson-g12a-ao-pwm-ab";
  1836. reg = <0x0 0x7000 0x0 0x20>;
  1837. #pwm-cells = <3>;
  1838. status = "disabled";
  1839. };
  1840. ir: ir@8000 {
  1841. compatible = "amlogic,meson-gxbb-ir";
  1842. reg = <0x0 0x8000 0x0 0x20>;
  1843. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  1844. status = "disabled";
  1845. };
  1846. saradc: adc@9000 {
  1847. compatible = "amlogic,meson-g12a-saradc",
  1848. "amlogic,meson-saradc";
  1849. reg = <0x0 0x9000 0x0 0x48>;
  1850. #io-channel-cells = <1>;
  1851. interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
  1852. clocks = <&xtal>,
  1853. <&clkc_AO CLKID_AO_SAR_ADC>,
  1854. <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
  1855. <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
  1856. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  1857. status = "disabled";
  1858. };
  1859. };
  1860. vdec: video-decoder@ff620000 {
  1861. compatible = "amlogic,g12a-vdec";
  1862. reg = <0x0 0xff620000 0x0 0x10000>,
  1863. <0x0 0xffd0e180 0x0 0xe4>;
  1864. reg-names = "dos", "esparser";
  1865. interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
  1866. <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
  1867. interrupt-names = "vdec", "esparser";
  1868. amlogic,ao-sysctrl = <&rti>;
  1869. amlogic,canvas = <&canvas>;
  1870. clocks = <&clkc CLKID_PARSER>,
  1871. <&clkc CLKID_DOS>,
  1872. <&clkc CLKID_VDEC_1>,
  1873. <&clkc CLKID_VDEC_HEVC>,
  1874. <&clkc CLKID_VDEC_HEVCF>;
  1875. clock-names = "dos_parser", "dos", "vdec_1",
  1876. "vdec_hevc", "vdec_hevcf";
  1877. resets = <&reset RESET_PARSER>;
  1878. reset-names = "esparser";
  1879. };
  1880. vpu: vpu@ff900000 {
  1881. compatible = "amlogic,meson-g12a-vpu";
  1882. reg = <0x0 0xff900000 0x0 0x100000>,
  1883. <0x0 0xff63c000 0x0 0x1000>;
  1884. reg-names = "vpu", "hhi";
  1885. interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  1886. #address-cells = <1>;
  1887. #size-cells = <0>;
  1888. amlogic,canvas = <&canvas>;
  1889. /* CVBS VDAC output port */
  1890. cvbs_vdac_port: port@0 {
  1891. reg = <0>;
  1892. };
  1893. /* HDMI-TX output port */
  1894. hdmi_tx_port: port@1 {
  1895. reg = <1>;
  1896. hdmi_tx_out: endpoint {
  1897. remote-endpoint = <&hdmi_tx_in>;
  1898. };
  1899. };
  1900. };
  1901. gic: interrupt-controller@ffc01000 {
  1902. compatible = "arm,gic-400";
  1903. reg = <0x0 0xffc01000 0 0x1000>,
  1904. <0x0 0xffc02000 0 0x2000>,
  1905. <0x0 0xffc04000 0 0x2000>,
  1906. <0x0 0xffc06000 0 0x2000>;
  1907. interrupt-controller;
  1908. interrupts = <GIC_PPI 9
  1909. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  1910. #interrupt-cells = <3>;
  1911. #address-cells = <0>;
  1912. };
  1913. cbus: bus@ffd00000 {
  1914. compatible = "simple-bus";
  1915. reg = <0x0 0xffd00000 0x0 0x100000>;
  1916. #address-cells = <2>;
  1917. #size-cells = <2>;
  1918. ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
  1919. reset: reset-controller@1004 {
  1920. compatible = "amlogic,meson-axg-reset";
  1921. reg = <0x0 0x1004 0x0 0x9c>;
  1922. #reset-cells = <1>;
  1923. };
  1924. gpio_intc: interrupt-controller@f080 {
  1925. compatible = "amlogic,meson-g12a-gpio-intc",
  1926. "amlogic,meson-gpio-intc";
  1927. reg = <0x0 0xf080 0x0 0x10>;
  1928. interrupt-controller;
  1929. #interrupt-cells = <2>;
  1930. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  1931. };
  1932. spicc0: spi@13000 {
  1933. compatible = "amlogic,meson-g12a-spicc";
  1934. reg = <0x0 0x13000 0x0 0x44>;
  1935. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  1936. clocks = <&clkc CLKID_SPICC0>,
  1937. <&clkc CLKID_SPICC0_SCLK>;
  1938. clock-names = "core", "pclk";
  1939. #address-cells = <1>;
  1940. #size-cells = <0>;
  1941. status = "disabled";
  1942. };
  1943. spicc1: spi@15000 {
  1944. compatible = "amlogic,meson-g12a-spicc";
  1945. reg = <0x0 0x15000 0x0 0x44>;
  1946. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  1947. clocks = <&clkc CLKID_SPICC1>,
  1948. <&clkc CLKID_SPICC1_SCLK>;
  1949. clock-names = "core", "pclk";
  1950. #address-cells = <1>;
  1951. #size-cells = <0>;
  1952. status = "disabled";
  1953. };
  1954. spifc: spi@14000 {
  1955. compatible = "amlogic,meson-gxbb-spifc";
  1956. status = "disabled";
  1957. reg = <0x0 0x14000 0x0 0x80>;
  1958. #address-cells = <1>;
  1959. #size-cells = <0>;
  1960. clocks = <&clkc CLKID_CLK81>;
  1961. };
  1962. pwm_ef: pwm@19000 {
  1963. compatible = "amlogic,meson-g12a-ee-pwm";
  1964. reg = <0x0 0x19000 0x0 0x20>;
  1965. #pwm-cells = <3>;
  1966. status = "disabled";
  1967. };
  1968. pwm_cd: pwm@1a000 {
  1969. compatible = "amlogic,meson-g12a-ee-pwm";
  1970. reg = <0x0 0x1a000 0x0 0x20>;
  1971. #pwm-cells = <3>;
  1972. status = "disabled";
  1973. };
  1974. pwm_ab: pwm@1b000 {
  1975. compatible = "amlogic,meson-g12a-ee-pwm";
  1976. reg = <0x0 0x1b000 0x0 0x20>;
  1977. #pwm-cells = <3>;
  1978. status = "disabled";
  1979. };
  1980. i2c3: i2c@1c000 {
  1981. compatible = "amlogic,meson-axg-i2c";
  1982. status = "disabled";
  1983. reg = <0x0 0x1c000 0x0 0x20>;
  1984. interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
  1985. #address-cells = <1>;
  1986. #size-cells = <0>;
  1987. clocks = <&clkc CLKID_I2C>;
  1988. };
  1989. i2c2: i2c@1d000 {
  1990. compatible = "amlogic,meson-axg-i2c";
  1991. status = "disabled";
  1992. reg = <0x0 0x1d000 0x0 0x20>;
  1993. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  1994. #address-cells = <1>;
  1995. #size-cells = <0>;
  1996. clocks = <&clkc CLKID_I2C>;
  1997. };
  1998. i2c1: i2c@1e000 {
  1999. compatible = "amlogic,meson-axg-i2c";
  2000. status = "disabled";
  2001. reg = <0x0 0x1e000 0x0 0x20>;
  2002. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  2003. #address-cells = <1>;
  2004. #size-cells = <0>;
  2005. clocks = <&clkc CLKID_I2C>;
  2006. };
  2007. i2c0: i2c@1f000 {
  2008. compatible = "amlogic,meson-axg-i2c";
  2009. status = "disabled";
  2010. reg = <0x0 0x1f000 0x0 0x20>;
  2011. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  2012. #address-cells = <1>;
  2013. #size-cells = <0>;
  2014. clocks = <&clkc CLKID_I2C>;
  2015. };
  2016. clk_msr: clock-measure@18000 {
  2017. compatible = "amlogic,meson-g12a-clk-measure";
  2018. reg = <0x0 0x18000 0x0 0x10>;
  2019. };
  2020. uart_C: serial@22000 {
  2021. compatible = "amlogic,meson-gx-uart";
  2022. reg = <0x0 0x22000 0x0 0x18>;
  2023. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  2024. clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  2025. clock-names = "xtal", "pclk", "baud";
  2026. status = "disabled";
  2027. };
  2028. uart_B: serial@23000 {
  2029. compatible = "amlogic,meson-gx-uart";
  2030. reg = <0x0 0x23000 0x0 0x18>;
  2031. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  2032. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  2033. clock-names = "xtal", "pclk", "baud";
  2034. status = "disabled";
  2035. };
  2036. uart_A: serial@24000 {
  2037. compatible = "amlogic,meson-gx-uart";
  2038. reg = <0x0 0x24000 0x0 0x18>;
  2039. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  2040. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  2041. clock-names = "xtal", "pclk", "baud";
  2042. status = "disabled";
  2043. };
  2044. };
  2045. sd_emmc_a: sd@ffe03000 {
  2046. compatible = "amlogic,meson-axg-mmc";
  2047. reg = <0x0 0xffe03000 0x0 0x800>;
  2048. interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  2049. status = "disabled";
  2050. clocks = <&clkc CLKID_SD_EMMC_A>,
  2051. <&clkc CLKID_SD_EMMC_A_CLK0>,
  2052. <&clkc CLKID_FCLK_DIV2>;
  2053. clock-names = "core", "clkin0", "clkin1";
  2054. resets = <&reset RESET_SD_EMMC_A>;
  2055. };
  2056. sd_emmc_b: sd@ffe05000 {
  2057. compatible = "amlogic,meson-axg-mmc";
  2058. reg = <0x0 0xffe05000 0x0 0x800>;
  2059. interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
  2060. status = "disabled";
  2061. clocks = <&clkc CLKID_SD_EMMC_B>,
  2062. <&clkc CLKID_SD_EMMC_B_CLK0>,
  2063. <&clkc CLKID_FCLK_DIV2>;
  2064. clock-names = "core", "clkin0", "clkin1";
  2065. resets = <&reset RESET_SD_EMMC_B>;
  2066. };
  2067. sd_emmc_c: mmc@ffe07000 {
  2068. compatible = "amlogic,meson-axg-mmc";
  2069. reg = <0x0 0xffe07000 0x0 0x800>;
  2070. interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
  2071. status = "disabled";
  2072. clocks = <&clkc CLKID_SD_EMMC_C>,
  2073. <&clkc CLKID_SD_EMMC_C_CLK0>,
  2074. <&clkc CLKID_FCLK_DIV2>;
  2075. clock-names = "core", "clkin0", "clkin1";
  2076. resets = <&reset RESET_SD_EMMC_C>;
  2077. };
  2078. usb: usb@ffe09000 {
  2079. status = "disabled";
  2080. compatible = "amlogic,meson-g12a-usb-ctrl";
  2081. reg = <0x0 0xffe09000 0x0 0xa0>;
  2082. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  2083. #address-cells = <2>;
  2084. #size-cells = <2>;
  2085. ranges;
  2086. clocks = <&clkc CLKID_USB>;
  2087. resets = <&reset RESET_USB>;
  2088. dr_mode = "otg";
  2089. phys = <&usb2_phy0>, <&usb2_phy1>,
  2090. <&usb3_pcie_phy PHY_TYPE_USB3>;
  2091. phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
  2092. dwc2: usb@ff400000 {
  2093. compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
  2094. reg = <0x0 0xff400000 0x0 0x40000>;
  2095. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  2096. clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  2097. clock-names = "otg";
  2098. phys = <&usb2_phy1>;
  2099. phy-names = "usb2-phy";
  2100. dr_mode = "peripheral";
  2101. g-rx-fifo-size = <192>;
  2102. g-np-tx-fifo-size = <128>;
  2103. g-tx-fifo-size = <128 128 16 16 16>;
  2104. };
  2105. dwc3: usb@ff500000 {
  2106. compatible = "snps,dwc3";
  2107. reg = <0x0 0xff500000 0x0 0x100000>;
  2108. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  2109. dr_mode = "host";
  2110. snps,dis_u2_susphy_quirk;
  2111. snps,quirk-frame-length-adjustment;
  2112. snps,parkmode-disable-ss-quirk;
  2113. };
  2114. };
  2115. mali: gpu@ffe40000 {
  2116. compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
  2117. reg = <0x0 0xffe40000 0x0 0x40000>;
  2118. interrupt-parent = <&gic>;
  2119. interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  2120. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  2121. <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
  2122. interrupt-names = "job", "mmu", "gpu";
  2123. clocks = <&clkc CLKID_MALI>;
  2124. resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
  2125. operating-points-v2 = <&gpu_opp_table>;
  2126. #cooling-cells = <2>;
  2127. };
  2128. };
  2129. timer {
  2130. compatible = "arm,armv8-timer";
  2131. interrupts = <GIC_PPI 13
  2132. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2133. <GIC_PPI 14
  2134. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2135. <GIC_PPI 11
  2136. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2137. <GIC_PPI 10
  2138. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  2139. arm,no-tick-in-suspend;
  2140. };
  2141. xtal: xtal-clk {
  2142. compatible = "fixed-clock";
  2143. clock-frequency = <24000000>;
  2144. clock-output-names = "xtal";
  2145. #clock-cells = <0>;
  2146. };
  2147. };