meson-axg.dtsi 38 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
  4. */
  5. #include <dt-bindings/clock/axg-aoclkc.h>
  6. #include <dt-bindings/clock/axg-audio-clkc.h>
  7. #include <dt-bindings/clock/axg-clkc.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include <dt-bindings/gpio/meson-axg-gpio.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include <dt-bindings/interrupt-controller/arm-gic.h>
  12. #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
  13. #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  14. / {
  15. compatible = "amlogic,meson-axg";
  16. interrupt-parent = <&gic>;
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19. tdmif_a: audio-controller-0 {
  20. compatible = "amlogic,axg-tdm-iface";
  21. #sound-dai-cells = <0>;
  22. sound-name-prefix = "TDM_A";
  23. clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
  24. <&clkc_audio AUD_CLKID_MST_A_SCLK>,
  25. <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
  26. clock-names = "mclk", "sclk", "lrclk";
  27. status = "disabled";
  28. };
  29. tdmif_b: audio-controller-1 {
  30. compatible = "amlogic,axg-tdm-iface";
  31. #sound-dai-cells = <0>;
  32. sound-name-prefix = "TDM_B";
  33. clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
  34. <&clkc_audio AUD_CLKID_MST_B_SCLK>,
  35. <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
  36. clock-names = "mclk", "sclk", "lrclk";
  37. status = "disabled";
  38. };
  39. tdmif_c: audio-controller-2 {
  40. compatible = "amlogic,axg-tdm-iface";
  41. #sound-dai-cells = <0>;
  42. sound-name-prefix = "TDM_C";
  43. clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
  44. <&clkc_audio AUD_CLKID_MST_C_SCLK>,
  45. <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
  46. clock-names = "mclk", "sclk", "lrclk";
  47. status = "disabled";
  48. };
  49. arm-pmu {
  50. compatible = "arm,cortex-a53-pmu";
  51. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  52. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  53. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  54. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  55. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  56. };
  57. cpus {
  58. #address-cells = <0x2>;
  59. #size-cells = <0x0>;
  60. cpu0: cpu@0 {
  61. device_type = "cpu";
  62. compatible = "arm,cortex-a53";
  63. reg = <0x0 0x0>;
  64. enable-method = "psci";
  65. next-level-cache = <&l2>;
  66. clocks = <&scpi_dvfs 0>;
  67. };
  68. cpu1: cpu@1 {
  69. device_type = "cpu";
  70. compatible = "arm,cortex-a53";
  71. reg = <0x0 0x1>;
  72. enable-method = "psci";
  73. next-level-cache = <&l2>;
  74. clocks = <&scpi_dvfs 0>;
  75. };
  76. cpu2: cpu@2 {
  77. device_type = "cpu";
  78. compatible = "arm,cortex-a53";
  79. reg = <0x0 0x2>;
  80. enable-method = "psci";
  81. next-level-cache = <&l2>;
  82. clocks = <&scpi_dvfs 0>;
  83. };
  84. cpu3: cpu@3 {
  85. device_type = "cpu";
  86. compatible = "arm,cortex-a53";
  87. reg = <0x0 0x3>;
  88. enable-method = "psci";
  89. next-level-cache = <&l2>;
  90. clocks = <&scpi_dvfs 0>;
  91. };
  92. l2: l2-cache0 {
  93. compatible = "cache";
  94. };
  95. };
  96. sm: secure-monitor {
  97. compatible = "amlogic,meson-gxbb-sm";
  98. };
  99. efuse: efuse {
  100. compatible = "amlogic,meson-gxbb-efuse";
  101. clocks = <&clkc CLKID_EFUSE>;
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. read-only;
  105. secure-monitor = <&sm>;
  106. };
  107. psci {
  108. compatible = "arm,psci-1.0";
  109. method = "smc";
  110. };
  111. reserved-memory {
  112. #address-cells = <2>;
  113. #size-cells = <2>;
  114. ranges;
  115. /* 16 MiB reserved for Hardware ROM Firmware */
  116. hwrom_reserved: hwrom@0 {
  117. reg = <0x0 0x0 0x0 0x1000000>;
  118. no-map;
  119. };
  120. /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  121. secmon_reserved: secmon@5000000 {
  122. reg = <0x0 0x05000000 0x0 0x300000>;
  123. no-map;
  124. };
  125. };
  126. scpi {
  127. compatible = "arm,scpi-pre-1.0";
  128. mboxes = <&mailbox 1 &mailbox 2>;
  129. shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
  130. scpi_clocks: clocks {
  131. compatible = "arm,scpi-clocks";
  132. scpi_dvfs: clock-controller {
  133. compatible = "arm,scpi-dvfs-clocks";
  134. #clock-cells = <1>;
  135. clock-indices = <0>;
  136. clock-output-names = "vcpu";
  137. };
  138. };
  139. scpi_sensors: sensors {
  140. compatible = "amlogic,meson-gxbb-scpi-sensors";
  141. #thermal-sensor-cells = <1>;
  142. };
  143. };
  144. soc {
  145. compatible = "simple-bus";
  146. #address-cells = <2>;
  147. #size-cells = <2>;
  148. ranges;
  149. ethmac: ethernet@ff3f0000 {
  150. compatible = "amlogic,meson-axg-dwmac",
  151. "snps,dwmac-3.70a",
  152. "snps,dwmac";
  153. reg = <0x0 0xff3f0000 0x0 0x10000>,
  154. <0x0 0xff634540 0x0 0x8>;
  155. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  156. interrupt-names = "macirq";
  157. clocks = <&clkc CLKID_ETH>,
  158. <&clkc CLKID_FCLK_DIV2>,
  159. <&clkc CLKID_MPLL2>;
  160. clock-names = "stmmaceth", "clkin0", "clkin1";
  161. rx-fifo-depth = <4096>;
  162. tx-fifo-depth = <2048>;
  163. status = "disabled";
  164. };
  165. pdm: audio-controller@ff632000 {
  166. compatible = "amlogic,axg-pdm";
  167. reg = <0x0 0xff632000 0x0 0x34>;
  168. #sound-dai-cells = <0>;
  169. sound-name-prefix = "PDM";
  170. clocks = <&clkc_audio AUD_CLKID_PDM>,
  171. <&clkc_audio AUD_CLKID_PDM_DCLK>,
  172. <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
  173. clock-names = "pclk", "dclk", "sysclk";
  174. status = "disabled";
  175. };
  176. periphs: bus@ff634000 {
  177. compatible = "simple-bus";
  178. reg = <0x0 0xff634000 0x0 0x2000>;
  179. #address-cells = <2>;
  180. #size-cells = <2>;
  181. ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
  182. hwrng: rng@18 {
  183. compatible = "amlogic,meson-rng";
  184. reg = <0x0 0x18 0x0 0x4>;
  185. clocks = <&clkc CLKID_RNG0>;
  186. clock-names = "core";
  187. };
  188. pinctrl_periphs: pinctrl@480 {
  189. compatible = "amlogic,meson-axg-periphs-pinctrl";
  190. #address-cells = <2>;
  191. #size-cells = <2>;
  192. ranges;
  193. gpio: bank@480 {
  194. reg = <0x0 0x00480 0x0 0x40>,
  195. <0x0 0x004e8 0x0 0x14>,
  196. <0x0 0x00520 0x0 0x14>,
  197. <0x0 0x00430 0x0 0x3c>;
  198. reg-names = "mux", "pull", "pull-enable", "gpio";
  199. gpio-controller;
  200. #gpio-cells = <2>;
  201. gpio-ranges = <&pinctrl_periphs 0 0 86>;
  202. };
  203. i2c0_pins: i2c0 {
  204. mux {
  205. groups = "i2c0_sck",
  206. "i2c0_sda";
  207. function = "i2c0";
  208. bias-disable;
  209. };
  210. };
  211. i2c1_x_pins: i2c1_x {
  212. mux {
  213. groups = "i2c1_sck_x",
  214. "i2c1_sda_x";
  215. function = "i2c1";
  216. bias-disable;
  217. };
  218. };
  219. i2c1_z_pins: i2c1_z {
  220. mux {
  221. groups = "i2c1_sck_z",
  222. "i2c1_sda_z";
  223. function = "i2c1";
  224. bias-disable;
  225. };
  226. };
  227. i2c2_a_pins: i2c2_a {
  228. mux {
  229. groups = "i2c2_sck_a",
  230. "i2c2_sda_a";
  231. function = "i2c2";
  232. bias-disable;
  233. };
  234. };
  235. i2c2_x_pins: i2c2_x {
  236. mux {
  237. groups = "i2c2_sck_x",
  238. "i2c2_sda_x";
  239. function = "i2c2";
  240. bias-disable;
  241. };
  242. };
  243. i2c3_a6_pins: i2c3_a6 {
  244. mux {
  245. groups = "i2c3_sda_a6",
  246. "i2c3_sck_a7";
  247. function = "i2c3";
  248. bias-disable;
  249. };
  250. };
  251. i2c3_a12_pins: i2c3_a12 {
  252. mux {
  253. groups = "i2c3_sda_a12",
  254. "i2c3_sck_a13";
  255. function = "i2c3";
  256. bias-disable;
  257. };
  258. };
  259. i2c3_a19_pins: i2c3_a19 {
  260. mux {
  261. groups = "i2c3_sda_a19",
  262. "i2c3_sck_a20";
  263. function = "i2c3";
  264. bias-disable;
  265. };
  266. };
  267. emmc_pins: emmc {
  268. mux-0 {
  269. groups = "emmc_nand_d0",
  270. "emmc_nand_d1",
  271. "emmc_nand_d2",
  272. "emmc_nand_d3",
  273. "emmc_nand_d4",
  274. "emmc_nand_d5",
  275. "emmc_nand_d6",
  276. "emmc_nand_d7",
  277. "emmc_cmd";
  278. function = "emmc";
  279. bias-pull-up;
  280. };
  281. mux-1 {
  282. groups = "emmc_clk";
  283. function = "emmc";
  284. bias-disable;
  285. };
  286. };
  287. emmc_ds_pins: emmc_ds {
  288. mux {
  289. groups = "emmc_ds";
  290. function = "emmc";
  291. bias-pull-down;
  292. };
  293. };
  294. emmc_clk_gate_pins: emmc_clk_gate {
  295. mux {
  296. groups = "BOOT_8";
  297. function = "gpio_periphs";
  298. bias-pull-down;
  299. };
  300. };
  301. eth_rgmii_x_pins: eth-x-rgmii {
  302. mux {
  303. groups = "eth_mdio_x",
  304. "eth_mdc_x",
  305. "eth_rgmii_rx_clk_x",
  306. "eth_rx_dv_x",
  307. "eth_rxd0_x",
  308. "eth_rxd1_x",
  309. "eth_rxd2_rgmii",
  310. "eth_rxd3_rgmii",
  311. "eth_rgmii_tx_clk",
  312. "eth_txen_x",
  313. "eth_txd0_x",
  314. "eth_txd1_x",
  315. "eth_txd2_rgmii",
  316. "eth_txd3_rgmii";
  317. function = "eth";
  318. bias-disable;
  319. };
  320. };
  321. eth_rgmii_y_pins: eth-y-rgmii {
  322. mux {
  323. groups = "eth_mdio_y",
  324. "eth_mdc_y",
  325. "eth_rgmii_rx_clk_y",
  326. "eth_rx_dv_y",
  327. "eth_rxd0_y",
  328. "eth_rxd1_y",
  329. "eth_rxd2_rgmii",
  330. "eth_rxd3_rgmii",
  331. "eth_rgmii_tx_clk",
  332. "eth_txen_y",
  333. "eth_txd0_y",
  334. "eth_txd1_y",
  335. "eth_txd2_rgmii",
  336. "eth_txd3_rgmii";
  337. function = "eth";
  338. bias-disable;
  339. };
  340. };
  341. eth_rmii_x_pins: eth-x-rmii {
  342. mux {
  343. groups = "eth_mdio_x",
  344. "eth_mdc_x",
  345. "eth_rgmii_rx_clk_x",
  346. "eth_rx_dv_x",
  347. "eth_rxd0_x",
  348. "eth_rxd1_x",
  349. "eth_txen_x",
  350. "eth_txd0_x",
  351. "eth_txd1_x";
  352. function = "eth";
  353. bias-disable;
  354. };
  355. };
  356. eth_rmii_y_pins: eth-y-rmii {
  357. mux {
  358. groups = "eth_mdio_y",
  359. "eth_mdc_y",
  360. "eth_rgmii_rx_clk_y",
  361. "eth_rx_dv_y",
  362. "eth_rxd0_y",
  363. "eth_rxd1_y",
  364. "eth_txen_y",
  365. "eth_txd0_y",
  366. "eth_txd1_y";
  367. function = "eth";
  368. bias-disable;
  369. };
  370. };
  371. mclk_b_pins: mclk_b {
  372. mux {
  373. groups = "mclk_b";
  374. function = "mclk_b";
  375. bias-disable;
  376. };
  377. };
  378. mclk_c_pins: mclk_c {
  379. mux {
  380. groups = "mclk_c";
  381. function = "mclk_c";
  382. bias-disable;
  383. };
  384. };
  385. pdm_dclk_a14_pins: pdm_dclk_a14 {
  386. mux {
  387. groups = "pdm_dclk_a14";
  388. function = "pdm";
  389. bias-disable;
  390. };
  391. };
  392. pdm_dclk_a19_pins: pdm_dclk_a19 {
  393. mux {
  394. groups = "pdm_dclk_a19";
  395. function = "pdm";
  396. bias-disable;
  397. };
  398. };
  399. pdm_din0_pins: pdm_din0 {
  400. mux {
  401. groups = "pdm_din0";
  402. function = "pdm";
  403. bias-disable;
  404. };
  405. };
  406. pdm_din1_pins: pdm_din1 {
  407. mux {
  408. groups = "pdm_din1";
  409. function = "pdm";
  410. bias-disable;
  411. };
  412. };
  413. pdm_din2_pins: pdm_din2 {
  414. mux {
  415. groups = "pdm_din2";
  416. function = "pdm";
  417. bias-disable;
  418. };
  419. };
  420. pdm_din3_pins: pdm_din3 {
  421. mux {
  422. groups = "pdm_din3";
  423. function = "pdm";
  424. bias-disable;
  425. };
  426. };
  427. pwm_a_a_pins: pwm_a_a {
  428. mux {
  429. groups = "pwm_a_a";
  430. function = "pwm_a";
  431. bias-disable;
  432. };
  433. };
  434. pwm_a_x18_pins: pwm_a_x18 {
  435. mux {
  436. groups = "pwm_a_x18";
  437. function = "pwm_a";
  438. bias-disable;
  439. };
  440. };
  441. pwm_a_x20_pins: pwm_a_x20 {
  442. mux {
  443. groups = "pwm_a_x20";
  444. function = "pwm_a";
  445. bias-disable;
  446. };
  447. };
  448. pwm_a_z_pins: pwm_a_z {
  449. mux {
  450. groups = "pwm_a_z";
  451. function = "pwm_a";
  452. bias-disable;
  453. };
  454. };
  455. pwm_b_a_pins: pwm_b_a {
  456. mux {
  457. groups = "pwm_b_a";
  458. function = "pwm_b";
  459. bias-disable;
  460. };
  461. };
  462. pwm_b_x_pins: pwm_b_x {
  463. mux {
  464. groups = "pwm_b_x";
  465. function = "pwm_b";
  466. bias-disable;
  467. };
  468. };
  469. pwm_b_z_pins: pwm_b_z {
  470. mux {
  471. groups = "pwm_b_z";
  472. function = "pwm_b";
  473. bias-disable;
  474. };
  475. };
  476. pwm_c_a_pins: pwm_c_a {
  477. mux {
  478. groups = "pwm_c_a";
  479. function = "pwm_c";
  480. bias-disable;
  481. };
  482. };
  483. pwm_c_x10_pins: pwm_c_x10 {
  484. mux {
  485. groups = "pwm_c_x10";
  486. function = "pwm_c";
  487. bias-disable;
  488. };
  489. };
  490. pwm_c_x17_pins: pwm_c_x17 {
  491. mux {
  492. groups = "pwm_c_x17";
  493. function = "pwm_c";
  494. bias-disable;
  495. };
  496. };
  497. pwm_d_x11_pins: pwm_d_x11 {
  498. mux {
  499. groups = "pwm_d_x11";
  500. function = "pwm_d";
  501. bias-disable;
  502. };
  503. };
  504. pwm_d_x16_pins: pwm_d_x16 {
  505. mux {
  506. groups = "pwm_d_x16";
  507. function = "pwm_d";
  508. bias-disable;
  509. };
  510. };
  511. sdio_pins: sdio {
  512. mux-0 {
  513. groups = "sdio_d0",
  514. "sdio_d1",
  515. "sdio_d2",
  516. "sdio_d3",
  517. "sdio_cmd";
  518. function = "sdio";
  519. bias-pull-up;
  520. };
  521. mux-1 {
  522. groups = "sdio_clk";
  523. function = "sdio";
  524. bias-disable;
  525. };
  526. };
  527. sdio_clk_gate_pins: sdio_clk_gate {
  528. mux {
  529. groups = "GPIOX_4";
  530. function = "gpio_periphs";
  531. bias-pull-down;
  532. };
  533. };
  534. spdif_in_z_pins: spdif_in_z {
  535. mux {
  536. groups = "spdif_in_z";
  537. function = "spdif_in";
  538. bias-disable;
  539. };
  540. };
  541. spdif_in_a1_pins: spdif_in_a1 {
  542. mux {
  543. groups = "spdif_in_a1";
  544. function = "spdif_in";
  545. bias-disable;
  546. };
  547. };
  548. spdif_in_a7_pins: spdif_in_a7 {
  549. mux {
  550. groups = "spdif_in_a7";
  551. function = "spdif_in";
  552. bias-disable;
  553. };
  554. };
  555. spdif_in_a19_pins: spdif_in_a19 {
  556. mux {
  557. groups = "spdif_in_a19";
  558. function = "spdif_in";
  559. bias-disable;
  560. };
  561. };
  562. spdif_in_a20_pins: spdif_in_a20 {
  563. mux {
  564. groups = "spdif_in_a20";
  565. function = "spdif_in";
  566. bias-disable;
  567. };
  568. };
  569. spdif_out_a1_pins: spdif_out_a1 {
  570. mux {
  571. groups = "spdif_out_a1";
  572. function = "spdif_out";
  573. bias-disable;
  574. };
  575. };
  576. spdif_out_a11_pins: spdif_out_a11 {
  577. mux {
  578. groups = "spdif_out_a11";
  579. function = "spdif_out";
  580. bias-disable;
  581. };
  582. };
  583. spdif_out_a19_pins: spdif_out_a19 {
  584. mux {
  585. groups = "spdif_out_a19";
  586. function = "spdif_out";
  587. bias-disable;
  588. };
  589. };
  590. spdif_out_a20_pins: spdif_out_a20 {
  591. mux {
  592. groups = "spdif_out_a20";
  593. function = "spdif_out";
  594. bias-disable;
  595. };
  596. };
  597. spdif_out_z_pins: spdif_out_z {
  598. mux {
  599. groups = "spdif_out_z";
  600. function = "spdif_out";
  601. bias-disable;
  602. };
  603. };
  604. spi0_pins: spi0 {
  605. mux {
  606. groups = "spi0_miso",
  607. "spi0_mosi",
  608. "spi0_clk";
  609. function = "spi0";
  610. bias-disable;
  611. };
  612. };
  613. spi0_ss0_pins: spi0_ss0 {
  614. mux {
  615. groups = "spi0_ss0";
  616. function = "spi0";
  617. bias-disable;
  618. };
  619. };
  620. spi0_ss1_pins: spi0_ss1 {
  621. mux {
  622. groups = "spi0_ss1";
  623. function = "spi0";
  624. bias-disable;
  625. };
  626. };
  627. spi0_ss2_pins: spi0_ss2 {
  628. mux {
  629. groups = "spi0_ss2";
  630. function = "spi0";
  631. bias-disable;
  632. };
  633. };
  634. spi1_a_pins: spi1_a {
  635. mux {
  636. groups = "spi1_miso_a",
  637. "spi1_mosi_a",
  638. "spi1_clk_a";
  639. function = "spi1";
  640. bias-disable;
  641. };
  642. };
  643. spi1_ss0_a_pins: spi1_ss0_a {
  644. mux {
  645. groups = "spi1_ss0_a";
  646. function = "spi1";
  647. bias-disable;
  648. };
  649. };
  650. spi1_ss1_pins: spi1_ss1 {
  651. mux {
  652. groups = "spi1_ss1";
  653. function = "spi1";
  654. bias-disable;
  655. };
  656. };
  657. spi1_x_pins: spi1_x {
  658. mux {
  659. groups = "spi1_miso_x",
  660. "spi1_mosi_x",
  661. "spi1_clk_x";
  662. function = "spi1";
  663. bias-disable;
  664. };
  665. };
  666. spi1_ss0_x_pins: spi1_ss0_x {
  667. mux {
  668. groups = "spi1_ss0_x";
  669. function = "spi1";
  670. bias-disable;
  671. };
  672. };
  673. tdma_din0_pins: tdma_din0 {
  674. mux {
  675. groups = "tdma_din0";
  676. function = "tdma";
  677. bias-disable;
  678. };
  679. };
  680. tdma_dout0_x14_pins: tdma_dout0_x14 {
  681. mux {
  682. groups = "tdma_dout0_x14";
  683. function = "tdma";
  684. bias-disable;
  685. };
  686. };
  687. tdma_dout0_x15_pins: tdma_dout0_x15 {
  688. mux {
  689. groups = "tdma_dout0_x15";
  690. function = "tdma";
  691. bias-disable;
  692. };
  693. };
  694. tdma_dout1_pins: tdma_dout1 {
  695. mux {
  696. groups = "tdma_dout1";
  697. function = "tdma";
  698. bias-disable;
  699. };
  700. };
  701. tdma_din1_pins: tdma_din1 {
  702. mux {
  703. groups = "tdma_din1";
  704. function = "tdma";
  705. bias-disable;
  706. };
  707. };
  708. tdma_fs_pins: tdma_fs {
  709. mux {
  710. groups = "tdma_fs";
  711. function = "tdma";
  712. bias-disable;
  713. };
  714. };
  715. tdma_fs_slv_pins: tdma_fs_slv {
  716. mux {
  717. groups = "tdma_fs_slv";
  718. function = "tdma";
  719. bias-disable;
  720. };
  721. };
  722. tdma_sclk_pins: tdma_sclk {
  723. mux {
  724. groups = "tdma_sclk";
  725. function = "tdma";
  726. bias-disable;
  727. };
  728. };
  729. tdma_sclk_slv_pins: tdma_sclk_slv {
  730. mux {
  731. groups = "tdma_sclk_slv";
  732. function = "tdma";
  733. bias-disable;
  734. };
  735. };
  736. tdmb_din0_pins: tdmb_din0 {
  737. mux {
  738. groups = "tdmb_din0";
  739. function = "tdmb";
  740. bias-disable;
  741. };
  742. };
  743. tdmb_din1_pins: tdmb_din1 {
  744. mux {
  745. groups = "tdmb_din1";
  746. function = "tdmb";
  747. bias-disable;
  748. };
  749. };
  750. tdmb_din2_pins: tdmb_din2 {
  751. mux {
  752. groups = "tdmb_din2";
  753. function = "tdmb";
  754. bias-disable;
  755. };
  756. };
  757. tdmb_din3_pins: tdmb_din3 {
  758. mux {
  759. groups = "tdmb_din3";
  760. function = "tdmb";
  761. bias-disable;
  762. };
  763. };
  764. tdmb_dout0_pins: tdmb_dout0 {
  765. mux {
  766. groups = "tdmb_dout0";
  767. function = "tdmb";
  768. bias-disable;
  769. };
  770. };
  771. tdmb_dout1_pins: tdmb_dout1 {
  772. mux {
  773. groups = "tdmb_dout1";
  774. function = "tdmb";
  775. bias-disable;
  776. };
  777. };
  778. tdmb_dout2_pins: tdmb_dout2 {
  779. mux {
  780. groups = "tdmb_dout2";
  781. function = "tdmb";
  782. bias-disable;
  783. };
  784. };
  785. tdmb_dout3_pins: tdmb_dout3 {
  786. mux {
  787. groups = "tdmb_dout3";
  788. function = "tdmb";
  789. bias-disable;
  790. };
  791. };
  792. tdmb_fs_pins: tdmb_fs {
  793. mux {
  794. groups = "tdmb_fs";
  795. function = "tdmb";
  796. bias-disable;
  797. };
  798. };
  799. tdmb_fs_slv_pins: tdmb_fs_slv {
  800. mux {
  801. groups = "tdmb_fs_slv";
  802. function = "tdmb";
  803. bias-disable;
  804. };
  805. };
  806. tdmb_sclk_pins: tdmb_sclk {
  807. mux {
  808. groups = "tdmb_sclk";
  809. function = "tdmb";
  810. bias-disable;
  811. };
  812. };
  813. tdmb_sclk_slv_pins: tdmb_sclk_slv {
  814. mux {
  815. groups = "tdmb_sclk_slv";
  816. function = "tdmb";
  817. bias-disable;
  818. };
  819. };
  820. tdmc_fs_pins: tdmc_fs {
  821. mux {
  822. groups = "tdmc_fs";
  823. function = "tdmc";
  824. bias-disable;
  825. };
  826. };
  827. tdmc_fs_slv_pins: tdmc_fs_slv {
  828. mux {
  829. groups = "tdmc_fs_slv";
  830. function = "tdmc";
  831. bias-disable;
  832. };
  833. };
  834. tdmc_sclk_pins: tdmc_sclk {
  835. mux {
  836. groups = "tdmc_sclk";
  837. function = "tdmc";
  838. bias-disable;
  839. };
  840. };
  841. tdmc_sclk_slv_pins: tdmc_sclk_slv {
  842. mux {
  843. groups = "tdmc_sclk_slv";
  844. function = "tdmc";
  845. bias-disable;
  846. };
  847. };
  848. tdmc_din0_pins: tdmc_din0 {
  849. mux {
  850. groups = "tdmc_din0";
  851. function = "tdmc";
  852. bias-disable;
  853. };
  854. };
  855. tdmc_din1_pins: tdmc_din1 {
  856. mux {
  857. groups = "tdmc_din1";
  858. function = "tdmc";
  859. bias-disable;
  860. };
  861. };
  862. tdmc_din2_pins: tdmc_din2 {
  863. mux {
  864. groups = "tdmc_din2";
  865. function = "tdmc";
  866. bias-disable;
  867. };
  868. };
  869. tdmc_din3_pins: tdmc_din3 {
  870. mux {
  871. groups = "tdmc_din3";
  872. function = "tdmc";
  873. bias-disable;
  874. };
  875. };
  876. tdmc_dout0_pins: tdmc_dout0 {
  877. mux {
  878. groups = "tdmc_dout0";
  879. function = "tdmc";
  880. bias-disable;
  881. };
  882. };
  883. tdmc_dout1_pins: tdmc_dout1 {
  884. mux {
  885. groups = "tdmc_dout1";
  886. function = "tdmc";
  887. bias-disable;
  888. };
  889. };
  890. tdmc_dout2_pins: tdmc_dout2 {
  891. mux {
  892. groups = "tdmc_dout2";
  893. function = "tdmc";
  894. bias-disable;
  895. };
  896. };
  897. tdmc_dout3_pins: tdmc_dout3 {
  898. mux {
  899. groups = "tdmc_dout3";
  900. function = "tdmc";
  901. bias-disable;
  902. };
  903. };
  904. uart_a_pins: uart_a {
  905. mux {
  906. groups = "uart_tx_a",
  907. "uart_rx_a";
  908. function = "uart_a";
  909. bias-disable;
  910. };
  911. };
  912. uart_a_cts_rts_pins: uart_a_cts_rts {
  913. mux {
  914. groups = "uart_cts_a",
  915. "uart_rts_a";
  916. function = "uart_a";
  917. bias-disable;
  918. };
  919. };
  920. uart_b_x_pins: uart_b_x {
  921. mux {
  922. groups = "uart_tx_b_x",
  923. "uart_rx_b_x";
  924. function = "uart_b";
  925. bias-disable;
  926. };
  927. };
  928. uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
  929. mux {
  930. groups = "uart_cts_b_x",
  931. "uart_rts_b_x";
  932. function = "uart_b";
  933. bias-disable;
  934. };
  935. };
  936. uart_b_z_pins: uart_b_z {
  937. mux {
  938. groups = "uart_tx_b_z",
  939. "uart_rx_b_z";
  940. function = "uart_b";
  941. bias-disable;
  942. };
  943. };
  944. uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
  945. mux {
  946. groups = "uart_cts_b_z",
  947. "uart_rts_b_z";
  948. function = "uart_b";
  949. bias-disable;
  950. };
  951. };
  952. uart_ao_b_z_pins: uart_ao_b_z {
  953. mux {
  954. groups = "uart_ao_tx_b_z",
  955. "uart_ao_rx_b_z";
  956. function = "uart_ao_b_z";
  957. bias-disable;
  958. };
  959. };
  960. uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
  961. mux {
  962. groups = "uart_ao_cts_b_z",
  963. "uart_ao_rts_b_z";
  964. function = "uart_ao_b_z";
  965. bias-disable;
  966. };
  967. };
  968. };
  969. };
  970. hiubus: bus@ff63c000 {
  971. compatible = "simple-bus";
  972. reg = <0x0 0xff63c000 0x0 0x1c00>;
  973. #address-cells = <2>;
  974. #size-cells = <2>;
  975. ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
  976. sysctrl: system-controller@0 {
  977. compatible = "amlogic,meson-axg-hhi-sysctrl",
  978. "simple-mfd", "syscon";
  979. reg = <0 0 0 0x400>;
  980. clkc: clock-controller {
  981. compatible = "amlogic,axg-clkc";
  982. #clock-cells = <1>;
  983. clocks = <&xtal>;
  984. clock-names = "xtal";
  985. };
  986. };
  987. };
  988. mailbox: mailbox@ff63c404 {
  989. compatible = "amlogic,meson-gxbb-mhu";
  990. reg = <0 0xff63c404 0 0x4c>;
  991. interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
  992. <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
  993. <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
  994. #mbox-cells = <1>;
  995. };
  996. audio: bus@ff642000 {
  997. compatible = "simple-bus";
  998. reg = <0x0 0xff642000 0x0 0x2000>;
  999. #address-cells = <2>;
  1000. #size-cells = <2>;
  1001. ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
  1002. clkc_audio: clock-controller@0 {
  1003. compatible = "amlogic,axg-audio-clkc";
  1004. reg = <0x0 0x0 0x0 0xb4>;
  1005. #clock-cells = <1>;
  1006. clocks = <&clkc CLKID_AUDIO>,
  1007. <&clkc CLKID_MPLL0>,
  1008. <&clkc CLKID_MPLL1>,
  1009. <&clkc CLKID_MPLL2>,
  1010. <&clkc CLKID_MPLL3>,
  1011. <&clkc CLKID_HIFI_PLL>,
  1012. <&clkc CLKID_FCLK_DIV3>,
  1013. <&clkc CLKID_FCLK_DIV4>,
  1014. <&clkc CLKID_GP0_PLL>;
  1015. clock-names = "pclk",
  1016. "mst_in0",
  1017. "mst_in1",
  1018. "mst_in2",
  1019. "mst_in3",
  1020. "mst_in4",
  1021. "mst_in5",
  1022. "mst_in6",
  1023. "mst_in7";
  1024. resets = <&reset RESET_AUDIO>;
  1025. };
  1026. toddr_a: audio-controller@100 {
  1027. compatible = "amlogic,axg-toddr";
  1028. reg = <0x0 0x100 0x0 0x2c>;
  1029. #sound-dai-cells = <0>;
  1030. sound-name-prefix = "TODDR_A";
  1031. interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
  1032. clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
  1033. resets = <&arb AXG_ARB_TODDR_A>;
  1034. amlogic,fifo-depth = <512>;
  1035. status = "disabled";
  1036. };
  1037. toddr_b: audio-controller@140 {
  1038. compatible = "amlogic,axg-toddr";
  1039. reg = <0x0 0x140 0x0 0x2c>;
  1040. #sound-dai-cells = <0>;
  1041. sound-name-prefix = "TODDR_B";
  1042. interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
  1043. clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
  1044. resets = <&arb AXG_ARB_TODDR_B>;
  1045. amlogic,fifo-depth = <256>;
  1046. status = "disabled";
  1047. };
  1048. toddr_c: audio-controller@180 {
  1049. compatible = "amlogic,axg-toddr";
  1050. reg = <0x0 0x180 0x0 0x2c>;
  1051. #sound-dai-cells = <0>;
  1052. sound-name-prefix = "TODDR_C";
  1053. interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
  1054. clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
  1055. resets = <&arb AXG_ARB_TODDR_C>;
  1056. amlogic,fifo-depth = <256>;
  1057. status = "disabled";
  1058. };
  1059. frddr_a: audio-controller@1c0 {
  1060. compatible = "amlogic,axg-frddr";
  1061. reg = <0x0 0x1c0 0x0 0x2c>;
  1062. #sound-dai-cells = <0>;
  1063. sound-name-prefix = "FRDDR_A";
  1064. interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
  1065. clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
  1066. resets = <&arb AXG_ARB_FRDDR_A>;
  1067. amlogic,fifo-depth = <512>;
  1068. status = "disabled";
  1069. };
  1070. frddr_b: audio-controller@200 {
  1071. compatible = "amlogic,axg-frddr";
  1072. reg = <0x0 0x200 0x0 0x2c>;
  1073. #sound-dai-cells = <0>;
  1074. sound-name-prefix = "FRDDR_B";
  1075. interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
  1076. clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
  1077. resets = <&arb AXG_ARB_FRDDR_B>;
  1078. amlogic,fifo-depth = <256>;
  1079. status = "disabled";
  1080. };
  1081. frddr_c: audio-controller@240 {
  1082. compatible = "amlogic,axg-frddr";
  1083. reg = <0x0 0x240 0x0 0x2c>;
  1084. #sound-dai-cells = <0>;
  1085. sound-name-prefix = "FRDDR_C";
  1086. interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
  1087. clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
  1088. resets = <&arb AXG_ARB_FRDDR_C>;
  1089. amlogic,fifo-depth = <256>;
  1090. status = "disabled";
  1091. };
  1092. arb: reset-controller@280 {
  1093. compatible = "amlogic,meson-axg-audio-arb";
  1094. reg = <0x0 0x280 0x0 0x4>;
  1095. #reset-cells = <1>;
  1096. clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
  1097. };
  1098. tdmin_a: audio-controller@300 {
  1099. compatible = "amlogic,axg-tdmin";
  1100. reg = <0x0 0x300 0x0 0x40>;
  1101. sound-name-prefix = "TDMIN_A";
  1102. clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
  1103. <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
  1104. <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
  1105. <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
  1106. <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
  1107. clock-names = "pclk", "sclk", "sclk_sel",
  1108. "lrclk", "lrclk_sel";
  1109. status = "disabled";
  1110. };
  1111. tdmin_b: audio-controller@340 {
  1112. compatible = "amlogic,axg-tdmin";
  1113. reg = <0x0 0x340 0x0 0x40>;
  1114. sound-name-prefix = "TDMIN_B";
  1115. clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
  1116. <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
  1117. <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
  1118. <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
  1119. <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
  1120. clock-names = "pclk", "sclk", "sclk_sel",
  1121. "lrclk", "lrclk_sel";
  1122. status = "disabled";
  1123. };
  1124. tdmin_c: audio-controller@380 {
  1125. compatible = "amlogic,axg-tdmin";
  1126. reg = <0x0 0x380 0x0 0x40>;
  1127. sound-name-prefix = "TDMIN_C";
  1128. clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
  1129. <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
  1130. <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
  1131. <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
  1132. <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
  1133. clock-names = "pclk", "sclk", "sclk_sel",
  1134. "lrclk", "lrclk_sel";
  1135. status = "disabled";
  1136. };
  1137. tdmin_lb: audio-controller@3c0 {
  1138. compatible = "amlogic,axg-tdmin";
  1139. reg = <0x0 0x3c0 0x0 0x40>;
  1140. sound-name-prefix = "TDMIN_LB";
  1141. clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
  1142. <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
  1143. <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
  1144. <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
  1145. <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
  1146. clock-names = "pclk", "sclk", "sclk_sel",
  1147. "lrclk", "lrclk_sel";
  1148. status = "disabled";
  1149. };
  1150. spdifin: audio-controller@400 {
  1151. compatible = "amlogic,axg-spdifin";
  1152. reg = <0x0 0x400 0x0 0x30>;
  1153. #sound-dai-cells = <0>;
  1154. sound-name-prefix = "SPDIFIN";
  1155. interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
  1156. clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
  1157. <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
  1158. clock-names = "pclk", "refclk";
  1159. status = "disabled";
  1160. };
  1161. spdifout: audio-controller@480 {
  1162. compatible = "amlogic,axg-spdifout";
  1163. reg = <0x0 0x480 0x0 0x50>;
  1164. #sound-dai-cells = <0>;
  1165. sound-name-prefix = "SPDIFOUT";
  1166. clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
  1167. <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
  1168. clock-names = "pclk", "mclk";
  1169. status = "disabled";
  1170. };
  1171. tdmout_a: audio-controller@500 {
  1172. compatible = "amlogic,axg-tdmout";
  1173. reg = <0x0 0x500 0x0 0x40>;
  1174. sound-name-prefix = "TDMOUT_A";
  1175. clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
  1176. <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
  1177. <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
  1178. <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
  1179. <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
  1180. clock-names = "pclk", "sclk", "sclk_sel",
  1181. "lrclk", "lrclk_sel";
  1182. status = "disabled";
  1183. };
  1184. tdmout_b: audio-controller@540 {
  1185. compatible = "amlogic,axg-tdmout";
  1186. reg = <0x0 0x540 0x0 0x40>;
  1187. sound-name-prefix = "TDMOUT_B";
  1188. clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
  1189. <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
  1190. <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
  1191. <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
  1192. <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
  1193. clock-names = "pclk", "sclk", "sclk_sel",
  1194. "lrclk", "lrclk_sel";
  1195. status = "disabled";
  1196. };
  1197. tdmout_c: audio-controller@580 {
  1198. compatible = "amlogic,axg-tdmout";
  1199. reg = <0x0 0x580 0x0 0x40>;
  1200. sound-name-prefix = "TDMOUT_C";
  1201. clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
  1202. <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
  1203. <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
  1204. <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
  1205. <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
  1206. clock-names = "pclk", "sclk", "sclk_sel",
  1207. "lrclk", "lrclk_sel";
  1208. status = "disabled";
  1209. };
  1210. };
  1211. aobus: bus@ff800000 {
  1212. compatible = "simple-bus";
  1213. reg = <0x0 0xff800000 0x0 0x100000>;
  1214. #address-cells = <2>;
  1215. #size-cells = <2>;
  1216. ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
  1217. sysctrl_AO: sys-ctrl@0 {
  1218. compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
  1219. reg = <0x0 0x0 0x0 0x100>;
  1220. clkc_AO: clock-controller {
  1221. compatible = "amlogic,meson-axg-aoclkc";
  1222. #clock-cells = <1>;
  1223. #reset-cells = <1>;
  1224. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  1225. clock-names = "xtal", "mpeg-clk";
  1226. };
  1227. };
  1228. pinctrl_aobus: pinctrl@14 {
  1229. compatible = "amlogic,meson-axg-aobus-pinctrl";
  1230. #address-cells = <2>;
  1231. #size-cells = <2>;
  1232. ranges;
  1233. gpio_ao: bank@14 {
  1234. reg = <0x0 0x00014 0x0 0x8>,
  1235. <0x0 0x0002c 0x0 0x4>,
  1236. <0x0 0x00024 0x0 0x8>;
  1237. reg-names = "mux", "pull", "gpio";
  1238. gpio-controller;
  1239. #gpio-cells = <2>;
  1240. gpio-ranges = <&pinctrl_aobus 0 0 15>;
  1241. };
  1242. i2c_ao_sck_4_pins: i2c_ao_sck_4 {
  1243. mux {
  1244. groups = "i2c_ao_sck_4";
  1245. function = "i2c_ao";
  1246. bias-disable;
  1247. };
  1248. };
  1249. i2c_ao_sck_8_pins: i2c_ao_sck_8 {
  1250. mux {
  1251. groups = "i2c_ao_sck_8";
  1252. function = "i2c_ao";
  1253. bias-disable;
  1254. };
  1255. };
  1256. i2c_ao_sck_10_pins: i2c_ao_sck_10 {
  1257. mux {
  1258. groups = "i2c_ao_sck_10";
  1259. function = "i2c_ao";
  1260. bias-disable;
  1261. };
  1262. };
  1263. i2c_ao_sda_5_pins: i2c_ao_sda_5 {
  1264. mux {
  1265. groups = "i2c_ao_sda_5";
  1266. function = "i2c_ao";
  1267. bias-disable;
  1268. };
  1269. };
  1270. i2c_ao_sda_9_pins: i2c_ao_sda_9 {
  1271. mux {
  1272. groups = "i2c_ao_sda_9";
  1273. function = "i2c_ao";
  1274. bias-disable;
  1275. };
  1276. };
  1277. i2c_ao_sda_11_pins: i2c_ao_sda_11 {
  1278. mux {
  1279. groups = "i2c_ao_sda_11";
  1280. function = "i2c_ao";
  1281. bias-disable;
  1282. };
  1283. };
  1284. remote_input_ao_pins: remote_input_ao {
  1285. mux {
  1286. groups = "remote_input_ao";
  1287. function = "remote_input_ao";
  1288. bias-disable;
  1289. };
  1290. };
  1291. uart_ao_a_pins: uart_ao_a {
  1292. mux {
  1293. groups = "uart_ao_tx_a",
  1294. "uart_ao_rx_a";
  1295. function = "uart_ao_a";
  1296. bias-disable;
  1297. };
  1298. };
  1299. uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  1300. mux {
  1301. groups = "uart_ao_cts_a",
  1302. "uart_ao_rts_a";
  1303. function = "uart_ao_a";
  1304. bias-disable;
  1305. };
  1306. };
  1307. uart_ao_b_pins: uart_ao_b {
  1308. mux {
  1309. groups = "uart_ao_tx_b",
  1310. "uart_ao_rx_b";
  1311. function = "uart_ao_b";
  1312. bias-disable;
  1313. };
  1314. };
  1315. uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
  1316. mux {
  1317. groups = "uart_ao_cts_b",
  1318. "uart_ao_rts_b";
  1319. function = "uart_ao_b";
  1320. bias-disable;
  1321. };
  1322. };
  1323. };
  1324. sec_AO: ao-secure@140 {
  1325. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  1326. reg = <0x0 0x140 0x0 0x140>;
  1327. amlogic,has-chip-id;
  1328. };
  1329. pwm_AO_cd: pwm@2000 {
  1330. compatible = "amlogic,meson-axg-ao-pwm";
  1331. reg = <0x0 0x02000 0x0 0x20>;
  1332. #pwm-cells = <3>;
  1333. status = "disabled";
  1334. };
  1335. uart_AO: serial@3000 {
  1336. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  1337. reg = <0x0 0x3000 0x0 0x18>;
  1338. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  1339. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
  1340. clock-names = "xtal", "pclk", "baud";
  1341. status = "disabled";
  1342. };
  1343. uart_AO_B: serial@4000 {
  1344. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  1345. reg = <0x0 0x4000 0x0 0x18>;
  1346. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  1347. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  1348. clock-names = "xtal", "pclk", "baud";
  1349. status = "disabled";
  1350. };
  1351. i2c_AO: i2c@5000 {
  1352. compatible = "amlogic,meson-axg-i2c";
  1353. reg = <0x0 0x05000 0x0 0x20>;
  1354. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  1355. clocks = <&clkc CLKID_AO_I2C>;
  1356. #address-cells = <1>;
  1357. #size-cells = <0>;
  1358. status = "disabled";
  1359. };
  1360. pwm_AO_ab: pwm@7000 {
  1361. compatible = "amlogic,meson-axg-ao-pwm";
  1362. reg = <0x0 0x07000 0x0 0x20>;
  1363. #pwm-cells = <3>;
  1364. status = "disabled";
  1365. };
  1366. ir: ir@8000 {
  1367. compatible = "amlogic,meson-gxbb-ir";
  1368. reg = <0x0 0x8000 0x0 0x20>;
  1369. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  1370. status = "disabled";
  1371. };
  1372. saradc: adc@9000 {
  1373. compatible = "amlogic,meson-axg-saradc",
  1374. "amlogic,meson-saradc";
  1375. reg = <0x0 0x9000 0x0 0x38>;
  1376. #io-channel-cells = <1>;
  1377. interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
  1378. clocks = <&xtal>,
  1379. <&clkc_AO CLKID_AO_SAR_ADC>,
  1380. <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
  1381. <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
  1382. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  1383. status = "disabled";
  1384. };
  1385. };
  1386. gic: interrupt-controller@ffc01000 {
  1387. compatible = "arm,gic-400";
  1388. reg = <0x0 0xffc01000 0 0x1000>,
  1389. <0x0 0xffc02000 0 0x2000>,
  1390. <0x0 0xffc04000 0 0x2000>,
  1391. <0x0 0xffc06000 0 0x2000>;
  1392. interrupt-controller;
  1393. interrupts = <GIC_PPI 9
  1394. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  1395. #interrupt-cells = <3>;
  1396. #address-cells = <0>;
  1397. };
  1398. cbus: bus@ffd00000 {
  1399. compatible = "simple-bus";
  1400. reg = <0x0 0xffd00000 0x0 0x25000>;
  1401. #address-cells = <2>;
  1402. #size-cells = <2>;
  1403. ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
  1404. reset: reset-controller@1004 {
  1405. compatible = "amlogic,meson-axg-reset";
  1406. reg = <0x0 0x01004 0x0 0x9c>;
  1407. #reset-cells = <1>;
  1408. };
  1409. gpio_intc: interrupt-controller@f080 {
  1410. compatible = "amlogic,meson-axg-gpio-intc",
  1411. "amlogic,meson-gpio-intc";
  1412. reg = <0x0 0xf080 0x0 0x10>;
  1413. interrupt-controller;
  1414. #interrupt-cells = <2>;
  1415. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  1416. };
  1417. watchdog@f0d0 {
  1418. compatible = "amlogic,meson-gxbb-wdt";
  1419. reg = <0x0 0xf0d0 0x0 0x10>;
  1420. clocks = <&xtal>;
  1421. };
  1422. pwm_ab: pwm@1b000 {
  1423. compatible = "amlogic,meson-axg-ee-pwm";
  1424. reg = <0x0 0x1b000 0x0 0x20>;
  1425. #pwm-cells = <3>;
  1426. status = "disabled";
  1427. };
  1428. pwm_cd: pwm@1a000 {
  1429. compatible = "amlogic,meson-axg-ee-pwm";
  1430. reg = <0x0 0x1a000 0x0 0x20>;
  1431. #pwm-cells = <3>;
  1432. status = "disabled";
  1433. };
  1434. spicc0: spi@13000 {
  1435. compatible = "amlogic,meson-axg-spicc";
  1436. reg = <0x0 0x13000 0x0 0x3c>;
  1437. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  1438. clocks = <&clkc CLKID_SPICC0>;
  1439. clock-names = "core";
  1440. #address-cells = <1>;
  1441. #size-cells = <0>;
  1442. status = "disabled";
  1443. };
  1444. spicc1: spi@15000 {
  1445. compatible = "amlogic,meson-axg-spicc";
  1446. reg = <0x0 0x15000 0x0 0x3c>;
  1447. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  1448. clocks = <&clkc CLKID_SPICC1>;
  1449. clock-names = "core";
  1450. #address-cells = <1>;
  1451. #size-cells = <0>;
  1452. status = "disabled";
  1453. };
  1454. clk_msr: clock-measure@18000 {
  1455. compatible = "amlogic,meson-axg-clk-measure";
  1456. reg = <0x0 0x18000 0x0 0x10>;
  1457. };
  1458. i2c3: i2c@1c000 {
  1459. compatible = "amlogic,meson-axg-i2c";
  1460. reg = <0x0 0x1c000 0x0 0x20>;
  1461. interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
  1462. clocks = <&clkc CLKID_I2C>;
  1463. #address-cells = <1>;
  1464. #size-cells = <0>;
  1465. status = "disabled";
  1466. };
  1467. i2c2: i2c@1d000 {
  1468. compatible = "amlogic,meson-axg-i2c";
  1469. reg = <0x0 0x1d000 0x0 0x20>;
  1470. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  1471. clocks = <&clkc CLKID_I2C>;
  1472. #address-cells = <1>;
  1473. #size-cells = <0>;
  1474. status = "disabled";
  1475. };
  1476. i2c1: i2c@1e000 {
  1477. compatible = "amlogic,meson-axg-i2c";
  1478. reg = <0x0 0x1e000 0x0 0x20>;
  1479. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  1480. clocks = <&clkc CLKID_I2C>;
  1481. #address-cells = <1>;
  1482. #size-cells = <0>;
  1483. status = "disabled";
  1484. };
  1485. i2c0: i2c@1f000 {
  1486. compatible = "amlogic,meson-axg-i2c";
  1487. reg = <0x0 0x1f000 0x0 0x20>;
  1488. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  1489. clocks = <&clkc CLKID_I2C>;
  1490. #address-cells = <1>;
  1491. #size-cells = <0>;
  1492. status = "disabled";
  1493. };
  1494. uart_B: serial@23000 {
  1495. compatible = "amlogic,meson-gx-uart";
  1496. reg = <0x0 0x23000 0x0 0x18>;
  1497. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  1498. status = "disabled";
  1499. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  1500. clock-names = "xtal", "pclk", "baud";
  1501. };
  1502. uart_A: serial@24000 {
  1503. compatible = "amlogic,meson-gx-uart";
  1504. reg = <0x0 0x24000 0x0 0x18>;
  1505. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  1506. status = "disabled";
  1507. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  1508. clock-names = "xtal", "pclk", "baud";
  1509. };
  1510. };
  1511. apb: bus@ffe00000 {
  1512. compatible = "simple-bus";
  1513. reg = <0x0 0xffe00000 0x0 0x200000>;
  1514. #address-cells = <2>;
  1515. #size-cells = <2>;
  1516. ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
  1517. sd_emmc_b: sd@5000 {
  1518. compatible = "amlogic,meson-axg-mmc";
  1519. reg = <0x0 0x5000 0x0 0x800>;
  1520. interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
  1521. status = "disabled";
  1522. clocks = <&clkc CLKID_SD_EMMC_B>,
  1523. <&clkc CLKID_SD_EMMC_B_CLK0>,
  1524. <&clkc CLKID_FCLK_DIV2>;
  1525. clock-names = "core", "clkin0", "clkin1";
  1526. resets = <&reset RESET_SD_EMMC_B>;
  1527. };
  1528. sd_emmc_c: mmc@7000 {
  1529. compatible = "amlogic,meson-axg-mmc";
  1530. reg = <0x0 0x7000 0x0 0x800>;
  1531. interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
  1532. status = "disabled";
  1533. clocks = <&clkc CLKID_SD_EMMC_C>,
  1534. <&clkc CLKID_SD_EMMC_C_CLK0>,
  1535. <&clkc CLKID_FCLK_DIV2>;
  1536. clock-names = "core", "clkin0", "clkin1";
  1537. resets = <&reset RESET_SD_EMMC_C>;
  1538. };
  1539. };
  1540. sram: sram@fffc0000 {
  1541. compatible = "mmio-sram";
  1542. reg = <0x0 0xfffc0000 0x0 0x20000>;
  1543. #address-cells = <1>;
  1544. #size-cells = <1>;
  1545. ranges = <0 0x0 0xfffc0000 0x20000>;
  1546. cpu_scp_lpri: scp-sram@13000 {
  1547. compatible = "amlogic,meson-axg-scp-shmem";
  1548. reg = <0x13000 0x400>;
  1549. };
  1550. cpu_scp_hpri: scp-sram@13400 {
  1551. compatible = "amlogic,meson-axg-scp-shmem";
  1552. reg = <0x13400 0x400>;
  1553. };
  1554. };
  1555. };
  1556. timer {
  1557. compatible = "arm,armv8-timer";
  1558. interrupts = <GIC_PPI 13
  1559. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  1560. <GIC_PPI 14
  1561. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  1562. <GIC_PPI 11
  1563. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  1564. <GIC_PPI 10
  1565. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  1566. };
  1567. xtal: xtal-clk {
  1568. compatible = "fixed-clock";
  1569. clock-frequency = <24000000>;
  1570. clock-output-names = "xtal";
  1571. #clock-cells = <0>;
  1572. };
  1573. };