ppc_asm.tmpl 7.9 KB

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  1. /*
  2. * (C) Copyright 2000-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * This file contains all the macros and symbols which define
  9. * a PowerPC assembly language environment.
  10. */
  11. #ifndef __PPC_ASM_TMPL__
  12. #define __PPC_ASM_TMPL__
  13. #include <config.h>
  14. /***************************************************************************
  15. *
  16. * These definitions simplify the ugly declarations necessary for GOT
  17. * definitions.
  18. *
  19. * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
  20. *
  21. * Uses r12 to access the GOT
  22. */
  23. #define START_GOT \
  24. .section ".got2","aw"; \
  25. .LCTOC1 = .+32768
  26. #define END_GOT \
  27. .text
  28. #define GET_GOT \
  29. bl 1f ; \
  30. .text 2 ; \
  31. 0: .long .LCTOC1-1f ; \
  32. .text ; \
  33. 1: mflr r12 ; \
  34. lwz r0,0b-1b(r12) ; \
  35. add r12,r0,r12 ;
  36. #define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
  37. #define GOT(NAME) .L_ ## NAME (r12)
  38. /***************************************************************************
  39. * Register names
  40. */
  41. #define r0 0
  42. #define r1 1
  43. #define r2 2
  44. #define r3 3
  45. #define r4 4
  46. #define r5 5
  47. #define r6 6
  48. #define r7 7
  49. #define r8 8
  50. #define r9 9
  51. #define r10 10
  52. #define r11 11
  53. #define r12 12
  54. #define r13 13
  55. #define r14 14
  56. #define r15 15
  57. #define r16 16
  58. #define r17 17
  59. #define r18 18
  60. #define r19 19
  61. #define r20 20
  62. #define r21 21
  63. #define r22 22
  64. #define r23 23
  65. #define r24 24
  66. #define r25 25
  67. #define r26 26
  68. #define r27 27
  69. #define r28 28
  70. #define r29 29
  71. #define r30 30
  72. #define r31 31
  73. #if defined(CONFIG_8xx)
  74. /* Some special registers */
  75. #define ICR 148 /* Interrupt Cause Register (37-44) */
  76. #define DER 149
  77. #define COUNTA 150 /* Breakpoint Counter (37-44) */
  78. #define COUNTB 151 /* Breakpoint Counter (37-44) */
  79. #define LCTRL1 156 /* Load/Store Support (37-40) */
  80. #define LCTRL2 157 /* Load/Store Support (37-41) */
  81. #define ICTRL 158
  82. #endif /* CONFIG_8xx */
  83. #if defined(CONFIG_5xx)
  84. /* Some special purpose registers */
  85. #define DER 149 /* Debug Enable Register */
  86. #define COUNTA 150 /* Breakpoint Counter */
  87. #define COUNTB 151 /* Breakpoint Counter */
  88. #define LCTRL1 156 /* Load/Store Support */
  89. #define LCTRL2 157 /* Load/Store Support */
  90. #define ICTRL 158 /* I-Bus Support Control Register */
  91. #define EID 81
  92. #endif /* CONFIG_5xx */
  93. #if defined(CONFIG_8xx)
  94. /* Registers in the processor's internal memory map that we use.
  95. */
  96. #define SYPCR 0x00000004
  97. #define BR0 0x00000100
  98. #define OR0 0x00000104
  99. #define BR1 0x00000108
  100. #define OR1 0x0000010c
  101. #define BR2 0x00000110
  102. #define OR2 0x00000114
  103. #define BR3 0x00000118
  104. #define OR3 0x0000011c
  105. #define BR4 0x00000120
  106. #define OR4 0x00000124
  107. #define MAR 0x00000164
  108. #define MCR 0x00000168
  109. #define MAMR 0x00000170
  110. #define MBMR 0x00000174
  111. #define MSTAT 0x00000178
  112. #define MPTPR 0x0000017a
  113. #define MDR 0x0000017c
  114. #define TBSCR 0x00000200
  115. #define TBREFF0 0x00000204
  116. #define PLPRCR 0x00000284
  117. #elif defined(CONFIG_MPC8260)
  118. #define HID2 1011
  119. #define HID0_IFEM (1<<7)
  120. #define HID0_ICE_BITPOS 16
  121. #define HID0_DCE_BITPOS 17
  122. #define IM_REGBASE 0x10000
  123. #define IM_SYPCR (IM_REGBASE+0x0004)
  124. #define IM_SWSR (IM_REGBASE+0x000e)
  125. #define IM_BR0 (IM_REGBASE+0x0100)
  126. #define IM_OR0 (IM_REGBASE+0x0104)
  127. #define IM_BR1 (IM_REGBASE+0x0108)
  128. #define IM_OR1 (IM_REGBASE+0x010c)
  129. #define IM_BR2 (IM_REGBASE+0x0110)
  130. #define IM_OR2 (IM_REGBASE+0x0114)
  131. #define IM_MPTPR (IM_REGBASE+0x0184)
  132. #define IM_PSDMR (IM_REGBASE+0x0190)
  133. #define IM_PSRT (IM_REGBASE+0x019c)
  134. #define IM_IMMR (IM_REGBASE+0x01a8)
  135. #define IM_SCCR (IM_REGBASE+0x0c80)
  136. #elif defined(CONFIG_MPC5xxx)
  137. #define HID0_ICE_BITPOS 16
  138. #define HID0_DCE_BITPOS 17
  139. #endif
  140. #define curptr r2
  141. #define SYNC \
  142. sync; \
  143. isync
  144. /*
  145. * Macros for storing registers into and loading registers from
  146. * exception frames.
  147. */
  148. #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
  149. #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  150. #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  151. #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  152. #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  153. #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
  154. #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
  155. #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  156. #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  157. #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  158. /*
  159. * GCC sometimes accesses words at negative offsets from the stack
  160. * pointer, although the SysV ABI says it shouldn't. To cope with
  161. * this, we leave this much untouched space on the stack on exception
  162. * entry.
  163. */
  164. #define STACK_UNDERHEAD 64
  165. /*
  166. * Exception entry code. This code runs with address translation
  167. * turned off, i.e. using physical addresses.
  168. * We assume sprg3 has the physical address of the current
  169. * task's thread_struct.
  170. */
  171. #define EXCEPTION_PROLOG(reg1, reg2) \
  172. mtspr SPRG0,r20; \
  173. mtspr SPRG1,r21; \
  174. mfcr r20; \
  175. subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
  176. stw r20,_CCR(r21); /* save registers */ \
  177. stw r22,GPR22(r21); \
  178. stw r23,GPR23(r21); \
  179. mfspr r20,SPRG0; \
  180. stw r20,GPR20(r21); \
  181. mfspr r22,SPRG1; \
  182. stw r22,GPR21(r21); \
  183. mflr r20; \
  184. stw r20,_LINK(r21); \
  185. mfctr r22; \
  186. stw r22,_CTR(r21); \
  187. mfspr r20,XER; \
  188. stw r20,_XER(r21); \
  189. mfspr r20, DAR_DEAR; \
  190. stw r20,_DAR(r21); \
  191. mfspr r22,reg1; \
  192. mfspr r23,reg2; \
  193. stw r0,GPR0(r21); \
  194. stw r1,GPR1(r21); \
  195. stw r2,GPR2(r21); \
  196. stw r1,0(r21); \
  197. mr r1,r21; /* set new kernel sp */ \
  198. SAVE_4GPRS(3, r21);
  199. /*
  200. * Note: code which follows this uses cr0.eq (set if from kernel),
  201. * r21, r22 (SRR0), and r23 (SRR1).
  202. */
  203. /*
  204. * Exception vectors.
  205. *
  206. * The data words for `hdlr' and `int_return' are initialized with
  207. * OFFSET values only; they must be relocated first before they can
  208. * be used!
  209. */
  210. #define COPY_EE(d, s) rlwimi d,s,0,16,16
  211. #define NOCOPY(d, s)
  212. #ifdef CONFIG_E500
  213. #define EXC_XFER_TEMPLATE(n, label, hdlr, msr, copyee) \
  214. stw r22,_NIP(r21); \
  215. stw r23,_MSR(r21); \
  216. li r23,n; \
  217. stw r23,TRAP(r21); \
  218. li r20,msr; \
  219. copyee(r20,r23); \
  220. rlwimi r20,r23,0,25,25; \
  221. mtmsr r20; \
  222. bl 1f; \
  223. 1: mflr r23; \
  224. addis r23,r23,(hdlr - 1b)@ha; \
  225. addi r23,r23,(hdlr - 1b)@l; \
  226. b transfer_to_handler
  227. #define STD_EXCEPTION(n, label, hdlr) \
  228. label: \
  229. EXCEPTION_PROLOG(SRR0, SRR1); \
  230. addi r3,r1,STACK_FRAME_OVERHEAD; \
  231. EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY) \
  232. #define CRIT_EXCEPTION(n, label, hdlr) \
  233. label: \
  234. EXCEPTION_PROLOG(CSRR0, CSRR1); \
  235. addi r3,r1,STACK_FRAME_OVERHEAD; \
  236. EXC_XFER_TEMPLATE(n, label, hdlr, \
  237. MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
  238. #define MCK_EXCEPTION(n, label, hdlr) \
  239. label: \
  240. EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
  241. addi r3,r1,STACK_FRAME_OVERHEAD; \
  242. EXC_XFER_TEMPLATE(n, label, hdlr, \
  243. MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
  244. #else /* !E500 */
  245. #define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \
  246. bl 1f; \
  247. 1: mflr r20; \
  248. lwz r20,(.L_ ## label)-1b+8(r20); \
  249. mtlr r20; \
  250. li r20,msr; \
  251. copyee(r20,r23); \
  252. rlwimi r20,r23,0,25,25; \
  253. blrl; \
  254. .L_ ## label : \
  255. .long hdlr - _start + _START_OFFSET; \
  256. .long int_return - _start + _START_OFFSET; \
  257. .long transfer_to_handler - _start + _START_OFFSET
  258. #define STD_EXCEPTION(n, label, hdlr) \
  259. . = n; \
  260. label: \
  261. EXCEPTION_PROLOG(SRR0, SRR1); \
  262. addi r3,r1,STACK_FRAME_OVERHEAD; \
  263. EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY) \
  264. #define CRIT_EXCEPTION(n, label, hdlr) \
  265. . = n; \
  266. label: \
  267. EXCEPTION_PROLOG(CSRR0, CSRR1); \
  268. addi r3,r1,STACK_FRAME_OVERHEAD; \
  269. EXC_XFER_TEMPLATE(label, hdlr, \
  270. MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
  271. #define MCK_EXCEPTION(n, label, hdlr) \
  272. . = n; \
  273. label: \
  274. EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
  275. addi r3,r1,STACK_FRAME_OVERHEAD; \
  276. EXC_XFER_TEMPLATE(label, hdlr, \
  277. MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
  278. #endif /* !E500 */
  279. #endif /* __PPC_ASM_TMPL__ */