start.S 43 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914
  1. /*
  2. * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  3. * Copyright (C) 2003 Motorola,Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
  8. *
  9. * The processor starts at 0xfffffffc and the code is first executed in the
  10. * last 4K page(0xfffff000-0xffffffff) in flash/rom.
  11. *
  12. */
  13. #include <asm-offsets.h>
  14. #include <config.h>
  15. #include <mpc85xx.h>
  16. #include <version.h>
  17. #include <ppc_asm.tmpl>
  18. #include <ppc_defs.h>
  19. #include <asm/cache.h>
  20. #include <asm/mmu.h>
  21. #undef MSR_KERNEL
  22. #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  23. #define LAW_EN 0x80000000
  24. #if defined(CONFIG_NAND_SPL) || \
  25. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
  26. #define MINIMAL_SPL
  27. #endif
  28. #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
  29. !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  30. #define NOR_BOOT
  31. #endif
  32. /*
  33. * Set up GOT: Global Offset Table
  34. *
  35. * Use r12 to access the GOT
  36. */
  37. START_GOT
  38. GOT_ENTRY(_GOT2_TABLE_)
  39. GOT_ENTRY(_FIXUP_TABLE_)
  40. #ifndef MINIMAL_SPL
  41. GOT_ENTRY(_start)
  42. GOT_ENTRY(_start_of_vectors)
  43. GOT_ENTRY(_end_of_vectors)
  44. GOT_ENTRY(transfer_to_handler)
  45. #endif
  46. GOT_ENTRY(__init_end)
  47. GOT_ENTRY(__bss_end)
  48. GOT_ENTRY(__bss_start)
  49. END_GOT
  50. /*
  51. * e500 Startup -- after reset only the last 4KB of the effective
  52. * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
  53. * section is located at THIS LAST page and basically does three
  54. * things: clear some registers, set up exception tables and
  55. * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
  56. * continue the boot procedure.
  57. * Once the boot rom is mapped by TLB entries we can proceed
  58. * with normal startup.
  59. *
  60. */
  61. .section .bootpg,"ax"
  62. .globl _start_e500
  63. _start_e500:
  64. /* Enable debug exception */
  65. li r1,MSR_DE
  66. mtmsr r1
  67. /*
  68. * If we got an ePAPR device tree pointer passed in as r3, we need that
  69. * later in cpu_init_early_f(). Save it to a safe register before we
  70. * clobber it so that we can fetch it from there later.
  71. */
  72. mr r24, r3
  73. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  74. mfspr r3,SPRN_SVR
  75. rlwinm r3,r3,0,0xff
  76. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
  77. cmpw r3,r4
  78. beq 1f
  79. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  80. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  81. cmpw r3,r4
  82. beq 1f
  83. #endif
  84. /* Not a supported revision affected by erratum */
  85. li r27,0
  86. b 2f
  87. 1: li r27,1 /* Remember for later that we have the erratum */
  88. /* Erratum says set bits 55:60 to 001001 */
  89. msync
  90. isync
  91. mfspr r3,SPRN_HDBCR0
  92. li r4,0x48
  93. rlwimi r3,r4,0,0x1f8
  94. mtspr SPRN_HDBCR0,r3
  95. isync
  96. 2:
  97. #endif
  98. #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
  99. msync
  100. isync
  101. mfspr r3, SPRN_HDBCR0
  102. oris r3, r3, 0x0080
  103. mtspr SPRN_HDBCR0, r3
  104. #endif
  105. #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
  106. !defined(CONFIG_E6500)
  107. /* ISBC uses L2 as stack.
  108. * Disable L2 cache here so that u-boot can enable it later
  109. * as part of it's normal flow
  110. */
  111. /* Check if L2 is enabled */
  112. mfspr r3, SPRN_L2CSR0
  113. lis r2, L2CSR0_L2E@h
  114. ori r2, r2, L2CSR0_L2E@l
  115. and. r4, r3, r2
  116. beq l2_disabled
  117. mfspr r3, SPRN_L2CSR0
  118. /* Flush L2 cache */
  119. lis r2,(L2CSR0_L2FL)@h
  120. ori r2, r2, (L2CSR0_L2FL)@l
  121. or r3, r2, r3
  122. sync
  123. isync
  124. mtspr SPRN_L2CSR0,r3
  125. isync
  126. 1:
  127. mfspr r3, SPRN_L2CSR0
  128. and. r1, r3, r2
  129. bne 1b
  130. mfspr r3, SPRN_L2CSR0
  131. lis r2, L2CSR0_L2E@h
  132. ori r2, r2, L2CSR0_L2E@l
  133. andc r4, r3, r2
  134. sync
  135. isync
  136. mtspr SPRN_L2CSR0,r4
  137. isync
  138. l2_disabled:
  139. #endif
  140. /* clear registers/arrays not reset by hardware */
  141. /* L1 */
  142. li r0,2
  143. mtspr L1CSR0,r0 /* invalidate d-cache */
  144. mtspr L1CSR1,r0 /* invalidate i-cache */
  145. mfspr r1,DBSR
  146. mtspr DBSR,r1 /* Clear all valid bits */
  147. .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
  148. lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
  149. ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
  150. mtspr MAS0, \scratch
  151. lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
  152. ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
  153. mtspr MAS1, \scratch
  154. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  155. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  156. mtspr MAS2, \scratch
  157. lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
  158. ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
  159. mtspr MAS3, \scratch
  160. lis \scratch, \phy_high@h
  161. ori \scratch, \scratch, \phy_high@l
  162. mtspr MAS7, \scratch
  163. isync
  164. msync
  165. tlbwe
  166. isync
  167. .endm
  168. .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
  169. lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
  170. ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
  171. mtspr MAS0, \scratch
  172. lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
  173. ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
  174. mtspr MAS1, \scratch
  175. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  176. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  177. mtspr MAS2, \scratch
  178. lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
  179. ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
  180. mtspr MAS3, \scratch
  181. lis \scratch, \phy_high@h
  182. ori \scratch, \scratch, \phy_high@l
  183. mtspr MAS7, \scratch
  184. isync
  185. msync
  186. tlbwe
  187. isync
  188. .endm
  189. .macro delete_tlb1_entry esel scratch
  190. lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
  191. ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
  192. mtspr MAS0, \scratch
  193. li \scratch, 0
  194. mtspr MAS1, \scratch
  195. isync
  196. msync
  197. tlbwe
  198. isync
  199. .endm
  200. .macro delete_tlb0_entry esel epn wimg scratch
  201. lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
  202. ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
  203. mtspr MAS0, \scratch
  204. li \scratch, 0
  205. mtspr MAS1, \scratch
  206. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  207. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  208. mtspr MAS2, \scratch
  209. isync
  210. msync
  211. tlbwe
  212. isync
  213. .endm
  214. /* Interrupt vectors do not fit in minimal SPL. */
  215. #if !defined(MINIMAL_SPL)
  216. /* Setup interrupt vectors */
  217. lis r1,CONFIG_SYS_MONITOR_BASE@h
  218. mtspr IVPR,r1
  219. li r4,CriticalInput@l
  220. mtspr IVOR0,r4 /* 0: Critical input */
  221. li r4,MachineCheck@l
  222. mtspr IVOR1,r4 /* 1: Machine check */
  223. li r4,DataStorage@l
  224. mtspr IVOR2,r4 /* 2: Data storage */
  225. li r4,InstStorage@l
  226. mtspr IVOR3,r4 /* 3: Instruction storage */
  227. li r4,ExtInterrupt@l
  228. mtspr IVOR4,r4 /* 4: External interrupt */
  229. li r4,Alignment@l
  230. mtspr IVOR5,r4 /* 5: Alignment */
  231. li r4,ProgramCheck@l
  232. mtspr IVOR6,r4 /* 6: Program check */
  233. li r4,FPUnavailable@l
  234. mtspr IVOR7,r4 /* 7: floating point unavailable */
  235. li r4,SystemCall@l
  236. mtspr IVOR8,r4 /* 8: System call */
  237. /* 9: Auxiliary processor unavailable(unsupported) */
  238. li r4,Decrementer@l
  239. mtspr IVOR10,r4 /* 10: Decrementer */
  240. li r4,IntervalTimer@l
  241. mtspr IVOR11,r4 /* 11: Interval timer */
  242. li r4,WatchdogTimer@l
  243. mtspr IVOR12,r4 /* 12: Watchdog timer */
  244. li r4,DataTLBError@l
  245. mtspr IVOR13,r4 /* 13: Data TLB error */
  246. li r4,InstructionTLBError@l
  247. mtspr IVOR14,r4 /* 14: Instruction TLB error */
  248. li r4,DebugBreakpoint@l
  249. mtspr IVOR15,r4 /* 15: Debug */
  250. #endif
  251. /* Clear and set up some registers. */
  252. li r0,0x0000
  253. lis r1,0xffff
  254. mtspr DEC,r0 /* prevent dec exceptions */
  255. mttbl r0 /* prevent fit & wdt exceptions */
  256. mttbu r0
  257. mtspr TSR,r1 /* clear all timer exception status */
  258. mtspr TCR,r0 /* disable all */
  259. mtspr ESR,r0 /* clear exception syndrome register */
  260. mtspr MCSR,r0 /* machine check syndrome register */
  261. mtxer r0 /* clear integer exception register */
  262. #ifdef CONFIG_SYS_BOOK3E_HV
  263. mtspr MAS8,r0 /* make sure MAS8 is clear */
  264. #endif
  265. /* Enable Time Base and Select Time Base Clock */
  266. lis r0,HID0_EMCP@h /* Enable machine check */
  267. #if defined(CONFIG_ENABLE_36BIT_PHYS)
  268. ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
  269. #endif
  270. #ifndef CONFIG_E500MC
  271. ori r0,r0,HID0_TBEN@l /* Enable Timebase */
  272. #endif
  273. mtspr HID0,r0
  274. #if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
  275. li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
  276. mfspr r3,PVR
  277. andi. r3,r3, 0xff
  278. cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
  279. blt 1f
  280. /* Set MBDD bit also */
  281. ori r0, r0, HID1_MBDD@l
  282. 1:
  283. mtspr HID1,r0
  284. #endif
  285. #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  286. mfspr r3,SPRN_HDBCR1
  287. oris r3,r3,0x0100
  288. mtspr SPRN_HDBCR1,r3
  289. #endif
  290. /* Enable Branch Prediction */
  291. #if defined(CONFIG_BTB)
  292. lis r0,BUCSR_ENABLE@h
  293. ori r0,r0,BUCSR_ENABLE@l
  294. mtspr SPRN_BUCSR,r0
  295. #endif
  296. #if defined(CONFIG_SYS_INIT_DBCR)
  297. lis r1,0xffff
  298. ori r1,r1,0xffff
  299. mtspr DBSR,r1 /* Clear all status bits */
  300. lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
  301. ori r0,r0,CONFIG_SYS_INIT_DBCR@l
  302. mtspr DBCR0,r0
  303. #endif
  304. #ifdef CONFIG_MPC8569
  305. #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
  306. #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
  307. /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
  308. * use address space which is more than 12bits, and it must be done in
  309. * the 4K boot page. So we set this bit here.
  310. */
  311. /* create a temp mapping TLB0[0] for LBCR */
  312. create_tlb0_entry 0, \
  313. 0, BOOKE_PAGESZ_4K, \
  314. CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
  315. CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
  316. 0, r6
  317. /* Set LBCR register */
  318. lis r4,CONFIG_SYS_LBCR_ADDR@h
  319. ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
  320. lis r5,CONFIG_SYS_LBC_LBCR@h
  321. ori r5,r5,CONFIG_SYS_LBC_LBCR@l
  322. stw r5,0(r4)
  323. isync
  324. /* invalidate this temp TLB */
  325. lis r4,CONFIG_SYS_LBC_ADDR@h
  326. ori r4,r4,CONFIG_SYS_LBC_ADDR@l
  327. tlbivax 0,r4
  328. isync
  329. #endif /* CONFIG_MPC8569 */
  330. /*
  331. * Search for the TLB that covers the code we're executing, and shrink it
  332. * so that it covers only this 4K page. That will ensure that any other
  333. * TLB we create won't interfere with it. We assume that the TLB exists,
  334. * which is why we don't check the Valid bit of MAS1. We also assume
  335. * it is in TLB1.
  336. *
  337. * This is necessary, for example, when booting from the on-chip ROM,
  338. * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
  339. */
  340. bl nexti /* Find our address */
  341. nexti: mflr r1 /* R1 = our PC */
  342. li r2, 0
  343. mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
  344. isync
  345. msync
  346. tlbsx 0, r1 /* This must succeed */
  347. mfspr r14, MAS0 /* Save ESEL for later */
  348. rlwinm r14, r14, 16, 0xfff
  349. /* Set the size of the TLB to 4KB */
  350. mfspr r3, MAS1
  351. li r2, 0xF80
  352. andc r3, r3, r2 /* Clear the TSIZE bits */
  353. ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
  354. oris r3, r3, MAS1_IPROT@h
  355. mtspr MAS1, r3
  356. /*
  357. * Set the base address of the TLB to our PC. We assume that
  358. * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
  359. */
  360. lis r3, MAS2_EPN@h
  361. ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
  362. and r1, r1, r3 /* Our PC, rounded down to the nearest page */
  363. mfspr r2, MAS2
  364. andc r2, r2, r3
  365. or r2, r2, r1
  366. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  367. cmpwi r27,0
  368. beq 1f
  369. andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
  370. rlwinm r2, r2, 0, ~MAS2_I
  371. ori r2, r2, MAS2_G
  372. 1:
  373. #endif
  374. mtspr MAS2, r2 /* Set the EPN to our PC base address */
  375. mfspr r2, MAS3
  376. andc r2, r2, r3
  377. or r2, r2, r1
  378. mtspr MAS3, r2 /* Set the RPN to our PC base address */
  379. isync
  380. msync
  381. tlbwe
  382. /*
  383. * Clear out any other TLB entries that may exist, to avoid conflicts.
  384. * Our TLB entry is in r14.
  385. */
  386. li r0, TLBIVAX_ALL | TLBIVAX_TLB0
  387. tlbivax 0, r0
  388. tlbsync
  389. mfspr r4, SPRN_TLB1CFG
  390. rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
  391. li r3, 0
  392. mtspr MAS1, r3
  393. 1: cmpw r3, r14
  394. rlwinm r5, r3, 16, MAS0_ESEL_MSK
  395. addi r3, r3, 1
  396. beq 2f /* skip the entry we're executing from */
  397. oris r5, r5, MAS0_TLBSEL(1)@h
  398. mtspr MAS0, r5
  399. isync
  400. tlbwe
  401. isync
  402. msync
  403. 2: cmpw r3, r4
  404. blt 1b
  405. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
  406. !defined(CONFIG_SECURE_BOOT)
  407. /*
  408. * TLB entry for debuggging in AS1
  409. * Create temporary TLB entry in AS0 to handle debug exception
  410. * As on debug exception MSR is cleared i.e. Address space is changed
  411. * to 0. A TLB entry (in AS0) is required to handle debug exception generated
  412. * in AS1.
  413. */
  414. #ifdef NOR_BOOT
  415. /*
  416. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  417. * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
  418. * and this window is outside of 4K boot window.
  419. */
  420. create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
  421. 0, BOOKE_PAGESZ_4M, \
  422. CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
  423. 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  424. 0, r6
  425. #else
  426. /*
  427. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  428. * because "nexti" will resize TLB to 4K
  429. */
  430. create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
  431. 0, BOOKE_PAGESZ_256K, \
  432. CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
  433. CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
  434. 0, r6
  435. #endif
  436. #endif
  437. /*
  438. * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
  439. * location is not where we want it. This typically happens on a 36-bit
  440. * system, where we want to move CCSR to near the top of 36-bit address space.
  441. *
  442. * To move CCSR, we create two temporary TLBs, one for the old location, and
  443. * another for the new location. On CoreNet systems, we also need to create
  444. * a special, temporary LAW.
  445. *
  446. * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
  447. * long-term TLBs, so we use TLB0 here.
  448. */
  449. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
  450. #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
  451. #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
  452. #endif
  453. create_ccsr_new_tlb:
  454. /*
  455. * Create a TLB for the new location of CCSR. Register R8 is reserved
  456. * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
  457. */
  458. lis r8, CONFIG_SYS_CCSRBAR@h
  459. ori r8, r8, CONFIG_SYS_CCSRBAR@l
  460. lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
  461. ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
  462. create_tlb0_entry 0, \
  463. 0, BOOKE_PAGESZ_4K, \
  464. CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
  465. CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
  466. CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
  467. /*
  468. * Create a TLB for the current location of CCSR. Register R9 is reserved
  469. * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
  470. */
  471. create_ccsr_old_tlb:
  472. create_tlb0_entry 1, \
  473. 0, BOOKE_PAGESZ_4K, \
  474. CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
  475. CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
  476. 0, r3 /* The default CCSR address is always a 32-bit number */
  477. /*
  478. * We have a TLB for what we think is the current (old) CCSR. Let's
  479. * verify that, otherwise we won't be able to move it.
  480. * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
  481. * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
  482. */
  483. verify_old_ccsr:
  484. lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
  485. ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
  486. #ifdef CONFIG_FSL_CORENET
  487. lwz r1, 4(r9) /* CCSRBARL */
  488. #else
  489. lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
  490. slwi r1, r1, 12
  491. #endif
  492. cmpl 0, r0, r1
  493. /*
  494. * If the value we read from CCSRBARL is not what we expect, then
  495. * enter an infinite loop. This will at least allow a debugger to
  496. * halt execution and examine TLBs, etc. There's no point in going
  497. * on.
  498. */
  499. infinite_debug_loop:
  500. bne infinite_debug_loop
  501. #ifdef CONFIG_FSL_CORENET
  502. #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
  503. #define LAW_SIZE_4K 0xb
  504. #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
  505. #define CCSRAR_C 0x80000000 /* Commit */
  506. create_temp_law:
  507. /*
  508. * On CoreNet systems, we create the temporary LAW using a special LAW
  509. * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
  510. */
  511. lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  512. ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  513. lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  514. ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  515. lis r2, CCSRBAR_LAWAR@h
  516. ori r2, r2, CCSRBAR_LAWAR@l
  517. stw r0, 0xc00(r9) /* LAWBARH0 */
  518. stw r1, 0xc04(r9) /* LAWBARL0 */
  519. sync
  520. stw r2, 0xc08(r9) /* LAWAR0 */
  521. /*
  522. * Read back from LAWAR to ensure the update is complete. e500mc
  523. * cores also require an isync.
  524. */
  525. lwz r0, 0xc08(r9) /* LAWAR0 */
  526. isync
  527. /*
  528. * Read the current CCSRBARH and CCSRBARL using load word instructions.
  529. * Follow this with an isync instruction. This forces any outstanding
  530. * accesses to configuration space to completion.
  531. */
  532. read_old_ccsrbar:
  533. lwz r0, 0(r9) /* CCSRBARH */
  534. lwz r0, 4(r9) /* CCSRBARL */
  535. isync
  536. /*
  537. * Write the new values for CCSRBARH and CCSRBARL to their old
  538. * locations. The CCSRBARH has a shadow register. When the CCSRBARH
  539. * has a new value written it loads a CCSRBARH shadow register. When
  540. * the CCSRBARL is written, the CCSRBARH shadow register contents
  541. * along with the CCSRBARL value are loaded into the CCSRBARH and
  542. * CCSRBARL registers, respectively. Follow this with a sync
  543. * instruction.
  544. */
  545. write_new_ccsrbar:
  546. lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  547. ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  548. lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  549. ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  550. lis r2, CCSRAR_C@h
  551. ori r2, r2, CCSRAR_C@l
  552. stw r0, 0(r9) /* Write to CCSRBARH */
  553. sync /* Make sure we write to CCSRBARH first */
  554. stw r1, 4(r9) /* Write to CCSRBARL */
  555. sync
  556. /*
  557. * Write a 1 to the commit bit (C) of CCSRAR at the old location.
  558. * Follow this with a sync instruction.
  559. */
  560. stw r2, 8(r9)
  561. sync
  562. /* Delete the temporary LAW */
  563. delete_temp_law:
  564. li r1, 0
  565. stw r1, 0xc08(r8)
  566. sync
  567. stw r1, 0xc00(r8)
  568. stw r1, 0xc04(r8)
  569. sync
  570. #else /* #ifdef CONFIG_FSL_CORENET */
  571. write_new_ccsrbar:
  572. /*
  573. * Read the current value of CCSRBAR using a load word instruction
  574. * followed by an isync. This forces all accesses to configuration
  575. * space to complete.
  576. */
  577. sync
  578. lwz r0, 0(r9)
  579. isync
  580. /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
  581. #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
  582. (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
  583. /* Write the new value to CCSRBAR. */
  584. lis r0, CCSRBAR_PHYS_RS12@h
  585. ori r0, r0, CCSRBAR_PHYS_RS12@l
  586. stw r0, 0(r9)
  587. sync
  588. /*
  589. * The manual says to perform a load of an address that does not
  590. * access configuration space or the on-chip SRAM using an existing TLB,
  591. * but that doesn't appear to be necessary. We will do the isync,
  592. * though.
  593. */
  594. isync
  595. /*
  596. * Read the contents of CCSRBAR from its new location, followed by
  597. * another isync.
  598. */
  599. lwz r0, 0(r8)
  600. isync
  601. #endif /* #ifdef CONFIG_FSL_CORENET */
  602. /* Delete the temporary TLBs */
  603. delete_temp_tlbs:
  604. delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
  605. delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
  606. #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
  607. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  608. create_ccsr_l2_tlb:
  609. /*
  610. * Create a TLB for the MMR location of CCSR
  611. * to access L2CSR0 register
  612. */
  613. create_tlb0_entry 0, \
  614. 0, BOOKE_PAGESZ_4K, \
  615. CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
  616. CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
  617. CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
  618. enable_l2_cluster_l2:
  619. /* enable L2 cache */
  620. lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
  621. ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
  622. li r4, 33 /* stash id */
  623. stw r4, 4(r3)
  624. lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
  625. ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
  626. sync
  627. stw r4, 0(r3) /* invalidate L2 */
  628. 1: sync
  629. lwz r0, 0(r3)
  630. twi 0, r0, 0
  631. isync
  632. and. r1, r0, r4
  633. bne 1b
  634. lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
  635. ori r4, r4, (L2CSR0_L2REP_MODE)@l
  636. sync
  637. stw r4, 0(r3) /* enable L2 */
  638. delete_ccsr_l2_tlb:
  639. delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
  640. #endif
  641. /*
  642. * Enable the L1. On e6500, this has to be done
  643. * after the L2 is up.
  644. */
  645. #ifdef CONFIG_SYS_CACHE_STASHING
  646. /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
  647. li r2,(32 + 0)
  648. mtspr L1CSR2,r2
  649. #endif
  650. /* Enable/invalidate the I-Cache */
  651. lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  652. ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  653. mtspr SPRN_L1CSR1,r2
  654. 1:
  655. mfspr r3,SPRN_L1CSR1
  656. and. r1,r3,r2
  657. bne 1b
  658. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  659. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  660. mtspr SPRN_L1CSR1,r3
  661. isync
  662. 2:
  663. mfspr r3,SPRN_L1CSR1
  664. andi. r1,r3,L1CSR1_ICE@l
  665. beq 2b
  666. /* Enable/invalidate the D-Cache */
  667. lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
  668. ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
  669. mtspr SPRN_L1CSR0,r2
  670. 1:
  671. mfspr r3,SPRN_L1CSR0
  672. and. r1,r3,r2
  673. bne 1b
  674. lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
  675. ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
  676. mtspr SPRN_L1CSR0,r3
  677. isync
  678. 2:
  679. mfspr r3,SPRN_L1CSR0
  680. andi. r1,r3,L1CSR0_DCE@l
  681. beq 2b
  682. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  683. #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
  684. #define LAW_SIZE_1M 0x13
  685. #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
  686. cmpwi r27,0
  687. beq 9f
  688. /*
  689. * Create a TLB entry for CCSR
  690. *
  691. * We're executing out of TLB1 entry in r14, and that's the only
  692. * TLB entry that exists. To allocate some TLB entries for our
  693. * own use, flip a bit high enough that we won't flip it again
  694. * via incrementing.
  695. */
  696. xori r8, r14, 32
  697. lis r0, MAS0_TLBSEL(1)@h
  698. rlwimi r0, r8, 16, MAS0_ESEL_MSK
  699. lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
  700. ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
  701. lis r7, CONFIG_SYS_CCSRBAR@h
  702. ori r7, r7, CONFIG_SYS_CCSRBAR@l
  703. ori r2, r7, MAS2_I|MAS2_G
  704. lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
  705. ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
  706. lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  707. ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  708. mtspr MAS0, r0
  709. mtspr MAS1, r1
  710. mtspr MAS2, r2
  711. mtspr MAS3, r3
  712. mtspr MAS7, r4
  713. isync
  714. tlbwe
  715. isync
  716. msync
  717. /* Map DCSR temporarily to physical address zero */
  718. li r0, 0
  719. lis r3, DCSRBAR_LAWAR@h
  720. ori r3, r3, DCSRBAR_LAWAR@l
  721. stw r0, 0xc00(r7) /* LAWBARH0 */
  722. stw r0, 0xc04(r7) /* LAWBARL0 */
  723. sync
  724. stw r3, 0xc08(r7) /* LAWAR0 */
  725. /* Read back from LAWAR to ensure the update is complete. */
  726. lwz r3, 0xc08(r7) /* LAWAR0 */
  727. isync
  728. /* Create a TLB entry for DCSR at zero */
  729. addi r9, r8, 1
  730. lis r0, MAS0_TLBSEL(1)@h
  731. rlwimi r0, r9, 16, MAS0_ESEL_MSK
  732. lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
  733. ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
  734. li r6, 0 /* DCSR effective address */
  735. ori r2, r6, MAS2_I|MAS2_G
  736. li r3, MAS3_SW|MAS3_SR
  737. li r4, 0
  738. mtspr MAS0, r0
  739. mtspr MAS1, r1
  740. mtspr MAS2, r2
  741. mtspr MAS3, r3
  742. mtspr MAS7, r4
  743. isync
  744. tlbwe
  745. isync
  746. msync
  747. /* enable the timebase */
  748. #define CTBENR 0xe2084
  749. li r3, 1
  750. addis r4, r7, CTBENR@ha
  751. stw r3, CTBENR@l(r4)
  752. lwz r3, CTBENR@l(r4)
  753. twi 0,r3,0
  754. isync
  755. .macro erratum_set_ccsr offset value
  756. addis r3, r7, \offset@ha
  757. lis r4, \value@h
  758. addi r3, r3, \offset@l
  759. ori r4, r4, \value@l
  760. bl erratum_set_value
  761. .endm
  762. .macro erratum_set_dcsr offset value
  763. addis r3, r6, \offset@ha
  764. lis r4, \value@h
  765. addi r3, r3, \offset@l
  766. ori r4, r4, \value@l
  767. bl erratum_set_value
  768. .endm
  769. erratum_set_dcsr 0xb0e08 0xe0201800
  770. erratum_set_dcsr 0xb0e18 0xe0201800
  771. erratum_set_dcsr 0xb0e38 0xe0400000
  772. erratum_set_dcsr 0xb0008 0x00900000
  773. erratum_set_dcsr 0xb0e40 0xe00a0000
  774. erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
  775. #ifdef CONFIG_RAMBOOT_PBL
  776. erratum_set_ccsr 0x10f00 0x495e5000
  777. #else
  778. erratum_set_ccsr 0x10f00 0x415e5000
  779. #endif
  780. erratum_set_ccsr 0x11f00 0x415e5000
  781. /* Make temp mapping uncacheable again, if it was initially */
  782. bl 2f
  783. 2: mflr r3
  784. tlbsx 0, r3
  785. mfspr r4, MAS2
  786. rlwimi r4, r15, 0, MAS2_I
  787. rlwimi r4, r15, 0, MAS2_G
  788. mtspr MAS2, r4
  789. isync
  790. tlbwe
  791. isync
  792. msync
  793. /* Clear the cache */
  794. lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  795. ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  796. sync
  797. isync
  798. mtspr SPRN_L1CSR1,r3
  799. isync
  800. 2: sync
  801. mfspr r4,SPRN_L1CSR1
  802. and. r4,r4,r3
  803. bne 2b
  804. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  805. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  806. sync
  807. isync
  808. mtspr SPRN_L1CSR1,r3
  809. isync
  810. 2: sync
  811. mfspr r4,SPRN_L1CSR1
  812. and. r4,r4,r3
  813. beq 2b
  814. /* Remove temporary mappings */
  815. lis r0, MAS0_TLBSEL(1)@h
  816. rlwimi r0, r9, 16, MAS0_ESEL_MSK
  817. li r3, 0
  818. mtspr MAS0, r0
  819. mtspr MAS1, r3
  820. isync
  821. tlbwe
  822. isync
  823. msync
  824. li r3, 0
  825. stw r3, 0xc08(r7) /* LAWAR0 */
  826. lwz r3, 0xc08(r7)
  827. isync
  828. lis r0, MAS0_TLBSEL(1)@h
  829. rlwimi r0, r8, 16, MAS0_ESEL_MSK
  830. li r3, 0
  831. mtspr MAS0, r0
  832. mtspr MAS1, r3
  833. isync
  834. tlbwe
  835. isync
  836. msync
  837. b 9f
  838. /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
  839. erratum_set_value:
  840. /* Lock two cache lines into I-Cache */
  841. sync
  842. mfspr r11, SPRN_L1CSR1
  843. rlwinm r11, r11, 0, ~L1CSR1_ICUL
  844. sync
  845. isync
  846. mtspr SPRN_L1CSR1, r11
  847. isync
  848. mflr r12
  849. bl 5f
  850. 5: mflr r5
  851. addi r5, r5, 2f - 5b
  852. icbtls 0, 0, r5
  853. addi r5, r5, 64
  854. sync
  855. mfspr r11, SPRN_L1CSR1
  856. 3: andi. r11, r11, L1CSR1_ICUL
  857. bne 3b
  858. icbtls 0, 0, r5
  859. addi r5, r5, 64
  860. sync
  861. mfspr r11, SPRN_L1CSR1
  862. 3: andi. r11, r11, L1CSR1_ICUL
  863. bne 3b
  864. b 2f
  865. .align 6
  866. /* Inside a locked cacheline, wait a while, write, then wait a while */
  867. 2: sync
  868. mfspr r5, SPRN_TBRL
  869. addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
  870. 4: mfspr r5, SPRN_TBRL
  871. subf. r5, r5, r11
  872. bgt 4b
  873. stw r4, 0(r3)
  874. mfspr r5, SPRN_TBRL
  875. addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
  876. 4: mfspr r5, SPRN_TBRL
  877. subf. r5, r5, r11
  878. bgt 4b
  879. sync
  880. /*
  881. * Fill out the rest of this cache line and the next with nops,
  882. * to ensure that nothing outside the locked area will be
  883. * fetched due to a branch.
  884. */
  885. .rept 19
  886. nop
  887. .endr
  888. sync
  889. mfspr r11, SPRN_L1CSR1
  890. rlwinm r11, r11, 0, ~L1CSR1_ICUL
  891. sync
  892. isync
  893. mtspr SPRN_L1CSR1, r11
  894. isync
  895. mtlr r12
  896. blr
  897. 9:
  898. #endif
  899. create_init_ram_area:
  900. lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
  901. ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
  902. #ifdef NOR_BOOT
  903. /* create a temp mapping in AS=1 to the 4M boot window */
  904. create_tlb1_entry 15, \
  905. 1, BOOKE_PAGESZ_4M, \
  906. CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
  907. 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  908. 0, r6
  909. #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
  910. /* create a temp mapping in AS = 1 for Flash mapping
  911. * created by PBL for ISBC code
  912. */
  913. create_tlb1_entry 15, \
  914. 1, BOOKE_PAGESZ_1M, \
  915. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  916. CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  917. 0, r6
  918. #else
  919. /*
  920. * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
  921. * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
  922. */
  923. create_tlb1_entry 15, \
  924. 1, BOOKE_PAGESZ_1M, \
  925. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  926. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  927. 0, r6
  928. #endif
  929. /* create a temp mapping in AS=1 to the stack */
  930. #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
  931. defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
  932. create_tlb1_entry 14, \
  933. 1, BOOKE_PAGESZ_16K, \
  934. CONFIG_SYS_INIT_RAM_ADDR, 0, \
  935. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
  936. CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
  937. #else
  938. create_tlb1_entry 14, \
  939. 1, BOOKE_PAGESZ_16K, \
  940. CONFIG_SYS_INIT_RAM_ADDR, 0, \
  941. CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
  942. 0, r6
  943. #endif
  944. lis r6,MSR_IS|MSR_DS|MSR_DE@h
  945. ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
  946. lis r7,switch_as@h
  947. ori r7,r7,switch_as@l
  948. mtspr SPRN_SRR0,r7
  949. mtspr SPRN_SRR1,r6
  950. rfi
  951. switch_as:
  952. /* L1 DCache is used for initial RAM */
  953. /* Allocate Initial RAM in data cache.
  954. */
  955. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  956. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  957. mfspr r2, L1CFG0
  958. andi. r2, r2, 0x1ff
  959. /* cache size * 1024 / (2 * L1 line size) */
  960. slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
  961. mtctr r2
  962. li r0,0
  963. 1:
  964. dcbz r0,r3
  965. dcbtls 0,r0,r3
  966. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  967. bdnz 1b
  968. /* Jump out the last 4K page and continue to 'normal' start */
  969. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
  970. /* We assume that we're already running at the address we're linked at */
  971. b _start_cont
  972. #else
  973. /* Calculate absolute address in FLASH and jump there */
  974. /*--------------------------------------------------------------*/
  975. lis r3,CONFIG_SYS_MONITOR_BASE@h
  976. ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
  977. addi r3,r3,_start_cont - _start
  978. mtlr r3
  979. blr
  980. #endif
  981. .text
  982. .globl _start
  983. _start:
  984. .long 0x27051956 /* U-BOOT Magic Number */
  985. .globl version_string
  986. version_string:
  987. .ascii U_BOOT_VERSION_STRING, "\0"
  988. .align 4
  989. .globl _start_cont
  990. _start_cont:
  991. /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
  992. lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
  993. ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
  994. li r0,0
  995. stw r0,0(r3) /* Terminate Back Chain */
  996. stw r0,+4(r3) /* NULL return address. */
  997. mr r1,r3 /* Transfer to SP(r1) */
  998. GET_GOT
  999. /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
  1000. mr r3, r24
  1001. bl cpu_init_early_f
  1002. /* switch back to AS = 0 */
  1003. lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
  1004. ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
  1005. mtmsr r3
  1006. isync
  1007. bl cpu_init_f /* return boot_flag for calling board_init_f */
  1008. bl board_init_f
  1009. isync
  1010. /* NOTREACHED - board_init_f() does not return */
  1011. #ifndef MINIMAL_SPL
  1012. .globl _start_of_vectors
  1013. _start_of_vectors:
  1014. /* Critical input. */
  1015. CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
  1016. /* Machine check */
  1017. MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  1018. /* Data Storage exception. */
  1019. STD_EXCEPTION(0x0300, DataStorage, UnknownException)
  1020. /* Instruction Storage exception. */
  1021. STD_EXCEPTION(0x0400, InstStorage, UnknownException)
  1022. /* External Interrupt exception. */
  1023. STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
  1024. /* Alignment exception. */
  1025. Alignment:
  1026. EXCEPTION_PROLOG(SRR0, SRR1)
  1027. mfspr r4,DAR
  1028. stw r4,_DAR(r21)
  1029. mfspr r5,DSISR
  1030. stw r5,_DSISR(r21)
  1031. addi r3,r1,STACK_FRAME_OVERHEAD
  1032. EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
  1033. MSR_KERNEL, COPY_EE)
  1034. /* Program check exception */
  1035. ProgramCheck:
  1036. EXCEPTION_PROLOG(SRR0, SRR1)
  1037. addi r3,r1,STACK_FRAME_OVERHEAD
  1038. EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
  1039. MSR_KERNEL, COPY_EE)
  1040. /* No FPU on MPC85xx. This exception is not supposed to happen.
  1041. */
  1042. STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
  1043. /*
  1044. * r0 - SYSCALL number
  1045. * r3-... arguments
  1046. */
  1047. SystemCall:
  1048. addis r11,r0,0 /* get functions table addr */
  1049. ori r11,r11,0 /* Note: this code is patched in trap_init */
  1050. addis r12,r0,0 /* get number of functions */
  1051. ori r12,r12,0
  1052. cmplw 0,r0,r12
  1053. bge 1f
  1054. rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
  1055. add r11,r11,r0
  1056. lwz r11,0(r11)
  1057. li r20,0xd00-4 /* Get stack pointer */
  1058. lwz r12,0(r20)
  1059. subi r12,r12,12 /* Adjust stack pointer */
  1060. li r0,0xc00+_end_back-SystemCall
  1061. cmplw 0,r0,r12 /* Check stack overflow */
  1062. bgt 1f
  1063. stw r12,0(r20)
  1064. mflr r0
  1065. stw r0,0(r12)
  1066. mfspr r0,SRR0
  1067. stw r0,4(r12)
  1068. mfspr r0,SRR1
  1069. stw r0,8(r12)
  1070. li r12,0xc00+_back-SystemCall
  1071. mtlr r12
  1072. mtspr SRR0,r11
  1073. 1: SYNC
  1074. rfi
  1075. _back:
  1076. mfmsr r11 /* Disable interrupts */
  1077. li r12,0
  1078. ori r12,r12,MSR_EE
  1079. andc r11,r11,r12
  1080. SYNC /* Some chip revs need this... */
  1081. mtmsr r11
  1082. SYNC
  1083. li r12,0xd00-4 /* restore regs */
  1084. lwz r12,0(r12)
  1085. lwz r11,0(r12)
  1086. mtlr r11
  1087. lwz r11,4(r12)
  1088. mtspr SRR0,r11
  1089. lwz r11,8(r12)
  1090. mtspr SRR1,r11
  1091. addi r12,r12,12 /* Adjust stack pointer */
  1092. li r20,0xd00-4
  1093. stw r12,0(r20)
  1094. SYNC
  1095. rfi
  1096. _end_back:
  1097. STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
  1098. STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
  1099. STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
  1100. STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
  1101. STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
  1102. CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
  1103. .globl _end_of_vectors
  1104. _end_of_vectors:
  1105. . = . + (0x100 - ( . & 0xff )) /* align for debug */
  1106. /*
  1107. * This code finishes saving the registers to the exception frame
  1108. * and jumps to the appropriate handler for the exception.
  1109. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  1110. * r23 is the address of the handler.
  1111. */
  1112. .globl transfer_to_handler
  1113. transfer_to_handler:
  1114. SAVE_GPR(7, r21)
  1115. SAVE_4GPRS(8, r21)
  1116. SAVE_8GPRS(12, r21)
  1117. SAVE_8GPRS(24, r21)
  1118. li r22,0
  1119. stw r22,RESULT(r21)
  1120. mtspr SPRG2,r22 /* r1 is now kernel sp */
  1121. mtctr r23 /* virtual address of handler */
  1122. mtmsr r20
  1123. bctrl
  1124. int_return:
  1125. mfmsr r28 /* Disable interrupts */
  1126. li r4,0
  1127. ori r4,r4,MSR_EE
  1128. andc r28,r28,r4
  1129. SYNC /* Some chip revs need this... */
  1130. mtmsr r28
  1131. SYNC
  1132. lwz r2,_CTR(r1)
  1133. lwz r0,_LINK(r1)
  1134. mtctr r2
  1135. mtlr r0
  1136. lwz r2,_XER(r1)
  1137. lwz r0,_CCR(r1)
  1138. mtspr XER,r2
  1139. mtcrf 0xFF,r0
  1140. REST_10GPRS(3, r1)
  1141. REST_10GPRS(13, r1)
  1142. REST_8GPRS(23, r1)
  1143. REST_GPR(31, r1)
  1144. lwz r2,_NIP(r1) /* Restore environment */
  1145. lwz r0,_MSR(r1)
  1146. mtspr SRR0,r2
  1147. mtspr SRR1,r0
  1148. lwz r0,GPR0(r1)
  1149. lwz r2,GPR2(r1)
  1150. lwz r1,GPR1(r1)
  1151. SYNC
  1152. rfi
  1153. crit_return:
  1154. mfmsr r28 /* Disable interrupts */
  1155. li r4,0
  1156. ori r4,r4,MSR_EE
  1157. andc r28,r28,r4
  1158. SYNC /* Some chip revs need this... */
  1159. mtmsr r28
  1160. SYNC
  1161. lwz r2,_CTR(r1)
  1162. lwz r0,_LINK(r1)
  1163. mtctr r2
  1164. mtlr r0
  1165. lwz r2,_XER(r1)
  1166. lwz r0,_CCR(r1)
  1167. mtspr XER,r2
  1168. mtcrf 0xFF,r0
  1169. REST_10GPRS(3, r1)
  1170. REST_10GPRS(13, r1)
  1171. REST_8GPRS(23, r1)
  1172. REST_GPR(31, r1)
  1173. lwz r2,_NIP(r1) /* Restore environment */
  1174. lwz r0,_MSR(r1)
  1175. mtspr SPRN_CSRR0,r2
  1176. mtspr SPRN_CSRR1,r0
  1177. lwz r0,GPR0(r1)
  1178. lwz r2,GPR2(r1)
  1179. lwz r1,GPR1(r1)
  1180. SYNC
  1181. rfci
  1182. mck_return:
  1183. mfmsr r28 /* Disable interrupts */
  1184. li r4,0
  1185. ori r4,r4,MSR_EE
  1186. andc r28,r28,r4
  1187. SYNC /* Some chip revs need this... */
  1188. mtmsr r28
  1189. SYNC
  1190. lwz r2,_CTR(r1)
  1191. lwz r0,_LINK(r1)
  1192. mtctr r2
  1193. mtlr r0
  1194. lwz r2,_XER(r1)
  1195. lwz r0,_CCR(r1)
  1196. mtspr XER,r2
  1197. mtcrf 0xFF,r0
  1198. REST_10GPRS(3, r1)
  1199. REST_10GPRS(13, r1)
  1200. REST_8GPRS(23, r1)
  1201. REST_GPR(31, r1)
  1202. lwz r2,_NIP(r1) /* Restore environment */
  1203. lwz r0,_MSR(r1)
  1204. mtspr SPRN_MCSRR0,r2
  1205. mtspr SPRN_MCSRR1,r0
  1206. lwz r0,GPR0(r1)
  1207. lwz r2,GPR2(r1)
  1208. lwz r1,GPR1(r1)
  1209. SYNC
  1210. rfmci
  1211. /* Cache functions.
  1212. */
  1213. .globl flush_icache
  1214. flush_icache:
  1215. .globl invalidate_icache
  1216. invalidate_icache:
  1217. mfspr r0,L1CSR1
  1218. ori r0,r0,L1CSR1_ICFI
  1219. msync
  1220. isync
  1221. mtspr L1CSR1,r0
  1222. isync
  1223. blr /* entire I cache */
  1224. .globl invalidate_dcache
  1225. invalidate_dcache:
  1226. mfspr r0,L1CSR0
  1227. ori r0,r0,L1CSR0_DCFI
  1228. msync
  1229. isync
  1230. mtspr L1CSR0,r0
  1231. isync
  1232. blr
  1233. .globl icache_enable
  1234. icache_enable:
  1235. mflr r8
  1236. bl invalidate_icache
  1237. mtlr r8
  1238. isync
  1239. mfspr r4,L1CSR1
  1240. ori r4,r4,0x0001
  1241. oris r4,r4,0x0001
  1242. mtspr L1CSR1,r4
  1243. isync
  1244. blr
  1245. .globl icache_disable
  1246. icache_disable:
  1247. mfspr r0,L1CSR1
  1248. lis r3,0
  1249. ori r3,r3,L1CSR1_ICE
  1250. andc r0,r0,r3
  1251. mtspr L1CSR1,r0
  1252. isync
  1253. blr
  1254. .globl icache_status
  1255. icache_status:
  1256. mfspr r3,L1CSR1
  1257. andi. r3,r3,L1CSR1_ICE
  1258. blr
  1259. .globl dcache_enable
  1260. dcache_enable:
  1261. mflr r8
  1262. bl invalidate_dcache
  1263. mtlr r8
  1264. isync
  1265. mfspr r0,L1CSR0
  1266. ori r0,r0,0x0001
  1267. oris r0,r0,0x0001
  1268. msync
  1269. isync
  1270. mtspr L1CSR0,r0
  1271. isync
  1272. blr
  1273. .globl dcache_disable
  1274. dcache_disable:
  1275. mfspr r3,L1CSR0
  1276. lis r4,0
  1277. ori r4,r4,L1CSR0_DCE
  1278. andc r3,r3,r4
  1279. mtspr L1CSR0,r3
  1280. isync
  1281. blr
  1282. .globl dcache_status
  1283. dcache_status:
  1284. mfspr r3,L1CSR0
  1285. andi. r3,r3,L1CSR0_DCE
  1286. blr
  1287. .globl get_pir
  1288. get_pir:
  1289. mfspr r3,PIR
  1290. blr
  1291. .globl get_pvr
  1292. get_pvr:
  1293. mfspr r3,PVR
  1294. blr
  1295. .globl get_svr
  1296. get_svr:
  1297. mfspr r3,SVR
  1298. blr
  1299. .globl wr_tcr
  1300. wr_tcr:
  1301. mtspr TCR,r3
  1302. blr
  1303. /*------------------------------------------------------------------------------- */
  1304. /* Function: in8 */
  1305. /* Description: Input 8 bits */
  1306. /*------------------------------------------------------------------------------- */
  1307. .globl in8
  1308. in8:
  1309. lbz r3,0x0000(r3)
  1310. blr
  1311. /*------------------------------------------------------------------------------- */
  1312. /* Function: out8 */
  1313. /* Description: Output 8 bits */
  1314. /*------------------------------------------------------------------------------- */
  1315. .globl out8
  1316. out8:
  1317. stb r4,0x0000(r3)
  1318. sync
  1319. blr
  1320. /*------------------------------------------------------------------------------- */
  1321. /* Function: out16 */
  1322. /* Description: Output 16 bits */
  1323. /*------------------------------------------------------------------------------- */
  1324. .globl out16
  1325. out16:
  1326. sth r4,0x0000(r3)
  1327. sync
  1328. blr
  1329. /*------------------------------------------------------------------------------- */
  1330. /* Function: out16r */
  1331. /* Description: Byte reverse and output 16 bits */
  1332. /*------------------------------------------------------------------------------- */
  1333. .globl out16r
  1334. out16r:
  1335. sthbrx r4,r0,r3
  1336. sync
  1337. blr
  1338. /*------------------------------------------------------------------------------- */
  1339. /* Function: out32 */
  1340. /* Description: Output 32 bits */
  1341. /*------------------------------------------------------------------------------- */
  1342. .globl out32
  1343. out32:
  1344. stw r4,0x0000(r3)
  1345. sync
  1346. blr
  1347. /*------------------------------------------------------------------------------- */
  1348. /* Function: out32r */
  1349. /* Description: Byte reverse and output 32 bits */
  1350. /*------------------------------------------------------------------------------- */
  1351. .globl out32r
  1352. out32r:
  1353. stwbrx r4,r0,r3
  1354. sync
  1355. blr
  1356. /*------------------------------------------------------------------------------- */
  1357. /* Function: in16 */
  1358. /* Description: Input 16 bits */
  1359. /*------------------------------------------------------------------------------- */
  1360. .globl in16
  1361. in16:
  1362. lhz r3,0x0000(r3)
  1363. blr
  1364. /*------------------------------------------------------------------------------- */
  1365. /* Function: in16r */
  1366. /* Description: Input 16 bits and byte reverse */
  1367. /*------------------------------------------------------------------------------- */
  1368. .globl in16r
  1369. in16r:
  1370. lhbrx r3,r0,r3
  1371. blr
  1372. /*------------------------------------------------------------------------------- */
  1373. /* Function: in32 */
  1374. /* Description: Input 32 bits */
  1375. /*------------------------------------------------------------------------------- */
  1376. .globl in32
  1377. in32:
  1378. lwz 3,0x0000(3)
  1379. blr
  1380. /*------------------------------------------------------------------------------- */
  1381. /* Function: in32r */
  1382. /* Description: Input 32 bits and byte reverse */
  1383. /*------------------------------------------------------------------------------- */
  1384. .globl in32r
  1385. in32r:
  1386. lwbrx r3,r0,r3
  1387. blr
  1388. #endif /* !MINIMAL_SPL */
  1389. /*------------------------------------------------------------------------------*/
  1390. /*
  1391. * void write_tlb(mas0, mas1, mas2, mas3, mas7)
  1392. */
  1393. .globl write_tlb
  1394. write_tlb:
  1395. mtspr MAS0,r3
  1396. mtspr MAS1,r4
  1397. mtspr MAS2,r5
  1398. mtspr MAS3,r6
  1399. #ifdef CONFIG_ENABLE_36BIT_PHYS
  1400. mtspr MAS7,r7
  1401. #endif
  1402. li r3,0
  1403. #ifdef CONFIG_SYS_BOOK3E_HV
  1404. mtspr MAS8,r3
  1405. #endif
  1406. isync
  1407. tlbwe
  1408. msync
  1409. isync
  1410. blr
  1411. /*
  1412. * void relocate_code (addr_sp, gd, addr_moni)
  1413. *
  1414. * This "function" does not return, instead it continues in RAM
  1415. * after relocating the monitor code.
  1416. *
  1417. * r3 = dest
  1418. * r4 = src
  1419. * r5 = length in bytes
  1420. * r6 = cachelinesize
  1421. */
  1422. .globl relocate_code
  1423. relocate_code:
  1424. mr r1,r3 /* Set new stack pointer */
  1425. mr r9,r4 /* Save copy of Init Data pointer */
  1426. mr r10,r5 /* Save copy of Destination Address */
  1427. GET_GOT
  1428. #ifndef CONFIG_SPL_SKIP_RELOCATE
  1429. mr r3,r5 /* Destination Address */
  1430. lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  1431. ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
  1432. lwz r5,GOT(__init_end)
  1433. sub r5,r5,r4
  1434. li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  1435. /*
  1436. * Fix GOT pointer:
  1437. *
  1438. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  1439. *
  1440. * Offset:
  1441. */
  1442. sub r15,r10,r4
  1443. /* First our own GOT */
  1444. add r12,r12,r15
  1445. /* the the one used by the C code */
  1446. add r30,r30,r15
  1447. /*
  1448. * Now relocate code
  1449. */
  1450. cmplw cr1,r3,r4
  1451. addi r0,r5,3
  1452. srwi. r0,r0,2
  1453. beq cr1,4f /* In place copy is not necessary */
  1454. beq 7f /* Protect against 0 count */
  1455. mtctr r0
  1456. bge cr1,2f
  1457. la r8,-4(r4)
  1458. la r7,-4(r3)
  1459. 1: lwzu r0,4(r8)
  1460. stwu r0,4(r7)
  1461. bdnz 1b
  1462. b 4f
  1463. 2: slwi r0,r0,2
  1464. add r8,r4,r0
  1465. add r7,r3,r0
  1466. 3: lwzu r0,-4(r8)
  1467. stwu r0,-4(r7)
  1468. bdnz 3b
  1469. /*
  1470. * Now flush the cache: note that we must start from a cache aligned
  1471. * address. Otherwise we might miss one cache line.
  1472. */
  1473. 4: cmpwi r6,0
  1474. add r5,r3,r5
  1475. beq 7f /* Always flush prefetch queue in any case */
  1476. subi r0,r6,1
  1477. andc r3,r3,r0
  1478. mr r4,r3
  1479. 5: dcbst 0,r4
  1480. add r4,r4,r6
  1481. cmplw r4,r5
  1482. blt 5b
  1483. sync /* Wait for all dcbst to complete on bus */
  1484. mr r4,r3
  1485. 6: icbi 0,r4
  1486. add r4,r4,r6
  1487. cmplw r4,r5
  1488. blt 6b
  1489. 7: sync /* Wait for all icbi to complete on bus */
  1490. isync
  1491. /*
  1492. * We are done. Do not return, instead branch to second part of board
  1493. * initialization, now running from RAM.
  1494. */
  1495. addi r0,r10,in_ram - _start
  1496. /*
  1497. * As IVPR is going to point RAM address,
  1498. * Make sure IVOR15 has valid opcode to support debugger
  1499. */
  1500. mtspr IVOR15,r0
  1501. /*
  1502. * Re-point the IVPR at RAM
  1503. */
  1504. mtspr IVPR,r10
  1505. mtlr r0
  1506. blr /* NEVER RETURNS! */
  1507. #endif
  1508. .globl in_ram
  1509. in_ram:
  1510. /*
  1511. * Relocation Function, r12 point to got2+0x8000
  1512. *
  1513. * Adjust got2 pointers, no need to check for 0, this code
  1514. * already puts a few entries in the table.
  1515. */
  1516. li r0,__got2_entries@sectoff@l
  1517. la r3,GOT(_GOT2_TABLE_)
  1518. lwz r11,GOT(_GOT2_TABLE_)
  1519. mtctr r0
  1520. sub r11,r3,r11
  1521. addi r3,r3,-4
  1522. 1: lwzu r0,4(r3)
  1523. cmpwi r0,0
  1524. beq- 2f
  1525. add r0,r0,r11
  1526. stw r0,0(r3)
  1527. 2: bdnz 1b
  1528. /*
  1529. * Now adjust the fixups and the pointers to the fixups
  1530. * in case we need to move ourselves again.
  1531. */
  1532. li r0,__fixup_entries@sectoff@l
  1533. lwz r3,GOT(_FIXUP_TABLE_)
  1534. cmpwi r0,0
  1535. mtctr r0
  1536. addi r3,r3,-4
  1537. beq 4f
  1538. 3: lwzu r4,4(r3)
  1539. lwzux r0,r4,r11
  1540. cmpwi r0,0
  1541. add r0,r0,r11
  1542. stw r4,0(r3)
  1543. beq- 5f
  1544. stw r0,0(r4)
  1545. 5: bdnz 3b
  1546. 4:
  1547. clear_bss:
  1548. /*
  1549. * Now clear BSS segment
  1550. */
  1551. lwz r3,GOT(__bss_start)
  1552. lwz r4,GOT(__bss_end)
  1553. cmplw 0,r3,r4
  1554. beq 6f
  1555. li r0,0
  1556. 5:
  1557. stw r0,0(r3)
  1558. addi r3,r3,4
  1559. cmplw 0,r3,r4
  1560. blt 5b
  1561. 6:
  1562. mr r3,r9 /* Init Data pointer */
  1563. mr r4,r10 /* Destination Address */
  1564. bl board_init_r
  1565. #ifndef MINIMAL_SPL
  1566. /*
  1567. * Copy exception vector code to low memory
  1568. *
  1569. * r3: dest_addr
  1570. * r7: source address, r8: end address, r9: target address
  1571. */
  1572. .globl trap_init
  1573. trap_init:
  1574. /* Update IVORs as per relocation */
  1575. mtspr IVPR,r3
  1576. li r4,CriticalInput@l
  1577. mtspr IVOR0,r4 /* 0: Critical input */
  1578. li r4,MachineCheck@l
  1579. mtspr IVOR1,r4 /* 1: Machine check */
  1580. li r4,DataStorage@l
  1581. mtspr IVOR2,r4 /* 2: Data storage */
  1582. li r4,InstStorage@l
  1583. mtspr IVOR3,r4 /* 3: Instruction storage */
  1584. li r4,ExtInterrupt@l
  1585. mtspr IVOR4,r4 /* 4: External interrupt */
  1586. li r4,Alignment@l
  1587. mtspr IVOR5,r4 /* 5: Alignment */
  1588. li r4,ProgramCheck@l
  1589. mtspr IVOR6,r4 /* 6: Program check */
  1590. li r4,FPUnavailable@l
  1591. mtspr IVOR7,r4 /* 7: floating point unavailable */
  1592. li r4,SystemCall@l
  1593. mtspr IVOR8,r4 /* 8: System call */
  1594. /* 9: Auxiliary processor unavailable(unsupported) */
  1595. li r4,Decrementer@l
  1596. mtspr IVOR10,r4 /* 10: Decrementer */
  1597. li r4,IntervalTimer@l
  1598. mtspr IVOR11,r4 /* 11: Interval timer */
  1599. li r4,WatchdogTimer@l
  1600. mtspr IVOR12,r4 /* 12: Watchdog timer */
  1601. li r4,DataTLBError@l
  1602. mtspr IVOR13,r4 /* 13: Data TLB error */
  1603. li r4,InstructionTLBError@l
  1604. mtspr IVOR14,r4 /* 14: Instruction TLB error */
  1605. li r4,DebugBreakpoint@l
  1606. mtspr IVOR15,r4 /* 15: Debug */
  1607. blr
  1608. .globl unlock_ram_in_cache
  1609. unlock_ram_in_cache:
  1610. /* invalidate the INIT_RAM section */
  1611. lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
  1612. ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
  1613. mfspr r4,L1CFG0
  1614. andi. r4,r4,0x1ff
  1615. slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
  1616. mtctr r4
  1617. 1: dcbi r0,r3
  1618. dcblc r0,r3
  1619. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  1620. bdnz 1b
  1621. sync
  1622. /* Invalidate the TLB entries for the cache */
  1623. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  1624. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  1625. tlbivax 0,r3
  1626. addi r3,r3,0x1000
  1627. tlbivax 0,r3
  1628. addi r3,r3,0x1000
  1629. tlbivax 0,r3
  1630. addi r3,r3,0x1000
  1631. tlbivax 0,r3
  1632. isync
  1633. blr
  1634. .globl flush_dcache
  1635. flush_dcache:
  1636. mfspr r3,SPRN_L1CFG0
  1637. rlwinm r5,r3,9,3 /* Extract cache block size */
  1638. twlgti r5,1 /* Only 32 and 64 byte cache blocks
  1639. * are currently defined.
  1640. */
  1641. li r4,32
  1642. subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
  1643. * log2(number of ways)
  1644. */
  1645. slw r5,r4,r5 /* r5 = cache block size */
  1646. rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
  1647. mulli r7,r7,13 /* An 8-way cache will require 13
  1648. * loads per set.
  1649. */
  1650. slw r7,r7,r6
  1651. /* save off HID0 and set DCFA */
  1652. mfspr r8,SPRN_HID0
  1653. ori r9,r8,HID0_DCFA@l
  1654. mtspr SPRN_HID0,r9
  1655. isync
  1656. lis r4,0
  1657. mtctr r7
  1658. 1: lwz r3,0(r4) /* Load... */
  1659. add r4,r4,r5
  1660. bdnz 1b
  1661. msync
  1662. lis r4,0
  1663. mtctr r7
  1664. 1: dcbf 0,r4 /* ...and flush. */
  1665. add r4,r4,r5
  1666. bdnz 1b
  1667. /* restore HID0 */
  1668. mtspr SPRN_HID0,r8
  1669. isync
  1670. blr
  1671. #endif /* !MINIMAL_SPL */