mpc83xx_cpu.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <bitfield.h>
  8. #include <clk.h>
  9. #include <cpu.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <vsprintf.h>
  13. #include <linux/bitops.h>
  14. #include "mpc83xx_cpu.h"
  15. /**
  16. * struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs
  17. * @e300_type: The e300 core type of the MPC83xx CPU
  18. * @family: The MPC83xx family the CPU belongs to
  19. * @type: The MPC83xx type of the CPU
  20. * @is_e_processor: Flag indicating whether the CPU is a E processor or not
  21. * @is_a_variant: Flag indicating whtther the CPU is a A variant or not
  22. * @revid: The revision ID of the CPU
  23. * @revid.major: The major part of the CPU's revision ID
  24. * @revid.minor: The minor part of the CPU's revision ID
  25. */
  26. struct mpc83xx_cpu_priv {
  27. enum e300_type e300_type;
  28. enum mpc83xx_cpu_family family;
  29. enum mpc83xx_cpu_type type;
  30. bool is_e_processor;
  31. bool is_a_variant;
  32. struct {
  33. uint major;
  34. uint minor;
  35. } revid;
  36. };
  37. int checkcpu(void)
  38. {
  39. /* Activate all CPUs from board_f.c */
  40. return cpu_probe_all();
  41. }
  42. /**
  43. * get_spridr() - Read SPRIDR (System Part and Revision ID Register) of CPU
  44. *
  45. * Return: The SPRIDR value
  46. */
  47. static inline u32 get_spridr(void)
  48. {
  49. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  50. return in_be32(&immr->sysconf.spridr);
  51. }
  52. /**
  53. * determine_type() - Determine CPU family of MPC83xx device
  54. * @dev: CPU device from which to read CPU family from
  55. */
  56. static inline void determine_family(const struct udevice *dev)
  57. {
  58. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  59. /* Upper 12 bits of PARTID field (bits 0-23 in SPRIDR) */
  60. const u32 PARTID_FAMILY_MASK = 0xFFF00000;
  61. switch (bitfield_extract_by_mask(get_spridr(), PARTID_FAMILY_MASK)) {
  62. case 0x810:
  63. case 0x811:
  64. priv->family = FAMILY_830X;
  65. break;
  66. case 0x80B:
  67. priv->family = FAMILY_831X;
  68. break;
  69. case 0x806:
  70. priv->family = FAMILY_832X;
  71. break;
  72. case 0x803:
  73. priv->family = FAMILY_834X;
  74. break;
  75. case 0x804:
  76. priv->family = FAMILY_836X;
  77. break;
  78. case 0x80C:
  79. priv->family = FAMILY_837X;
  80. break;
  81. default:
  82. priv->family = FAMILY_UNKNOWN;
  83. }
  84. }
  85. /**
  86. * determine_type() - Determine CPU type of MPC83xx device
  87. * @dev: CPU device from which to read CPU type from
  88. */
  89. static inline void determine_type(const struct udevice *dev)
  90. {
  91. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  92. /* Upper 16 bits of PVR (Processor Version Register) */
  93. const u32 PCR_UPPER_MASK = 0xFFFF0000;
  94. u32 val;
  95. val = bitfield_extract_by_mask(get_spridr(), PCR_UPPER_MASK);
  96. /* Mask out E-variant bit */
  97. switch (val & 0xFFFE) {
  98. case 0x8100:
  99. priv->type = TYPE_8308;
  100. break;
  101. case 0x8110:
  102. priv->type = TYPE_8309;
  103. break;
  104. case 0x80B2:
  105. priv->type = TYPE_8311;
  106. break;
  107. case 0x80B0:
  108. priv->type = TYPE_8313;
  109. break;
  110. case 0x80B6:
  111. priv->type = TYPE_8314;
  112. break;
  113. case 0x80B4:
  114. priv->type = TYPE_8315;
  115. break;
  116. case 0x8066:
  117. priv->type = TYPE_8321;
  118. break;
  119. case 0x8062:
  120. priv->type = TYPE_8323;
  121. break;
  122. case 0x8036:
  123. priv->type = TYPE_8343;
  124. break;
  125. case 0x8032:
  126. priv->type = TYPE_8347_TBGA;
  127. break;
  128. case 0x8034:
  129. priv->type = TYPE_8347_PBGA;
  130. break;
  131. case 0x8030:
  132. priv->type = TYPE_8349;
  133. break;
  134. case 0x804A:
  135. priv->type = TYPE_8358_TBGA;
  136. break;
  137. case 0x804E:
  138. priv->type = TYPE_8358_PBGA;
  139. break;
  140. case 0x8048:
  141. priv->type = TYPE_8360;
  142. break;
  143. case 0x80C6:
  144. priv->type = TYPE_8377;
  145. break;
  146. case 0x80C4:
  147. priv->type = TYPE_8378;
  148. break;
  149. case 0x80C2:
  150. priv->type = TYPE_8379;
  151. break;
  152. default:
  153. priv->type = TYPE_UNKNOWN;
  154. }
  155. }
  156. /**
  157. * determine_e300_type() - Determine e300 core type of MPC83xx device
  158. * @dev: CPU device from which to read e300 core type from
  159. */
  160. static inline void determine_e300_type(const struct udevice *dev)
  161. {
  162. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  163. /* Upper 16 bits of PVR (Processor Version Register) */
  164. const u32 PCR_UPPER_MASK = 0xFFFF0000;
  165. u32 pvr = get_pvr();
  166. switch ((pvr & PCR_UPPER_MASK) >> 16) {
  167. case 0x8083:
  168. priv->e300_type = E300C1;
  169. break;
  170. case 0x8084:
  171. priv->e300_type = E300C2;
  172. break;
  173. case 0x8085:
  174. priv->e300_type = E300C3;
  175. break;
  176. case 0x8086:
  177. priv->e300_type = E300C4;
  178. break;
  179. default:
  180. priv->e300_type = E300_UNKNOWN;
  181. }
  182. }
  183. /**
  184. * determine_revid() - Determine revision ID of CPU device
  185. * @dev: CPU device from which to read revision ID
  186. */
  187. static inline void determine_revid(const struct udevice *dev)
  188. {
  189. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  190. u32 REVID_MAJOR_MASK;
  191. u32 REVID_MINOR_MASK;
  192. u32 spridr = get_spridr();
  193. if (priv->family == FAMILY_834X) {
  194. REVID_MAJOR_MASK = 0x0000FF00;
  195. REVID_MINOR_MASK = 0x000000FF;
  196. } else {
  197. REVID_MAJOR_MASK = 0x000000F0;
  198. REVID_MINOR_MASK = 0x0000000F;
  199. }
  200. priv->revid.major = bitfield_extract_by_mask(spridr, REVID_MAJOR_MASK);
  201. priv->revid.minor = bitfield_extract_by_mask(spridr, REVID_MINOR_MASK);
  202. }
  203. /**
  204. * determine_cpu_data() - Determine CPU information from hardware
  205. * @dev: CPU device from which to read information
  206. */
  207. static void determine_cpu_data(const struct udevice *dev)
  208. {
  209. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  210. const u32 E_FLAG_MASK = 0x00010000;
  211. u32 spridr = get_spridr();
  212. determine_family(dev);
  213. determine_type(dev);
  214. determine_e300_type(dev);
  215. determine_revid(dev);
  216. if ((priv->family == FAMILY_834X ||
  217. priv->family == FAMILY_836X) && priv->revid.major >= 2)
  218. priv->is_a_variant = true;
  219. priv->is_e_processor = !bitfield_extract_by_mask(spridr, E_FLAG_MASK);
  220. }
  221. static int mpc83xx_cpu_get_desc(const struct udevice *dev, char *buf, int size)
  222. {
  223. struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
  224. struct clk core_clk;
  225. struct clk csb_clk;
  226. char core_freq[32];
  227. char csb_freq[32];
  228. int ret;
  229. ret = clk_get_by_index((struct udevice *)dev, 0, &core_clk);
  230. if (ret) {
  231. debug("%s: Failed to get core clock (err = %d)\n",
  232. dev->name, ret);
  233. return ret;
  234. }
  235. ret = clk_get_by_index((struct udevice *)dev, 1, &csb_clk);
  236. if (ret) {
  237. debug("%s: Failed to get CSB clock (err = %d)\n",
  238. dev->name, ret);
  239. return ret;
  240. }
  241. determine_cpu_data(dev);
  242. snprintf(buf, size,
  243. "%s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz",
  244. e300_names[priv->e300_type],
  245. cpu_type_names[priv->type],
  246. priv->is_e_processor ? "E" : "",
  247. priv->is_a_variant ? "A" : "",
  248. priv->revid.major,
  249. priv->revid.minor,
  250. strmhz(core_freq, clk_get_rate(&core_clk)),
  251. strmhz(csb_freq, clk_get_rate(&csb_clk)));
  252. return 0;
  253. }
  254. static int mpc83xx_cpu_get_info(const struct udevice *dev,
  255. struct cpu_info *info)
  256. {
  257. struct clk clock;
  258. int ret;
  259. ulong freq;
  260. ret = clk_get_by_index((struct udevice *)dev, 0, &clock);
  261. if (ret) {
  262. debug("%s: Failed to get core clock (err = %d)\n",
  263. dev->name, ret);
  264. return ret;
  265. }
  266. freq = clk_get_rate(&clock);
  267. if (!freq) {
  268. debug("%s: Core clock speed is zero\n", dev->name);
  269. return -EINVAL;
  270. }
  271. info->cpu_freq = freq;
  272. info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
  273. return 0;
  274. }
  275. static int mpc83xx_cpu_get_count(const struct udevice *dev)
  276. {
  277. /* We have one e300cX core */
  278. return 1;
  279. }
  280. static int mpc83xx_cpu_get_vendor(const struct udevice *dev, char *buf,
  281. int size)
  282. {
  283. snprintf(buf, size, "NXP");
  284. return 0;
  285. }
  286. static const struct cpu_ops mpc83xx_cpu_ops = {
  287. .get_desc = mpc83xx_cpu_get_desc,
  288. .get_info = mpc83xx_cpu_get_info,
  289. .get_count = mpc83xx_cpu_get_count,
  290. .get_vendor = mpc83xx_cpu_get_vendor,
  291. };
  292. static int mpc83xx_cpu_probe(struct udevice *dev)
  293. {
  294. return 0;
  295. }
  296. static const struct udevice_id mpc83xx_cpu_ids[] = {
  297. { .compatible = "fsl,mpc83xx", },
  298. { .compatible = "fsl,mpc8308", },
  299. { .compatible = "fsl,mpc8309", },
  300. { .compatible = "fsl,mpc8313", },
  301. { .compatible = "fsl,mpc8315", },
  302. { .compatible = "fsl,mpc832x", },
  303. { .compatible = "fsl,mpc8349", },
  304. { .compatible = "fsl,mpc8360", },
  305. { .compatible = "fsl,mpc8379", },
  306. { /* sentinel */ }
  307. };
  308. U_BOOT_DRIVER(mpc83xx_cpu) = {
  309. .name = "mpc83xx_cpu",
  310. .id = UCLASS_CPU,
  311. .of_match = mpc83xx_cpu_ids,
  312. .probe = mpc83xx_cpu_probe,
  313. .priv_auto_alloc_size = sizeof(struct mpc83xx_cpu_priv),
  314. .ops = &mpc83xx_cpu_ops,
  315. .flags = DM_FLAG_PRE_RELOC,
  316. };