cpu_full.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. *
  5. * Based on code from coreboot src/soc/intel/broadwell/cpu.c
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <cpu.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/cpu.h>
  13. #include <asm/cpu_x86.h>
  14. #include <asm/cpu_common.h>
  15. #include <asm/intel_regs.h>
  16. #include <asm/msr.h>
  17. #include <asm/post.h>
  18. #include <asm/turbo.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/pch.h>
  21. #include <asm/arch/rcb.h>
  22. #include <linux/delay.h>
  23. struct cpu_broadwell_priv {
  24. bool ht_disabled;
  25. };
  26. /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
  27. static const u8 power_limit_time_sec_to_msr[] = {
  28. [0] = 0x00,
  29. [1] = 0x0a,
  30. [2] = 0x0b,
  31. [3] = 0x4b,
  32. [4] = 0x0c,
  33. [5] = 0x2c,
  34. [6] = 0x4c,
  35. [7] = 0x6c,
  36. [8] = 0x0d,
  37. [10] = 0x2d,
  38. [12] = 0x4d,
  39. [14] = 0x6d,
  40. [16] = 0x0e,
  41. [20] = 0x2e,
  42. [24] = 0x4e,
  43. [28] = 0x6e,
  44. [32] = 0x0f,
  45. [40] = 0x2f,
  46. [48] = 0x4f,
  47. [56] = 0x6f,
  48. [64] = 0x10,
  49. [80] = 0x30,
  50. [96] = 0x50,
  51. [112] = 0x70,
  52. [128] = 0x11,
  53. };
  54. /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
  55. static const u8 power_limit_time_msr_to_sec[] = {
  56. [0x00] = 0,
  57. [0x0a] = 1,
  58. [0x0b] = 2,
  59. [0x4b] = 3,
  60. [0x0c] = 4,
  61. [0x2c] = 5,
  62. [0x4c] = 6,
  63. [0x6c] = 7,
  64. [0x0d] = 8,
  65. [0x2d] = 10,
  66. [0x4d] = 12,
  67. [0x6d] = 14,
  68. [0x0e] = 16,
  69. [0x2e] = 20,
  70. [0x4e] = 24,
  71. [0x6e] = 28,
  72. [0x0f] = 32,
  73. [0x2f] = 40,
  74. [0x4f] = 48,
  75. [0x6f] = 56,
  76. [0x10] = 64,
  77. [0x30] = 80,
  78. [0x50] = 96,
  79. [0x70] = 112,
  80. [0x11] = 128,
  81. };
  82. #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
  83. int arch_cpu_init(void)
  84. {
  85. return 0;
  86. }
  87. #endif
  88. /*
  89. * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
  90. * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
  91. * when a core is woken up
  92. */
  93. static int pcode_ready(void)
  94. {
  95. int wait_count;
  96. const int delay_step = 10;
  97. wait_count = 0;
  98. do {
  99. if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
  100. MAILBOX_RUN_BUSY))
  101. return 0;
  102. wait_count += delay_step;
  103. udelay(delay_step);
  104. } while (wait_count < 1000);
  105. return -ETIMEDOUT;
  106. }
  107. static u32 pcode_mailbox_read(u32 command)
  108. {
  109. int ret;
  110. ret = pcode_ready();
  111. if (ret) {
  112. debug("PCODE: mailbox timeout on wait ready\n");
  113. return ret;
  114. }
  115. /* Send command and start transaction */
  116. writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
  117. ret = pcode_ready();
  118. if (ret) {
  119. debug("PCODE: mailbox timeout on completion\n");
  120. return ret;
  121. }
  122. /* Read mailbox */
  123. return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
  124. }
  125. static int pcode_mailbox_write(u32 command, u32 data)
  126. {
  127. int ret;
  128. ret = pcode_ready();
  129. if (ret) {
  130. debug("PCODE: mailbox timeout on wait ready\n");
  131. return ret;
  132. }
  133. writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
  134. /* Send command and start transaction */
  135. writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
  136. ret = pcode_ready();
  137. if (ret) {
  138. debug("PCODE: mailbox timeout on completion\n");
  139. return ret;
  140. }
  141. return 0;
  142. }
  143. /* @dev is the CPU device */
  144. static void initialize_vr_config(struct udevice *dev)
  145. {
  146. int ramp, min_vid;
  147. msr_t msr;
  148. debug("Initializing VR config\n");
  149. /* Configure VR_CURRENT_CONFIG */
  150. msr = msr_read(MSR_VR_CURRENT_CONFIG);
  151. /*
  152. * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
  153. * on ULT systems
  154. */
  155. msr.hi &= 0xc0000000;
  156. msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
  157. msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
  158. msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
  159. msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
  160. /* Leave the max instantaneous current limit (12:0) to default */
  161. msr_write(MSR_VR_CURRENT_CONFIG, msr);
  162. /* Configure VR_MISC_CONFIG MSR */
  163. msr = msr_read(MSR_VR_MISC_CONFIG);
  164. /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
  165. msr.hi &= ~(0x3ff << (40 - 32));
  166. msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
  167. /* Set IOUT_OFFSET to 0 */
  168. msr.hi &= ~0xff;
  169. /* Set entry ramp rate to slow */
  170. msr.hi &= ~(1 << (51 - 32));
  171. /* Enable decay mode on C-state entry */
  172. msr.hi |= (1 << (52 - 32));
  173. /* Set the slow ramp rate */
  174. msr.hi &= ~(0x3 << (53 - 32));
  175. /* Configure the C-state exit ramp rate */
  176. ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  177. "intel,slow-ramp", -1);
  178. if (ramp != -1) {
  179. /* Configured slow ramp rate */
  180. msr.hi |= ((ramp & 0x3) << (53 - 32));
  181. /* Set exit ramp rate to slow */
  182. msr.hi &= ~(1 << (50 - 32));
  183. } else {
  184. /* Fast ramp rate / 4 */
  185. msr.hi |= (0x01 << (53 - 32));
  186. /* Set exit ramp rate to fast */
  187. msr.hi |= (1 << (50 - 32));
  188. }
  189. /* Set MIN_VID (31:24) to allow CPU to have full control */
  190. msr.lo &= ~0xff000000;
  191. min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  192. "intel,min-vid", 0);
  193. msr.lo |= (min_vid & 0xff) << 24;
  194. msr_write(MSR_VR_MISC_CONFIG, msr);
  195. /* Configure VR_MISC_CONFIG2 MSR */
  196. msr = msr_read(MSR_VR_MISC_CONFIG2);
  197. msr.lo &= ~0xffff;
  198. /*
  199. * Allow CPU to control minimum voltage completely (15:8) and
  200. * set the fast ramp voltage in 10mV steps
  201. */
  202. if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
  203. msr.lo |= 0x006a; /* 1.56V */
  204. else
  205. msr.lo |= 0x006f; /* 1.60V */
  206. msr_write(MSR_VR_MISC_CONFIG2, msr);
  207. /* Set C9/C10 VCC Min */
  208. pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
  209. }
  210. static int calibrate_24mhz_bclk(void)
  211. {
  212. int err_code;
  213. int ret;
  214. ret = pcode_ready();
  215. if (ret)
  216. return ret;
  217. /* A non-zero value initiates the PCODE calibration */
  218. writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
  219. writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
  220. MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
  221. ret = pcode_ready();
  222. if (ret)
  223. return ret;
  224. err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
  225. debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
  226. /* Read the calibrated value */
  227. writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
  228. MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
  229. ret = pcode_ready();
  230. if (ret)
  231. return ret;
  232. debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
  233. readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
  234. return 0;
  235. }
  236. static void configure_pch_power_sharing(void)
  237. {
  238. u32 pch_power, pch_power_ext, pmsync, pmsync2;
  239. int i;
  240. /* Read PCH Power levels from PCODE */
  241. pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
  242. pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
  243. debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
  244. pch_power_ext);
  245. pmsync = readl(RCB_REG(PMSYNC_CONFIG));
  246. pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
  247. /*
  248. * Program PMSYNC_TPR_CONFIG PCH power limit values
  249. * pmsync[0:4] = mailbox[0:5]
  250. * pmsync[8:12] = mailbox[6:11]
  251. * pmsync[16:20] = mailbox[12:17]
  252. */
  253. for (i = 0; i < 3; i++) {
  254. u32 level = pch_power & 0x3f;
  255. pch_power >>= 6;
  256. pmsync &= ~(0x1f << (i * 8));
  257. pmsync |= (level & 0x1f) << (i * 8);
  258. }
  259. writel(pmsync, RCB_REG(PMSYNC_CONFIG));
  260. /*
  261. * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
  262. * pmsync2[0:4] = mailbox[23:18]
  263. * pmsync2[8:12] = mailbox_ext[6:11]
  264. * pmsync2[16:20] = mailbox_ext[12:17]
  265. * pmsync2[24:28] = mailbox_ext[18:22]
  266. */
  267. pmsync2 &= ~0x1f;
  268. pmsync2 |= pch_power & 0x1f;
  269. for (i = 1; i < 4; i++) {
  270. u32 level = pch_power_ext & 0x3f;
  271. pch_power_ext >>= 6;
  272. pmsync2 &= ~(0x1f << (i * 8));
  273. pmsync2 |= (level & 0x1f) << (i * 8);
  274. }
  275. writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
  276. }
  277. static int bsp_init_before_ap_bringup(struct udevice *dev)
  278. {
  279. int ret;
  280. initialize_vr_config(dev);
  281. ret = calibrate_24mhz_bclk();
  282. if (ret)
  283. return ret;
  284. configure_pch_power_sharing();
  285. return 0;
  286. }
  287. static void set_max_ratio(void)
  288. {
  289. msr_t msr, perf_ctl;
  290. perf_ctl.hi = 0;
  291. /* Check for configurable TDP option */
  292. if (turbo_get_state() == TURBO_ENABLED) {
  293. msr = msr_read(MSR_TURBO_RATIO_LIMIT);
  294. perf_ctl.lo = (msr.lo & 0xff) << 8;
  295. } else if (cpu_config_tdp_levels()) {
  296. /* Set to nominal TDP ratio */
  297. msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
  298. perf_ctl.lo = (msr.lo & 0xff) << 8;
  299. } else {
  300. /* Platform Info bits 15:8 give max ratio */
  301. msr = msr_read(MSR_PLATFORM_INFO);
  302. perf_ctl.lo = msr.lo & 0xff00;
  303. }
  304. msr_write(MSR_IA32_PERF_CTL, perf_ctl);
  305. debug("cpu: frequency set to %d\n",
  306. ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
  307. }
  308. int broadwell_init(struct udevice *dev)
  309. {
  310. struct cpu_broadwell_priv *priv = dev_get_priv(dev);
  311. int num_threads;
  312. int num_cores;
  313. msr_t msr;
  314. int ret;
  315. msr = msr_read(CORE_THREAD_COUNT_MSR);
  316. num_threads = (msr.lo >> 0) & 0xffff;
  317. num_cores = (msr.lo >> 16) & 0xffff;
  318. debug("CPU has %u cores, %u threads enabled\n", num_cores,
  319. num_threads);
  320. priv->ht_disabled = num_threads == num_cores;
  321. ret = bsp_init_before_ap_bringup(dev);
  322. if (ret)
  323. return ret;
  324. set_max_ratio();
  325. return ret;
  326. }
  327. static void configure_mca(void)
  328. {
  329. msr_t msr;
  330. const unsigned int mcg_cap_msr = 0x179;
  331. int i;
  332. int num_banks;
  333. msr = msr_read(mcg_cap_msr);
  334. num_banks = msr.lo & 0xff;
  335. msr.lo = 0;
  336. msr.hi = 0;
  337. /*
  338. * TODO(adurbin): This should only be done on a cold boot. Also, some
  339. * of these banks are core vs package scope. For now every CPU clears
  340. * every bank
  341. */
  342. for (i = 0; i < num_banks; i++)
  343. msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
  344. }
  345. static void enable_lapic_tpr(void)
  346. {
  347. msr_t msr;
  348. msr = msr_read(MSR_PIC_MSG_CONTROL);
  349. msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
  350. msr_write(MSR_PIC_MSG_CONTROL, msr);
  351. }
  352. static void configure_c_states(void)
  353. {
  354. msr_t msr;
  355. msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
  356. msr.lo |= (1 << 31); /* Timed MWAIT Enable */
  357. msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
  358. msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
  359. msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
  360. msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
  361. msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
  362. msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
  363. msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
  364. /* The deepest package c-state defaults to factory-configured value */
  365. msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
  366. msr = msr_read(MSR_MISC_PWR_MGMT);
  367. msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
  368. msr_write(MSR_MISC_PWR_MGMT, msr);
  369. msr = msr_read(MSR_POWER_CTL);
  370. msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
  371. msr.lo |= (1 << 1); /* C1E Enable */
  372. msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
  373. msr_write(MSR_POWER_CTL, msr);
  374. /* C-state Interrupt Response Latency Control 0 - package C3 latency */
  375. msr.hi = 0;
  376. msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
  377. msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
  378. /* C-state Interrupt Response Latency Control 1 */
  379. msr.hi = 0;
  380. msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
  381. msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
  382. /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
  383. msr.hi = 0;
  384. msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
  385. msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
  386. /* C-state Interrupt Response Latency Control 3 - package C8 */
  387. msr.hi = 0;
  388. msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
  389. msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
  390. /* C-state Interrupt Response Latency Control 4 - package C9 */
  391. msr.hi = 0;
  392. msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
  393. msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
  394. /* C-state Interrupt Response Latency Control 5 - package C10 */
  395. msr.hi = 0;
  396. msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
  397. msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
  398. }
  399. static void configure_misc(void)
  400. {
  401. msr_t msr;
  402. msr = msr_read(MSR_IA32_MISC_ENABLE);
  403. msr.lo |= MISC_ENABLE_FAST_STRING;
  404. msr.lo |= MISC_ENABLE_TM1;
  405. msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
  406. msr_write(MSR_IA32_MISC_ENABLE, msr);
  407. /* Disable thermal interrupts */
  408. msr.lo = 0;
  409. msr.hi = 0;
  410. msr_write(MSR_IA32_THERM_INTERRUPT, msr);
  411. /* Enable package critical interrupt only */
  412. msr.lo = 1 << 4;
  413. msr.hi = 0;
  414. msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
  415. }
  416. static void configure_dca_cap(void)
  417. {
  418. struct cpuid_result cpuid_regs;
  419. msr_t msr;
  420. /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
  421. cpuid_regs = cpuid(1);
  422. if (cpuid_regs.ecx & (1 << 18)) {
  423. msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
  424. msr.lo |= 1;
  425. msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
  426. }
  427. }
  428. static void set_energy_perf_bias(u8 policy)
  429. {
  430. msr_t msr;
  431. int ecx;
  432. /* Determine if energy efficient policy is supported */
  433. ecx = cpuid_ecx(0x6);
  434. if (!(ecx & (1 << 3)))
  435. return;
  436. /* Energy Policy is bits 3:0 */
  437. msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
  438. msr.lo &= ~0xf;
  439. msr.lo |= policy & 0xf;
  440. msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
  441. debug("cpu: energy policy set to %u\n", policy);
  442. }
  443. /* All CPUs including BSP will run the following function */
  444. static void cpu_core_init(struct udevice *dev)
  445. {
  446. /* Clear out pending MCEs */
  447. configure_mca();
  448. /* Enable the local cpu apics */
  449. enable_lapic_tpr();
  450. /* Configure C States */
  451. configure_c_states();
  452. /* Configure Enhanced SpeedStep and Thermal Sensors */
  453. configure_misc();
  454. /* Thermal throttle activation offset */
  455. cpu_configure_thermal_target(dev);
  456. /* Enable Direct Cache Access */
  457. configure_dca_cap();
  458. /* Set energy policy */
  459. set_energy_perf_bias(ENERGY_POLICY_NORMAL);
  460. /* Enable Turbo */
  461. turbo_enable();
  462. }
  463. /*
  464. * Configure processor power limits if possible
  465. * This must be done AFTER set of BIOS_RESET_CPL
  466. */
  467. void cpu_set_power_limits(int power_limit_1_time)
  468. {
  469. msr_t msr;
  470. msr_t limit;
  471. uint power_unit;
  472. uint tdp, min_power, max_power, max_time;
  473. u8 power_limit_1_val;
  474. msr = msr_read(MSR_PLATFORM_INFO);
  475. if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
  476. power_limit_1_time = 28;
  477. if (!(msr.lo & PLATFORM_INFO_SET_TDP))
  478. return;
  479. /* Get units */
  480. msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
  481. power_unit = 2 << ((msr.lo & 0xf) - 1);
  482. /* Get power defaults for this SKU */
  483. msr = msr_read(MSR_PKG_POWER_SKU);
  484. tdp = msr.lo & 0x7fff;
  485. min_power = (msr.lo >> 16) & 0x7fff;
  486. max_power = msr.hi & 0x7fff;
  487. max_time = (msr.hi >> 16) & 0x7f;
  488. debug("CPU TDP: %u Watts\n", tdp / power_unit);
  489. if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
  490. power_limit_1_time = power_limit_time_msr_to_sec[max_time];
  491. if (min_power > 0 && tdp < min_power)
  492. tdp = min_power;
  493. if (max_power > 0 && tdp > max_power)
  494. tdp = max_power;
  495. power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
  496. /* Set long term power limit to TDP */
  497. limit.lo = 0;
  498. limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
  499. limit.lo |= PKG_POWER_LIMIT_EN;
  500. limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
  501. PKG_POWER_LIMIT_TIME_SHIFT;
  502. /* Set short term power limit to 1.25 * TDP */
  503. limit.hi = 0;
  504. limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
  505. limit.hi |= PKG_POWER_LIMIT_EN;
  506. /* Power limit 2 time is only programmable on server SKU */
  507. msr_write(MSR_PKG_POWER_LIMIT, limit);
  508. /* Set power limit values in MCHBAR as well */
  509. writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
  510. writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
  511. /* Set DDR RAPL power limit by copying from MMIO to MSR */
  512. msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
  513. msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
  514. msr_write(MSR_DDR_RAPL_LIMIT, msr);
  515. /* Use nominal TDP values for CPUs with configurable TDP */
  516. if (cpu_config_tdp_levels()) {
  517. msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
  518. limit.hi = 0;
  519. limit.lo = msr.lo & 0xff;
  520. msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
  521. }
  522. }
  523. static int broadwell_get_info(const struct udevice *dev, struct cpu_info *info)
  524. {
  525. return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
  526. }
  527. static int broadwell_get_count(const struct udevice *dev)
  528. {
  529. return 4;
  530. }
  531. static int cpu_x86_broadwell_probe(struct udevice *dev)
  532. {
  533. if (dev->seq == 0) {
  534. cpu_core_init(dev);
  535. return broadwell_init(dev);
  536. }
  537. return 0;
  538. }
  539. static const struct cpu_ops cpu_x86_broadwell_ops = {
  540. .get_desc = cpu_x86_get_desc,
  541. .get_info = broadwell_get_info,
  542. .get_count = broadwell_get_count,
  543. .get_vendor = cpu_x86_get_vendor,
  544. };
  545. static const struct udevice_id cpu_x86_broadwell_ids[] = {
  546. { .compatible = "intel,core-i3-gen5" },
  547. { }
  548. };
  549. U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
  550. .name = "cpu_x86_broadwell",
  551. .id = UCLASS_CPU,
  552. .of_match = cpu_x86_broadwell_ids,
  553. .bind = cpu_x86_bind,
  554. .probe = cpu_x86_broadwell_probe,
  555. .ops = &cpu_x86_broadwell_ops,
  556. .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
  557. .flags = DM_FLAG_PRE_RELOC,
  558. };