sti-reset.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <wait_bit.h>
  9. #include <dm.h>
  10. #include <reset-uclass.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <dt-bindings/reset/stih407-resets.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. struct sti_reset {
  16. const struct syscfg_reset_controller_data *data;
  17. };
  18. /**
  19. * Reset channel description for a system configuration register based
  20. * reset controller.
  21. *
  22. * @compatible: Compatible string of the syscon containing this
  23. * channel's control and ack (status) bits.
  24. * @reset_offset: Reset register offset in sysconf bank.
  25. * @reset_bit: Bit number in reset register.
  26. * @ack_offset: Ack reset register offset in syscon bank.
  27. * @ack_bit: Bit number in Ack reset register.
  28. * @deassert_cnt: incremented when reset is deasserted, reset can only be
  29. * asserted when equal to 0
  30. */
  31. struct syscfg_reset_channel_data {
  32. const char *compatible;
  33. int reset_offset;
  34. int reset_bit;
  35. int ack_offset;
  36. int ack_bit;
  37. int deassert_cnt;
  38. };
  39. /**
  40. * Description of a system configuration register based reset controller.
  41. *
  42. * @wait_for_ack: The controller will wait for reset assert and de-assert to
  43. * be "ack'd" in a channel's ack field.
  44. * @active_low: Are the resets in this controller active low, i.e. clearing
  45. * the reset bit puts the hardware into reset.
  46. * @nr_channels: The number of reset channels in this controller.
  47. * @channels: An array of reset channel descriptions.
  48. */
  49. struct syscfg_reset_controller_data {
  50. bool wait_for_ack;
  51. bool active_low;
  52. int nr_channels;
  53. struct syscfg_reset_channel_data *channels;
  54. };
  55. /* STiH407 Peripheral powerdown definitions. */
  56. static const char stih407_core[] = "st,stih407-core-syscfg";
  57. static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
  58. static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
  59. #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
  60. { .compatible = _c, \
  61. .reset_offset = _rr, \
  62. .reset_bit = _rb, \
  63. .ack_offset = _ar, \
  64. .ack_bit = _ab, }
  65. #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
  66. { .compatible = _c, \
  67. .reset_offset = _rr, \
  68. .reset_bit = _rb, }
  69. #define STIH407_SRST_CORE(_reg, _bit) \
  70. _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
  71. #define STIH407_SRST_SBC(_reg, _bit) \
  72. _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
  73. #define STIH407_SRST_LPM(_reg, _bit) \
  74. _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
  75. #define STIH407_PDN_0(_bit) \
  76. _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
  77. #define STIH407_PDN_1(_bit) \
  78. _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
  79. #define STIH407_PDN_ETH(_bit, _stat) \
  80. _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
  81. /* Powerdown requests control 0 */
  82. #define SYSCFG_5000 0x0
  83. #define SYSSTAT_5500 0x7d0
  84. /* Powerdown requests control 1 (High Speed Links) */
  85. #define SYSCFG_5001 0x4
  86. #define SYSSTAT_5501 0x7d4
  87. /* Ethernet powerdown/status/reset */
  88. #define SYSCFG_4032 0x80
  89. #define SYSSTAT_4520 0x820
  90. #define SYSCFG_4002 0x8
  91. static struct syscfg_reset_channel_data stih407_powerdowns[] = {
  92. [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
  93. [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
  94. [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
  95. [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
  96. [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
  97. [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
  98. [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
  99. [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
  100. [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
  101. [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
  102. };
  103. /* Reset Generator control 0/1 */
  104. #define SYSCFG_5128 0x200
  105. #define SYSCFG_5131 0x20c
  106. #define SYSCFG_5132 0x210
  107. #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
  108. static struct syscfg_reset_channel_data stih407_softresets[] = {
  109. [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
  110. [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
  111. [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
  112. [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
  113. [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
  114. [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
  115. [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
  116. [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
  117. [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
  118. [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
  119. [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
  120. [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
  121. [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
  122. [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
  123. [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
  124. [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
  125. [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
  126. [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
  127. [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
  128. [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
  129. [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
  130. [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
  131. [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
  132. [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
  133. [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
  134. [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
  135. [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
  136. [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
  137. [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
  138. [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
  139. [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
  140. [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
  141. [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
  142. };
  143. /* PicoPHY reset/control */
  144. #define SYSCFG_5061 0x0f4
  145. static struct syscfg_reset_channel_data stih407_picophyresets[] = {
  146. [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
  147. [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
  148. [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
  149. };
  150. static const struct
  151. syscfg_reset_controller_data stih407_powerdown_controller = {
  152. .wait_for_ack = true,
  153. .nr_channels = ARRAY_SIZE(stih407_powerdowns),
  154. .channels = stih407_powerdowns,
  155. };
  156. static const struct
  157. syscfg_reset_controller_data stih407_softreset_controller = {
  158. .wait_for_ack = false,
  159. .active_low = true,
  160. .nr_channels = ARRAY_SIZE(stih407_softresets),
  161. .channels = stih407_softresets,
  162. };
  163. static const struct
  164. syscfg_reset_controller_data stih407_picophyreset_controller = {
  165. .wait_for_ack = false,
  166. .nr_channels = ARRAY_SIZE(stih407_picophyresets),
  167. .channels = stih407_picophyresets,
  168. };
  169. phys_addr_t sti_reset_get_regmap(const char *compatible)
  170. {
  171. struct udevice *syscon;
  172. struct regmap *regmap;
  173. int node, ret;
  174. node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
  175. compatible);
  176. if (node < 0) {
  177. pr_err("unable to find %s node\n", compatible);
  178. return node;
  179. }
  180. ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
  181. if (ret) {
  182. pr_err("%s: uclass_get_device_by_of_offset failed: %d\n",
  183. __func__, ret);
  184. return ret;
  185. }
  186. regmap = syscon_get_regmap(syscon);
  187. if (!regmap) {
  188. pr_err("unable to get regmap for %s\n", syscon->name);
  189. return -ENODEV;
  190. }
  191. return regmap->ranges[0].start;
  192. }
  193. static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
  194. {
  195. struct udevice *dev = reset_ctl->dev;
  196. struct syscfg_reset_controller_data *reset_desc =
  197. (struct syscfg_reset_controller_data *)(dev->driver_data);
  198. struct syscfg_reset_channel_data *ch;
  199. phys_addr_t base;
  200. u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
  201. void __iomem *reg;
  202. /* check if reset id is inside available range */
  203. if (reset_ctl->id >= reset_desc->nr_channels)
  204. return -EINVAL;
  205. /* get reset sysconf register base address */
  206. base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
  207. ch = &reset_desc->channels[reset_ctl->id];
  208. /* check the deassert counter to assert reset when it reaches 0 */
  209. if (!assert) {
  210. ch->deassert_cnt++;
  211. if (ch->deassert_cnt > 1)
  212. return 0;
  213. } else {
  214. if (ch->deassert_cnt > 0) {
  215. ch->deassert_cnt--;
  216. if (ch->deassert_cnt > 0)
  217. return 0;
  218. } else
  219. pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n",
  220. reset_ctl, reset_ctl->dev, reset_ctl->id);
  221. }
  222. reg = (void __iomem *)base + ch->reset_offset;
  223. if (ctrl_val)
  224. generic_set_bit(ch->reset_bit, reg);
  225. else
  226. generic_clear_bit(ch->reset_bit, reg);
  227. if (!reset_desc->wait_for_ack)
  228. return 0;
  229. reg = (void __iomem *)base + ch->ack_offset;
  230. if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
  231. 1000, false)) {
  232. pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
  233. reset_ctl, reset_ctl->dev, reset_ctl->id);
  234. return -ETIMEDOUT;
  235. }
  236. return 0;
  237. }
  238. static int sti_reset_request(struct reset_ctl *reset_ctl)
  239. {
  240. return 0;
  241. }
  242. static int sti_reset_free(struct reset_ctl *reset_ctl)
  243. {
  244. return 0;
  245. }
  246. static int sti_reset_assert(struct reset_ctl *reset_ctl)
  247. {
  248. return sti_reset_program_hw(reset_ctl, true);
  249. }
  250. static int sti_reset_deassert(struct reset_ctl *reset_ctl)
  251. {
  252. return sti_reset_program_hw(reset_ctl, false);
  253. }
  254. struct reset_ops sti_reset_ops = {
  255. .request = sti_reset_request,
  256. .rfree = sti_reset_free,
  257. .rst_assert = sti_reset_assert,
  258. .rst_deassert = sti_reset_deassert,
  259. };
  260. static int sti_reset_probe(struct udevice *dev)
  261. {
  262. struct sti_reset *priv = dev_get_priv(dev);
  263. priv->data = (void *)dev_get_driver_data(dev);
  264. return 0;
  265. }
  266. static const struct udevice_id sti_reset_ids[] = {
  267. {
  268. .compatible = "st,stih407-picophyreset",
  269. .data = (ulong)&stih407_picophyreset_controller,
  270. },
  271. {
  272. .compatible = "st,stih407-powerdown",
  273. .data = (ulong)&stih407_powerdown_controller,
  274. },
  275. {
  276. .compatible = "st,stih407-softreset",
  277. .data = (ulong)&stih407_softreset_controller,
  278. },
  279. { }
  280. };
  281. U_BOOT_DRIVER(sti_reset) = {
  282. .name = "sti_reset",
  283. .id = UCLASS_RESET,
  284. .of_match = sti_reset_ids,
  285. .probe = sti_reset_probe,
  286. .priv_auto_alloc_size = sizeof(struct sti_reset),
  287. .ops = &sti_reset_ops,
  288. };