reset-imx7.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017, Impinj, Inc.
  4. */
  5. #include <asm/io.h>
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dt-bindings/reset/imx7-reset.h>
  9. #include <dt-bindings/reset/imx8mq-reset.h>
  10. #include <reset-uclass.h>
  11. struct imx7_reset_priv {
  12. void __iomem *base;
  13. struct reset_ops ops;
  14. };
  15. struct imx7_src_signal {
  16. unsigned int offset, bit;
  17. };
  18. enum imx7_src_registers {
  19. SRC_A7RCR0 = 0x0004,
  20. SRC_M4RCR = 0x000c,
  21. SRC_ERCR = 0x0014,
  22. SRC_HSICPHY_RCR = 0x001c,
  23. SRC_USBOPHY1_RCR = 0x0020,
  24. SRC_USBOPHY2_RCR = 0x0024,
  25. SRC_MIPIPHY_RCR = 0x0028,
  26. SRC_PCIEPHY_RCR = 0x002c,
  27. SRC_DDRC_RCR = 0x1000,
  28. };
  29. static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
  30. [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
  31. [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
  32. [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
  33. [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
  34. [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
  35. [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
  36. [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
  37. [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
  38. [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
  39. [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
  40. [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
  41. [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
  42. [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
  43. [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
  44. [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
  45. [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
  46. [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
  47. [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
  48. [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
  49. [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
  50. [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
  51. [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  52. [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  53. [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  54. [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
  55. [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
  56. };
  57. static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
  58. {
  59. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  60. const struct imx7_src_signal *sig = imx7_src_signals;
  61. u32 val;
  62. if (rst->id >= IMX7_RESET_NUM)
  63. return -EINVAL;
  64. if (rst->id == IMX7_RESET_PCIEPHY) {
  65. /*
  66. * wait for more than 10us to release phy g_rst and
  67. * btnrst
  68. */
  69. udelay(10);
  70. }
  71. val = readl(priv->base + sig[rst->id].offset);
  72. switch (rst->id) {
  73. case IMX7_RESET_PCIE_CTRL_APPS_EN:
  74. val |= sig[rst->id].bit;
  75. break;
  76. default:
  77. val &= ~sig[rst->id].bit;
  78. break;
  79. }
  80. writel(val, priv->base + sig[rst->id].offset);
  81. return 0;
  82. }
  83. static int imx7_reset_assert_imx7(struct reset_ctl *rst)
  84. {
  85. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  86. const struct imx7_src_signal *sig = imx7_src_signals;
  87. u32 val;
  88. if (rst->id >= IMX7_RESET_NUM)
  89. return -EINVAL;
  90. val = readl(priv->base + sig[rst->id].offset);
  91. switch (rst->id) {
  92. case IMX7_RESET_PCIE_CTRL_APPS_EN:
  93. val &= ~sig[rst->id].bit;
  94. break;
  95. default:
  96. val |= sig[rst->id].bit;
  97. break;
  98. }
  99. writel(val, priv->base + sig[rst->id].offset);
  100. return 0;
  101. }
  102. enum imx8mq_src_registers {
  103. SRC_A53RCR0 = 0x0004,
  104. SRC_HDMI_RCR = 0x0030,
  105. SRC_DISP_RCR = 0x0034,
  106. SRC_GPU_RCR = 0x0040,
  107. SRC_VPU_RCR = 0x0044,
  108. SRC_PCIE2_RCR = 0x0048,
  109. SRC_MIPIPHY1_RCR = 0x004c,
  110. SRC_MIPIPHY2_RCR = 0x0050,
  111. SRC_DDRC2_RCR = 0x1004,
  112. };
  113. static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
  114. [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
  115. [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
  116. [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
  117. [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
  118. [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
  119. [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
  120. [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
  121. [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
  122. [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
  123. [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
  124. [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
  125. [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
  126. [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
  127. [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
  128. [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
  129. [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
  130. [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
  131. [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
  132. [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
  133. [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
  134. [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
  135. [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
  136. [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
  137. [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
  138. [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
  139. [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
  140. [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
  141. BIT(2) | BIT(1) },
  142. [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  143. [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  144. [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  145. [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
  146. [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
  147. [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
  148. [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
  149. [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
  150. BIT(2) | BIT(1) },
  151. [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
  152. [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
  153. [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
  154. [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
  155. [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
  156. [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
  157. [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
  158. [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
  159. [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
  160. [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
  161. [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
  162. [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
  163. [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
  164. [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
  165. [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
  166. };
  167. static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
  168. {
  169. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  170. const struct imx7_src_signal *sig = imx8mq_src_signals;
  171. u32 val;
  172. if (rst->id >= IMX8MQ_RESET_NUM)
  173. return -EINVAL;
  174. if (rst->id == IMX8MQ_RESET_PCIEPHY ||
  175. rst->id == IMX8MQ_RESET_PCIEPHY2) {
  176. /*
  177. * wait for more than 10us to release phy g_rst and
  178. * btnrst
  179. */
  180. udelay(10);
  181. }
  182. val = readl(priv->base + sig[rst->id].offset);
  183. switch (rst->id) {
  184. case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
  185. case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
  186. case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
  187. case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
  188. case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
  189. case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
  190. case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
  191. val |= sig[rst->id].bit;
  192. break;
  193. default:
  194. val &= ~sig[rst->id].bit;
  195. break;
  196. }
  197. writel(val, priv->base + sig[rst->id].offset);
  198. return 0;
  199. }
  200. static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
  201. {
  202. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  203. const struct imx7_src_signal *sig = imx8mq_src_signals;
  204. u32 val;
  205. if (rst->id >= IMX8MQ_RESET_NUM)
  206. return -EINVAL;
  207. val = readl(priv->base + sig[rst->id].offset);
  208. switch (rst->id) {
  209. case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
  210. case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
  211. case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
  212. case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
  213. case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
  214. case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
  215. case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
  216. val &= ~sig[rst->id].bit;
  217. break;
  218. default:
  219. val |= sig[rst->id].bit;
  220. break;
  221. }
  222. writel(val, priv->base + sig[rst->id].offset);
  223. return 0;
  224. }
  225. static int imx7_reset_assert(struct reset_ctl *rst)
  226. {
  227. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  228. return priv->ops.rst_assert(rst);
  229. }
  230. static int imx7_reset_deassert(struct reset_ctl *rst)
  231. {
  232. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  233. return priv->ops.rst_deassert(rst);
  234. }
  235. static int imx7_reset_free(struct reset_ctl *rst)
  236. {
  237. return 0;
  238. }
  239. static int imx7_reset_request(struct reset_ctl *rst)
  240. {
  241. return 0;
  242. }
  243. static const struct reset_ops imx7_reset_reset_ops = {
  244. .request = imx7_reset_request,
  245. .rfree = imx7_reset_free,
  246. .rst_assert = imx7_reset_assert,
  247. .rst_deassert = imx7_reset_deassert,
  248. };
  249. static const struct udevice_id imx7_reset_ids[] = {
  250. { .compatible = "fsl,imx7d-src" },
  251. { .compatible = "fsl,imx8mq-src" },
  252. { }
  253. };
  254. static int imx7_reset_probe(struct udevice *dev)
  255. {
  256. struct imx7_reset_priv *priv = dev_get_priv(dev);
  257. priv->base = dev_remap_addr(dev);
  258. if (!priv->base)
  259. return -ENOMEM;
  260. if (device_is_compatible(dev, "fsl,imx8mq-src")) {
  261. priv->ops.rst_assert = imx7_reset_assert_imx8mq;
  262. priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
  263. } else if (device_is_compatible(dev, "fsl,imx7d-src")) {
  264. priv->ops.rst_assert = imx7_reset_assert_imx7;
  265. priv->ops.rst_deassert = imx7_reset_deassert_imx7;
  266. }
  267. return 0;
  268. }
  269. U_BOOT_DRIVER(imx7_reset) = {
  270. .name = "imx7_reset",
  271. .id = UCLASS_RESET,
  272. .of_match = imx7_reset_ids,
  273. .ops = &imx7_reset_reset_ops,
  274. .probe = imx7_reset_probe,
  275. .priv_auto_alloc_size = sizeof(struct imx7_reset_priv),
  276. };