zeus.h 14 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /************************************************************************
  8. * zeus.h - configuration for Zeus board
  9. ***********************************************************************/
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*-----------------------------------------------------------------------
  13. * High Level Configuration Options
  14. *----------------------------------------------------------------------*/
  15. #define CONFIG_ZEUS 1 /* Board is Zeus */
  16. #define CONFIG_4xx 1 /* ... PPC4xx family */
  17. #define CONFIG_405EP 1 /* Specifc 405EP support*/
  18. #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  19. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  20. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  21. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  22. #define PLLMR0_DEFAULT PLLMR0_333_111_55_111
  23. #define PLLMR1_DEFAULT PLLMR1_333_111_55_111
  24. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  25. #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  26. #define CONFIG_PPC4xx_EMAC
  27. #define CONFIG_MII 1 /* MII PHY management */
  28. #define CONFIG_PHY_ADDR 0x01 /* PHY address */
  29. #define CONFIG_HAS_ETH1 1
  30. #define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
  31. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
  32. #define CONFIG_PHY_RESET 1
  33. #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
  34. /*
  35. * BOOTP options
  36. */
  37. #define CONFIG_BOOTP_BOOTFILESIZE
  38. #define CONFIG_BOOTP_BOOTPATH
  39. #define CONFIG_BOOTP_GATEWAY
  40. #define CONFIG_BOOTP_HOSTNAME
  41. /*
  42. * Command line configuration.
  43. */
  44. #include <config_cmd_default.h>
  45. #define CONFIG_CMD_ASKENV
  46. #define CONFIG_CMD_CACHE
  47. #define CONFIG_CMD_DHCP
  48. #define CONFIG_CMD_DIAG
  49. #define CONFIG_CMD_EEPROM
  50. #define CONFIG_CMD_ELF
  51. #define CONFIG_CMD_I2C
  52. #define CONFIG_CMD_IRQ
  53. #define CONFIG_CMD_MII
  54. #define CONFIG_CMD_NET
  55. #define CONFIG_CMD_NFS
  56. #define CONFIG_CMD_PING
  57. #define CONFIG_CMD_REGINFO
  58. /* POST support */
  59. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  60. CONFIG_SYS_POST_CPU | \
  61. CONFIG_SYS_POST_CACHE | \
  62. CONFIG_SYS_POST_UART | \
  63. CONFIG_SYS_POST_ETHER)
  64. #define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
  65. /* Define here the base-addresses of the UARTs to test in POST */
  66. #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
  67. #define CONFIG_LOGBUFFER
  68. #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
  69. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
  70. #undef CONFIG_WATCHDOG /* watchdog disabled */
  71. /*-----------------------------------------------------------------------
  72. * SDRAM
  73. *----------------------------------------------------------------------*/
  74. /*
  75. * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  76. */
  77. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  78. #define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
  79. /* SDRAM timings used in datasheet */
  80. #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
  81. #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
  82. #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
  83. #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
  84. #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
  85. /*-----------------------------------------------------------------------
  86. * Serial Port
  87. *----------------------------------------------------------------------*/
  88. #define CONFIG_CONS_INDEX 1
  89. #define CONFIG_SYS_NS16550
  90. #define CONFIG_SYS_NS16550_SERIAL
  91. #define CONFIG_SYS_NS16550_REG_SIZE 1
  92. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  93. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  94. #define CONFIG_SYS_BASE_BAUD 691200
  95. #define CONFIG_BAUDRATE 115200
  96. #define CONFIG_SYS_BAUDRATE_TABLE \
  97. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  98. /*-----------------------------------------------------------------------
  99. * Miscellaneous configurable options
  100. *----------------------------------------------------------------------*/
  101. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  102. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  103. #if defined(CONFIG_CMD_KGDB)
  104. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  105. #else
  106. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  107. #endif
  108. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  109. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  110. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  111. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  112. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  113. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  114. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  115. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  116. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  117. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  118. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  119. #define CONFIG_LOOPW 1 /* enable loopw command */
  120. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  121. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  122. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  123. /*-----------------------------------------------------------------------
  124. * I2C
  125. *----------------------------------------------------------------------*/
  126. #define CONFIG_SYS_I2C
  127. #define CONFIG_SYS_I2C_PPC4XX
  128. #define CONFIG_SYS_I2C_PPC4XX_CH0
  129. #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
  130. #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
  131. /* these are for the ST M24C02 2kbit serial i2c eeprom */
  132. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
  133. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  134. /* mask of address bits that overflow into the "EEPROM chip address" */
  135. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  136. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
  137. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  138. /*
  139. * The layout of the I2C EEPROM, used for bootstrap setup and for board-
  140. * specific values, like ethaddr... that can be restored via the sw-reset
  141. * button
  142. */
  143. #define FACTORY_RESET_I2C_EEPROM 0x50
  144. #define FACTORY_RESET_ENV_OFFS 0x80
  145. #define FACTORY_RESET_ENV_SIZE 0x80
  146. /*-----------------------------------------------------------------------
  147. * Start addresses for the final memory configuration
  148. * (Set up by the startup code)
  149. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  150. */
  151. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  152. #define CONFIG_SYS_FLASH_BASE 0xFF000000
  153. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  154. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  155. #define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
  156. /*
  157. * For booting Linux, the board info and command line data
  158. * have to be in the first 8 MB of memory, since this is
  159. * the maximum mapped by the Linux kernel during initialization.
  160. */
  161. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  162. /*-----------------------------------------------------------------------
  163. * FLASH organization
  164. */
  165. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  166. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  167. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  168. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  169. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  170. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  171. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  172. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  173. #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
  174. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  175. #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
  176. #ifdef CONFIG_ENV_IS_IN_FLASH
  177. #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  178. #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
  179. #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  180. /* Address and size of Redundant Environment Sector */
  181. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  182. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  183. #endif
  184. /*-----------------------------------------------------------------------
  185. * Definitions for initial stack pointer and data area (in data cache)
  186. */
  187. /* use on chip memory (OCM) for temperary stack until sdram is tested */
  188. #define CONFIG_SYS_TEMP_STACK_OCM 1
  189. /* On Chip Memory location */
  190. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  191. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  192. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
  193. #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
  194. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  195. /* reserve some memory for POST and BOOT limit info */
  196. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
  197. /* extra data in OCM */
  198. #define CONFIG_SYS_POST_MAGIC \
  199. (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
  200. #define CONFIG_SYS_POST_VAL \
  201. (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
  202. /*-----------------------------------------------------------------------
  203. * External Bus Controller (EBC) Setup
  204. */
  205. /* Memory Bank 0 (Flash 16M) initialization */
  206. #define CONFIG_SYS_EBC_PB0AP 0x05815600
  207. #define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
  208. /*-----------------------------------------------------------------------
  209. * Definitions for GPIO setup (PPC405EP specific)
  210. *
  211. * GPIO0[0] - External Bus Controller BLAST output
  212. * GPIO0[1-9] - Instruction trace outputs
  213. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  214. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
  215. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  216. * GPIO0[24-27] - UART0 control signal inputs/outputs
  217. * GPIO0[28-29] - UART1 data signal input/output
  218. * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  219. */
  220. #define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
  221. #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
  222. #define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
  223. #define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
  224. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  225. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  226. #define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
  227. #define CONFIG_SYS_GPIO0_ODR 0x00000000
  228. #define CONFIG_SYS_GPIO_SW_RESET 1
  229. #define CONFIG_SYS_GPIO_ZEUS_PE 12
  230. #define CONFIG_SYS_GPIO_LED_RED 22
  231. #define CONFIG_SYS_GPIO_LED_GREEN 23
  232. /* Time in milli-seconds */
  233. #define CONFIG_SYS_TIME_POST 5000
  234. #define CONFIG_SYS_TIME_FACTORY_RESET 10000
  235. #if defined(CONFIG_CMD_KGDB)
  236. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  237. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  238. #endif
  239. /*
  240. * Pass open firmware flat tree
  241. */
  242. #define CONFIG_OF_LIBFDT
  243. #define CONFIG_OF_BOARD_SETUP
  244. /* ENVIRONMENT VARS */
  245. #define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
  246. #define CONFIG_IPADDR 192.168.1.10
  247. #define CONFIG_SERVERIP 192.168.1.100
  248. #define CONFIG_GATEWAYIP 192.168.1.100
  249. #define CONFIG_ETHADDR 50:00:00:00:06:00
  250. #define CONFIG_ETH1ADDR 50:00:00:00:06:01
  251. #if 0
  252. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  253. #else
  254. #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
  255. #endif
  256. #define CONFIG_EXTRA_ENV_SETTINGS \
  257. "logversion=2\0" \
  258. "hostname=zeus\0" \
  259. "netdev=eth0\0" \
  260. "ethact=ppc_4xx_eth0\0" \
  261. "netmask=255.255.255.0\0" \
  262. "ramdisk_size=50000\0" \
  263. "nfsargs=setenv bootargs root=/dev/nfs rw" \
  264. " nfsroot=${serverip}:${rootpath}\0" \
  265. "ramargs=setenv bootargs root=/dev/ram rw" \
  266. " ramdisk_size=${ramdisk_size}\0" \
  267. "addip=setenv bootargs ${bootargs} " \
  268. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  269. ":${hostname}:${netdev}:off panic=1\0" \
  270. "addtty=setenv bootargs ${bootargs} console=ttyS0," \
  271. "${baudrate}\0" \
  272. "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
  273. "run nfsargs addip addtty;bootm\0" \
  274. "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
  275. "tftp ${ramdisk_mem_addr} ${file_fs};" \
  276. "run ramargs addip addtty;" \
  277. "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
  278. "rootpath=/target_fs/zeus\0" \
  279. "kernel_fl_addr=ff000000\0" \
  280. "kernel_mem_addr=200000\0" \
  281. "ramdisk_fl_addr=ff300000\0" \
  282. "ramdisk_mem_addr=4000000\0" \
  283. "uboot_fl_addr=fffc0000\0" \
  284. "uboot_mem_addr=100000\0" \
  285. "file_uboot=/zeus/u-boot.bin\0" \
  286. "tftp_uboot=tftp 100000 ${file_uboot}\0" \
  287. "update_uboot=protect off fffc0000 ffffffff;" \
  288. "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
  289. "protect on fffc0000 ffffffff\0" \
  290. "upd_uboot=run tftp_uboot;run update_uboot\0" \
  291. "file_kernel=/zeus/uImage_ba\0" \
  292. "tftp_kernel=tftp 100000 ${file_kernel}\0" \
  293. "update_kernel=protect off ff000000 ff17ffff;" \
  294. "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
  295. "upd_kernel=run tftp_kernel;run update_kernel\0" \
  296. "file_fs=/zeus/rootfs_ba.img\0" \
  297. "tftp_fs=tftp 100000 ${file_fs}\0" \
  298. "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
  299. "cp.b 100000 ff300000 580000\0" \
  300. "upd_fs=run tftp_fs;run update_fs\0" \
  301. "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
  302. "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
  303. ""
  304. #endif /* __CONFIG_H */