P3G4.h 13 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. #ifndef __ASSEMBLY__
  13. #include <galileo/core.h>
  14. #endif
  15. #include "../board/evb64260/local.h"
  16. /*
  17. * High Level Configuration Options
  18. * (easy to change)
  19. */
  20. #define CONFIG_P3G4 1 /* this is a P3G4 board */
  21. #define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
  22. #define CONFIG_SYS_TEXT_BASE 0xfff00000
  23. #define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
  24. #undef CONFIG_ECC /* enable ECC support */
  25. /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
  26. /* which initialization functions to call for this board */
  27. #define CONFIG_MISC_INIT_R 1
  28. #define CONFIG_BOARD_EARLY_INIT_F 1
  29. #define CONFIG_SYS_BOARD_NAME "P3G4"
  30. #undef CONFIG_SYS_HUSH_PARSER
  31. /*
  32. * The following defines let you select what serial you want to use
  33. * for your console driver.
  34. *
  35. * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
  36. * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  37. */
  38. #define CONFIG_MPSC
  39. #define CONFIG_MPSC_PORT 0
  40. /* define this if you want to enable GT MAC filtering */
  41. #define CONFIG_GT_USE_MAC_HASH_TABLE
  42. #undef CONFIG_ETHER_PORT_MII /* use RMII */
  43. #if 0
  44. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  45. #else
  46. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  47. #endif
  48. #define CONFIG_ZERO_BOOTDELAY_CHECK
  49. #define CONFIG_PREBOOT "echo;" \
  50. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  51. "echo"
  52. #undef CONFIG_BOOTARGS
  53. #define CONFIG_EXTRA_ENV_SETTINGS \
  54. "netdev=eth0\0" \
  55. "hostname=p3g4\0" \
  56. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  57. "nfsroot=${serverip}:${rootpath}\0" \
  58. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  59. "addip=setenv bootargs ${bootargs} " \
  60. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  61. ":${hostname}:${netdev}:off panic=1\0" \
  62. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  63. "flash_nfs=run nfsargs addip addtty;" \
  64. "bootm ${kernel_addr}\0" \
  65. "flash_self=run ramargs addip addtty;" \
  66. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  67. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  68. "bootm\0" \
  69. "rootpath=/opt/eldk/ppc_74xx\0" \
  70. "bootfile=/tftpboot/p3g4/uImage\0" \
  71. "kernel_addr=ff000000\0" \
  72. "ramdisk_addr=ff010000\0" \
  73. "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
  74. "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
  75. "cp.b 100000 fff00000 ${filesize};" \
  76. "setenv filesize;saveenv\0" \
  77. "upd=run load update\0" \
  78. ""
  79. #define CONFIG_BOOTCOMMAND "run flash_self"
  80. #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
  81. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
  82. #undef CONFIG_WATCHDOG /* watchdog disabled */
  83. #undef CONFIG_ALTIVEC /* undef to disable */
  84. /*
  85. * BOOTP options
  86. */
  87. #define CONFIG_BOOTP_SUBNETMASK
  88. #define CONFIG_BOOTP_GATEWAY
  89. #define CONFIG_BOOTP_HOSTNAME
  90. #define CONFIG_BOOTP_BOOTPATH
  91. #define CONFIG_BOOTP_BOOTFILESIZE
  92. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  93. /*
  94. * Command line configuration.
  95. */
  96. #include <config_cmd_default.h>
  97. #define CONFIG_CMD_ASKENV
  98. #define CONFIG_CMD_DHCP
  99. #define CONFIG_CMD_PCI
  100. #define CONFIG_CMD_ELF
  101. #define CONFIG_CMD_MII
  102. #define CONFIG_CMD_PING
  103. #define CONFIG_CMD_UNIVERSE
  104. #define CONFIG_CMD_BSP
  105. /*
  106. * Miscellaneous configurable options
  107. */
  108. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  109. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  110. #if defined(CONFIG_CMD_KGDB)
  111. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  112. #else
  113. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  114. #endif
  115. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  116. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  117. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  118. #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
  119. #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
  120. #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
  121. #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
  122. #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
  123. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  124. /*
  125. * Low Level Configuration Settings
  126. * (address mappings, register initial values, etc.)
  127. * You should know what you are doing if you make changes here.
  128. */
  129. /*-----------------------------------------------------------------------
  130. * Definitions for initial stack pointer and data area
  131. */
  132. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  133. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  134. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  135. #define CONFIG_SYS_INIT_RAM_LOCK
  136. /*-----------------------------------------------------------------------
  137. * Start addresses for the final memory configuration
  138. * (Set up by the startup code)
  139. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  140. */
  141. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  142. #define CONFIG_SYS_FLASH_BASE 0xff000000
  143. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  144. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  145. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  146. #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
  147. /* areas to map different things with the GT in physical space */
  148. #define CONFIG_SYS_DRAM_BANKS 1
  149. #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
  150. /* What to put in the bats. */
  151. #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
  152. /* Peripheral Device section */
  153. #define CONFIG_SYS_GT_REGS 0xf8000000
  154. #define CONFIG_SYS_DEV_BASE 0xff000000
  155. #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
  156. #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
  157. #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
  158. #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
  159. #define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
  160. #define CONFIG_SYS_DEV1_SIZE 0 /* unused */
  161. #define CONFIG_SYS_DEV2_SIZE 0 /* unused */
  162. #define CONFIG_SYS_DEV3_SIZE 0 /* unused */
  163. #define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
  164. #define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
  165. #if 0 /* Wrong?? NTL */
  166. #define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
  167. /* DMAAck[1:0] GNT0[1:0] */
  168. #else
  169. #define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
  170. /* REQ0[1:0] GNT0[1:0] */
  171. #endif
  172. #define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
  173. /* DMAReq[4] DMAAck[4] WDNMI WDE */
  174. #if 0 /* Wrong?? NTL */
  175. #define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
  176. /* DMAAck[1:0] GNT1[1:0] */
  177. #else
  178. #define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
  179. /* GPP[22] (RS232IntB or PCI1Int) */
  180. /* GPP[21] (RS323IntA) */
  181. /* BClkIn */
  182. /* REQ1[1:0] GNT1[1:0] */
  183. #endif
  184. #if 0 /* Wrong?? NTL */
  185. # define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
  186. /* GPP[27:26] Int[1:0] */
  187. #else
  188. # define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
  189. /* GPP[29] (PCI1Int) */
  190. /* BClkOut0 */
  191. /* GPP[27] (PCI0Int) */
  192. /* GPP[26] (RtcInt or PCI1Int) */
  193. /* CPUInt[25:24] */
  194. #endif
  195. #define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
  196. #if 0 /* Wrong?? - NTL */
  197. # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
  198. #else
  199. # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
  200. /* gpp[29] */
  201. /* gpp[27:26] */
  202. /* gpp[22:21] */
  203. # define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
  204. /* idmas use buffer 1,1
  205. comm use buffer 0
  206. pci use buffer 1,1
  207. cpu use buffer 0
  208. normal load (see also ifdef HVL)
  209. standard SDRAM (see also ifdef REG)
  210. non staggered refresh */
  211. /* 31:26 25 23 20 19 18 16 */
  212. /* 110110 00 111 0 0 00 1 */
  213. /* refresh_count=0x200
  214. phisical interleaving disable
  215. virtual interleaving enable */
  216. /* 15 14 13:0 */
  217. /* 1 0 0x200 */
  218. #endif
  219. #if 0
  220. #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
  221. #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
  222. #endif
  223. #undef CONFIG_SYS_INIT_CHAN1
  224. #undef CONFIG_SYS_INIT_CHAN2
  225. #if 0
  226. #define SRAM_BASE CONFIG_SYS_DEV0_SPACE
  227. #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
  228. #endif
  229. /*-----------------------------------------------------------------------
  230. * PCI stuff
  231. *-----------------------------------------------------------------------
  232. */
  233. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  234. #define PCI_HOST_FORCE 1 /* configure as pci host */
  235. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  236. #define CONFIG_PCI /* include pci support */
  237. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  238. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  239. /* PCI MEMORY MAP section */
  240. #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
  241. #define CONFIG_SYS_PCI0_MEM_SIZE _128M
  242. #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
  243. #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
  244. #define CONFIG_SYS_PCI1_MEM_SIZE _128M
  245. #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
  246. /* PCI I/O MAP section */
  247. #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
  248. #define CONFIG_SYS_PCI0_IO_SIZE _16M
  249. #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
  250. #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
  251. #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
  252. #define CONFIG_SYS_PCI1_IO_SIZE _16M
  253. #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
  254. #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
  255. /*----------------------------------------------------------------------
  256. * Initial BAT mappings
  257. */
  258. /* NOTES:
  259. * 1) GUARDED and WRITE_THRU not allowed in IBATS
  260. * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
  261. */
  262. /* SDRAM */
  263. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  264. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  265. #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  266. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  267. /* init ram */
  268. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  269. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  270. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  271. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  272. /* PCI0, PCI1 in one BAT */
  273. #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
  274. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  275. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  276. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  277. /* GT regs, bootrom, all the devices, PCI I/O */
  278. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
  279. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
  280. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  281. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  282. /* I2C speed and slave address (for compatability) defaults */
  283. #define CONFIG_SYS_I2C_SPEED 400000
  284. #define CONFIG_SYS_I2C_SLAVE 0x7F
  285. /* I2C addresses for the two DIMM SPD chips */
  286. #ifndef CONFIG_EVB64260_750CX
  287. #define DIMM0_I2C_ADDR 0x56
  288. #define DIMM1_I2C_ADDR 0x54
  289. #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
  290. #define DIMM0_I2C_ADDR 0x54
  291. #define DIMM1_I2C_ADDR 0x54
  292. #endif
  293. /*
  294. * For booting Linux, the board info and command line data
  295. * have to be in the first 8 MB of memory, since this is
  296. * the maximum mapped by the Linux kernel during initialization.
  297. */
  298. #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
  299. /*-----------------------------------------------------------------------
  300. * FLASH organization
  301. */
  302. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  303. #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
  304. #define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
  305. #define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
  306. #define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
  307. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  308. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  309. #define CONFIG_SYS_FLASH_CFI 1
  310. #define CONFIG_ENV_IS_IN_FLASH 1
  311. #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  312. #define CONFIG_ENV_SECT_SIZE 0x20000
  313. #define CONFIG_ENV_ADDR 0xFFFE0000
  314. /*-----------------------------------------------------------------------
  315. * Cache Configuration
  316. */
  317. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  318. #if defined(CONFIG_CMD_KGDB)
  319. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  320. #endif
  321. /*-----------------------------------------------------------------------
  322. * L2CR setup -- make sure this is right for your board!
  323. * look in include/74xx_7xx.h for the defines used here
  324. */
  325. #define CONFIG_SYS_L2
  326. #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  327. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  328. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  329. #define CONFIG_SYS_BOARD_ASM_INIT 1
  330. #endif /* __CONFIG_H */