pci.c 33 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /* PCI.c - PCI functions */
  8. #include <common.h>
  9. #ifdef CONFIG_PCI
  10. #include <pci.h>
  11. #include "../../Marvell/include/pci.h"
  12. #undef DEBUG
  13. #undef IDE_SET_NATIVE_MODE
  14. static unsigned int local_buses[] = { 0, 0 };
  15. static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
  16. {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
  17. {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
  18. };
  19. #ifdef CONFIG_USE_CPCIDVI
  20. typedef struct {
  21. unsigned int base;
  22. unsigned int init;
  23. } GT_CPCIDVI_ROM_T;
  24. static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
  25. #endif
  26. #ifdef DEBUG
  27. static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
  28. static void gt_pci_bus_mode_display (PCI_HOST host)
  29. {
  30. unsigned int mode;
  31. mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
  32. switch (mode) {
  33. case 0:
  34. printf ("PCI %d bus mode: Conventional PCI\n", host);
  35. break;
  36. case 1:
  37. printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
  38. break;
  39. case 2:
  40. printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
  41. break;
  42. case 3:
  43. printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
  44. break;
  45. default:
  46. printf ("Unknown BUS %d\n", mode);
  47. }
  48. }
  49. #endif
  50. static const unsigned int pci_p2p_configuration_reg[] = {
  51. PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
  52. };
  53. static const unsigned int pci_configuration_address[] = {
  54. PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
  55. };
  56. static const unsigned int pci_configuration_data[] = {
  57. PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
  58. PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
  59. };
  60. static const unsigned int pci_error_cause_reg[] = {
  61. PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
  62. };
  63. static const unsigned int pci_arbiter_control[] = {
  64. PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
  65. };
  66. static const unsigned int pci_address_space_en[] = {
  67. PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
  68. };
  69. static const unsigned int pci_snoop_control_base_0_low[] = {
  70. PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
  71. };
  72. static const unsigned int pci_snoop_control_top_0[] = {
  73. PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
  74. };
  75. static const unsigned int pci_access_control_base_0_low[] = {
  76. PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
  77. };
  78. static const unsigned int pci_access_control_top_0[] = {
  79. PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
  80. };
  81. static const unsigned int pci_scs_bank_size[2][4] = {
  82. {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
  83. PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
  84. {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
  85. PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
  86. };
  87. static const unsigned int pci_p2p_configuration[] = {
  88. PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
  89. };
  90. /********************************************************************
  91. * pciWriteConfigReg - Write to a PCI configuration register
  92. * - Make sure the GT is configured as a master before writing
  93. * to another device on the PCI.
  94. * - The function takes care of Big/Little endian conversion.
  95. *
  96. *
  97. * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
  98. * (or any other PCI device spec)
  99. * pciDevNum: The device number needs to be addressed.
  100. *
  101. * Configuration Address 0xCF8:
  102. *
  103. * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
  104. * |congif|Reserved| Bus |Device|Function|Register|00|
  105. * |Enable| |Number|Number| Number | Number | | <=field Name
  106. *
  107. *********************************************************************/
  108. void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
  109. unsigned int pciDevNum, unsigned int data)
  110. {
  111. volatile unsigned int DataForAddrReg;
  112. unsigned int functionNum;
  113. unsigned int busNum = 0;
  114. unsigned int addr;
  115. if (pciDevNum > 32) /* illegal device Number */
  116. return;
  117. if (pciDevNum == SELF) { /* configure our configuration space. */
  118. pciDevNum =
  119. (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
  120. 0x1f;
  121. busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
  122. 0xff0000;
  123. }
  124. functionNum = regOffset & 0x00000700;
  125. pciDevNum = pciDevNum << 11;
  126. regOffset = regOffset & 0xfc;
  127. DataForAddrReg =
  128. (regOffset | pciDevNum | functionNum | busNum) | BIT31;
  129. GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
  130. GT_REG_READ (pci_configuration_address[host], &addr);
  131. if (addr != DataForAddrReg)
  132. return;
  133. GT_REG_WRITE (pci_configuration_data[host], data);
  134. }
  135. /********************************************************************
  136. * pciReadConfigReg - Read from a PCI0 configuration register
  137. * - Make sure the GT is configured as a master before reading
  138. * from another device on the PCI.
  139. * - The function takes care of Big/Little endian conversion.
  140. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
  141. * spec)
  142. * pciDevNum: The device number needs to be addressed.
  143. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
  144. * cause register to make sure the data is valid
  145. *
  146. * Configuration Address 0xCF8:
  147. *
  148. * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
  149. * |congif|Reserved| Bus |Device|Function|Register|00|
  150. * |Enable| |Number|Number| Number | Number | | <=field Name
  151. *
  152. *********************************************************************/
  153. unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
  154. unsigned int pciDevNum)
  155. {
  156. volatile unsigned int DataForAddrReg;
  157. unsigned int data;
  158. unsigned int functionNum;
  159. unsigned int busNum = 0;
  160. if (pciDevNum > 32) /* illegal device Number */
  161. return 0xffffffff;
  162. if (pciDevNum == SELF) { /* configure our configuration space. */
  163. pciDevNum =
  164. (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
  165. 0x1f;
  166. busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
  167. 0xff0000;
  168. }
  169. functionNum = regOffset & 0x00000700;
  170. pciDevNum = pciDevNum << 11;
  171. regOffset = regOffset & 0xfc;
  172. DataForAddrReg =
  173. (regOffset | pciDevNum | functionNum | busNum) | BIT31;
  174. GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
  175. GT_REG_READ (pci_configuration_address[host], &data);
  176. if (data != DataForAddrReg)
  177. return 0xffffffff;
  178. GT_REG_READ (pci_configuration_data[host], &data);
  179. return data;
  180. }
  181. /********************************************************************
  182. * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
  183. * the agent is placed on another Bus. For more
  184. * information read P2P in the PCI spec.
  185. *
  186. * Inputs: unsigned int regOffset - The register offset as it apears in the
  187. * GT spec (or any other PCI device spec).
  188. * unsigned int pciDevNum - The device number needs to be addressed.
  189. * unsigned int busNum - On which bus does the Target agent connect
  190. * to.
  191. * unsigned int data - data to be written.
  192. *
  193. * Configuration Address 0xCF8:
  194. *
  195. * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
  196. * |congif|Reserved| Bus |Device|Function|Register|01|
  197. * |Enable| |Number|Number| Number | Number | | <=field Name
  198. *
  199. * The configuration Address is configure as type-I (bits[1:0] = '01') due to
  200. * PCI spec referring to P2P.
  201. *
  202. *********************************************************************/
  203. void pciOverBridgeWriteConfigReg (PCI_HOST host,
  204. unsigned int regOffset,
  205. unsigned int pciDevNum,
  206. unsigned int busNum, unsigned int data)
  207. {
  208. unsigned int DataForReg;
  209. unsigned int functionNum;
  210. functionNum = regOffset & 0x00000700;
  211. pciDevNum = pciDevNum << 11;
  212. regOffset = regOffset & 0xff;
  213. busNum = busNum << 16;
  214. if (pciDevNum == SELF) { /* This board */
  215. DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
  216. } else {
  217. DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
  218. BIT31 | BIT0;
  219. }
  220. GT_REG_WRITE (pci_configuration_address[host], DataForReg);
  221. GT_REG_WRITE (pci_configuration_data[host], data);
  222. }
  223. /********************************************************************
  224. * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
  225. * the agent target locate on another PCI bus.
  226. * - Make sure the GT is configured as a master
  227. * before reading from another device on the PCI.
  228. * - The function takes care of Big/Little endian
  229. * conversion.
  230. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
  231. * spec). (configuration register offset.)
  232. * pciDevNum: The device number needs to be addressed.
  233. * busNum: the Bus number where the agent is place.
  234. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
  235. * cause register to make sure the data is valid
  236. *
  237. * Configuration Address 0xCF8:
  238. *
  239. * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
  240. * |congif|Reserved| Bus |Device|Function|Register|01|
  241. * |Enable| |Number|Number| Number | Number | | <=field Name
  242. *
  243. *********************************************************************/
  244. unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
  245. unsigned int regOffset,
  246. unsigned int pciDevNum,
  247. unsigned int busNum)
  248. {
  249. unsigned int DataForReg;
  250. unsigned int data;
  251. unsigned int functionNum;
  252. functionNum = regOffset & 0x00000700;
  253. pciDevNum = pciDevNum << 11;
  254. regOffset = regOffset & 0xff;
  255. busNum = busNum << 16;
  256. if (pciDevNum == SELF) { /* This board */
  257. DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
  258. } else { /* agent on another bus */
  259. DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
  260. BIT0 | BIT31;
  261. }
  262. GT_REG_WRITE (pci_configuration_address[host], DataForReg);
  263. GT_REG_READ (pci_configuration_data[host], &data);
  264. return data;
  265. }
  266. /********************************************************************
  267. * pciGetRegOffset - Gets the register offset for this region config.
  268. *
  269. * INPUT: Bus, Region - The bus and region we ask for its base address.
  270. * OUTPUT: N/A
  271. * RETURNS: PCI register base address
  272. *********************************************************************/
  273. static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
  274. {
  275. switch (host) {
  276. case PCI_HOST0:
  277. switch (region) {
  278. case PCI_IO:
  279. return PCI_0I_O_LOW_DECODE_ADDRESS;
  280. case PCI_REGION0:
  281. return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
  282. case PCI_REGION1:
  283. return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
  284. case PCI_REGION2:
  285. return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
  286. case PCI_REGION3:
  287. return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
  288. }
  289. case PCI_HOST1:
  290. switch (region) {
  291. case PCI_IO:
  292. return PCI_1I_O_LOW_DECODE_ADDRESS;
  293. case PCI_REGION0:
  294. return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
  295. case PCI_REGION1:
  296. return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
  297. case PCI_REGION2:
  298. return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
  299. case PCI_REGION3:
  300. return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
  301. }
  302. }
  303. return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
  304. }
  305. static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
  306. {
  307. switch (host) {
  308. case PCI_HOST0:
  309. switch (region) {
  310. case PCI_IO:
  311. return PCI_0I_O_ADDRESS_REMAP;
  312. case PCI_REGION0:
  313. return PCI_0MEMORY0_ADDRESS_REMAP;
  314. case PCI_REGION1:
  315. return PCI_0MEMORY1_ADDRESS_REMAP;
  316. case PCI_REGION2:
  317. return PCI_0MEMORY2_ADDRESS_REMAP;
  318. case PCI_REGION3:
  319. return PCI_0MEMORY3_ADDRESS_REMAP;
  320. }
  321. case PCI_HOST1:
  322. switch (region) {
  323. case PCI_IO:
  324. return PCI_1I_O_ADDRESS_REMAP;
  325. case PCI_REGION0:
  326. return PCI_1MEMORY0_ADDRESS_REMAP;
  327. case PCI_REGION1:
  328. return PCI_1MEMORY1_ADDRESS_REMAP;
  329. case PCI_REGION2:
  330. return PCI_1MEMORY2_ADDRESS_REMAP;
  331. case PCI_REGION3:
  332. return PCI_1MEMORY3_ADDRESS_REMAP;
  333. }
  334. }
  335. return PCI_0MEMORY0_ADDRESS_REMAP;
  336. }
  337. /********************************************************************
  338. * pciGetBaseAddress - Gets the base address of a PCI.
  339. * - If the PCI size is 0 then this base address has no meaning!!!
  340. *
  341. *
  342. * INPUT: Bus, Region - The bus and region we ask for its base address.
  343. * OUTPUT: N/A
  344. * RETURNS: PCI base address.
  345. *********************************************************************/
  346. unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
  347. {
  348. unsigned int regBase;
  349. unsigned int regEnd;
  350. unsigned int regOffset = pciGetRegOffset (host, region);
  351. GT_REG_READ (regOffset, &regBase);
  352. GT_REG_READ (regOffset + 8, &regEnd);
  353. if (regEnd <= regBase)
  354. return 0xffffffff; /* ERROR !!! */
  355. regBase = regBase << 16;
  356. return regBase;
  357. }
  358. bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
  359. unsigned int bankBase, unsigned int bankLength)
  360. {
  361. unsigned int low = 0xfff;
  362. unsigned int high = 0x0;
  363. unsigned int regOffset = pciGetRegOffset (host, region);
  364. unsigned int remapOffset = pciGetRemapOffset (host, region);
  365. if (bankLength != 0) {
  366. low = (bankBase >> 16) & 0xffff;
  367. high = ((bankBase + bankLength) >> 16) - 1;
  368. }
  369. GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
  370. GT_REG_WRITE (regOffset + 8, high);
  371. if (bankLength != 0) { /* must do AFTER writing maps */
  372. GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
  373. dont support upper 32
  374. in this driver */
  375. }
  376. return true;
  377. }
  378. unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
  379. {
  380. unsigned int low;
  381. unsigned int regOffset = pciGetRegOffset (host, region);
  382. GT_REG_READ (regOffset, &low);
  383. return (low & 0xffff) << 16;
  384. }
  385. unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
  386. {
  387. unsigned int low, high;
  388. unsigned int regOffset = pciGetRegOffset (host, region);
  389. GT_REG_READ (regOffset, &low);
  390. GT_REG_READ (regOffset + 8, &high);
  391. return ((high & 0xffff) + 1) << 16;
  392. }
  393. /* ronen - 7/Dec/03*/
  394. /********************************************************************
  395. * gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
  396. * Inputs: one of the PCI BAR
  397. *********************************************************************/
  398. void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
  399. {
  400. RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
  401. }
  402. void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
  403. {
  404. SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
  405. }
  406. /********************************************************************
  407. * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
  408. *
  409. * Inputs: base and size of PCI SCS
  410. *********************************************************************/
  411. void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
  412. unsigned int pciDramBase, unsigned int pciDramSize)
  413. {
  414. /*ronen different function for 3rd bank. */
  415. unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
  416. pciDramBase = pciDramBase & 0xfffff000;
  417. pciDramBase = pciDramBase | (pciReadConfigReg (host,
  418. PCI_SCS_0_BASE_ADDRESS
  419. + offset,
  420. SELF) & 0x00000fff);
  421. pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
  422. pciDramBase);
  423. if (pciDramSize == 0)
  424. pciDramSize++;
  425. GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
  426. gtPciEnableInternalBAR (host, bank);
  427. }
  428. /********************************************************************
  429. * pciSetRegionFeatures - This function modifys one of the 8 regions with
  430. * feature bits given as an input.
  431. * - Be advised to check the spec before modifying them.
  432. * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
  433. * unsigned int features - See file: pci.h there are defintion for those
  434. * region features.
  435. * unsigned int baseAddress - The region base Address.
  436. * unsigned int topAddress - The region top Address.
  437. * Returns: false if one of the parameters is erroneous true otherwise.
  438. *********************************************************************/
  439. bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
  440. unsigned int features, unsigned int baseAddress,
  441. unsigned int regionLength)
  442. {
  443. unsigned int accessLow;
  444. unsigned int accessHigh;
  445. unsigned int accessTop = baseAddress + regionLength;
  446. if (regionLength == 0) { /* close the region. */
  447. pciDisableAccessRegion (host, region);
  448. return true;
  449. }
  450. /* base Address is store is bits [11:0] */
  451. accessLow = (baseAddress & 0xfff00000) >> 20;
  452. /* All the features are update according to the defines in pci.h (to be on
  453. the safe side we disable bits: [11:0] */
  454. accessLow = accessLow | (features & 0xfffff000);
  455. /* write to the Low Access Region register */
  456. GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
  457. accessLow);
  458. accessHigh = (accessTop & 0xfff00000) >> 20;
  459. /* write to the High Access Region register */
  460. GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
  461. accessHigh - 1);
  462. return true;
  463. }
  464. /********************************************************************
  465. * pciDisableAccessRegion - Disable The given Region by writing MAX size
  466. * to its low Address and MIN size to its high Address.
  467. *
  468. * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
  469. * Returns: N/A.
  470. *********************************************************************/
  471. void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
  472. {
  473. /* writing back the registers default values. */
  474. GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
  475. 0x01001fff);
  476. GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
  477. }
  478. /********************************************************************
  479. * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
  480. *
  481. * Inputs: N/A
  482. * Returns: true.
  483. *********************************************************************/
  484. bool pciArbiterEnable (PCI_HOST host)
  485. {
  486. unsigned int regData;
  487. GT_REG_READ (pci_arbiter_control[host], &regData);
  488. GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
  489. return true;
  490. }
  491. /********************************************************************
  492. * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
  493. *
  494. * Inputs: N/A
  495. * Returns: true
  496. *********************************************************************/
  497. bool pciArbiterDisable (PCI_HOST host)
  498. {
  499. unsigned int regData;
  500. GT_REG_READ (pci_arbiter_control[host], &regData);
  501. GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
  502. return true;
  503. }
  504. /********************************************************************
  505. * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
  506. *
  507. * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
  508. * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
  509. * PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
  510. * PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
  511. * PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
  512. * PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
  513. * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
  514. * Returns: true
  515. *********************************************************************/
  516. bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
  517. PCI_AGENT_PRIO externalAgent0,
  518. PCI_AGENT_PRIO externalAgent1,
  519. PCI_AGENT_PRIO externalAgent2,
  520. PCI_AGENT_PRIO externalAgent3,
  521. PCI_AGENT_PRIO externalAgent4,
  522. PCI_AGENT_PRIO externalAgent5)
  523. {
  524. unsigned int regData;
  525. unsigned int writeData;
  526. GT_REG_READ (pci_arbiter_control[host], &regData);
  527. writeData = (internalAgent << 7) + (externalAgent0 << 8) +
  528. (externalAgent1 << 9) + (externalAgent2 << 10) +
  529. (externalAgent3 << 11) + (externalAgent4 << 12) +
  530. (externalAgent5 << 13);
  531. regData = (regData & 0xffffc07f) | writeData;
  532. GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
  533. return true;
  534. }
  535. /********************************************************************
  536. * pciParkingDisable - Park on last option disable, with this function you can
  537. * disable the park on last mechanism for each agent.
  538. * disabling this option for all agents results parking
  539. * on the internal master.
  540. *
  541. * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
  542. * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
  543. * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
  544. * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
  545. * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
  546. * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
  547. * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
  548. * Returns: true
  549. *********************************************************************/
  550. bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
  551. PCI_AGENT_PARK externalAgent0,
  552. PCI_AGENT_PARK externalAgent1,
  553. PCI_AGENT_PARK externalAgent2,
  554. PCI_AGENT_PARK externalAgent3,
  555. PCI_AGENT_PARK externalAgent4,
  556. PCI_AGENT_PARK externalAgent5)
  557. {
  558. unsigned int regData;
  559. unsigned int writeData;
  560. GT_REG_READ (pci_arbiter_control[host], &regData);
  561. writeData = (internalAgent << 14) + (externalAgent0 << 15) +
  562. (externalAgent1 << 16) + (externalAgent2 << 17) +
  563. (externalAgent3 << 18) + (externalAgent4 << 19) +
  564. (externalAgent5 << 20);
  565. regData = (regData & ~(0x7f << 14)) | writeData;
  566. GT_REG_WRITE (pci_arbiter_control[host], regData);
  567. return true;
  568. }
  569. /********************************************************************
  570. * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
  571. * respond to grant assertion within a window specified in
  572. * the input value: 'brokenValue'.
  573. *
  574. * Inputs: unsigned char brokenValue - A value which limits the Master to hold the
  575. * grant without asserting frame.
  576. * Returns: Error for illegal broken value otherwise true.
  577. *********************************************************************/
  578. bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
  579. {
  580. unsigned int data;
  581. unsigned int regData;
  582. if (brokenValue > 0xf)
  583. return false; /* brokenValue must be 4 bit */
  584. data = brokenValue << 3;
  585. GT_REG_READ (pci_arbiter_control[host], &regData);
  586. regData = (regData & 0xffffff87) | data;
  587. GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
  588. return true;
  589. }
  590. /********************************************************************
  591. * pciDisableBrokenAgentDetection - This function disable the Broken agent
  592. * Detection mechanism.
  593. * NOTE: This operation may cause a dead lock on the
  594. * pci0 arbitration.
  595. *
  596. * Inputs: N/A
  597. * Returns: true.
  598. *********************************************************************/
  599. bool pciDisableBrokenAgentDetection (PCI_HOST host)
  600. {
  601. unsigned int regData;
  602. GT_REG_READ (pci_arbiter_control[host], &regData);
  603. regData = regData & 0xfffffffd;
  604. GT_REG_WRITE (pci_arbiter_control[host], regData);
  605. return true;
  606. }
  607. /********************************************************************
  608. * pciP2PConfig - This function set the PCI_n P2P configurate.
  609. * For more information on the P2P read PCI spec.
  610. *
  611. * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
  612. * Boundry.
  613. * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
  614. * Boundry.
  615. * unsigned int busNum - The CPI bus number to which the PCI interface
  616. * is connected.
  617. * unsigned int devNum - The PCI interface's device number.
  618. *
  619. * Returns: true.
  620. *********************************************************************/
  621. bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
  622. unsigned int SecondBusHigh,
  623. unsigned int busNum, unsigned int devNum)
  624. {
  625. unsigned int regData;
  626. regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
  627. ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
  628. GT_REG_WRITE (pci_p2p_configuration[host], regData);
  629. return true;
  630. }
  631. /********************************************************************
  632. * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
  633. * supports Cache Coherency in the PCI_n interface.
  634. * Inputs: region - One of the four regions.
  635. * snoopType - There is four optional Types:
  636. * 1. No Snoop.
  637. * 2. Snoop to WT region.
  638. * 3. Snoop to WB region.
  639. * 4. Snoop & Invalidate to WB region.
  640. * baseAddress - Base Address of this region.
  641. * regionLength - Region length.
  642. * Returns: false if one of the parameters is wrong otherwise return true.
  643. *********************************************************************/
  644. bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
  645. PCI_SNOOP_TYPE snoopType,
  646. unsigned int baseAddress,
  647. unsigned int regionLength)
  648. {
  649. unsigned int snoopXbaseAddress;
  650. unsigned int snoopXtopAddress;
  651. unsigned int data;
  652. unsigned int snoopHigh = baseAddress + regionLength;
  653. if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
  654. return false;
  655. snoopXbaseAddress =
  656. pci_snoop_control_base_0_low[host] + 0x10 * region;
  657. snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
  658. if (regionLength == 0) { /* closing the region */
  659. GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
  660. GT_REG_WRITE (snoopXtopAddress, 0);
  661. return true;
  662. }
  663. baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
  664. data = (baseAddress >> 20) | snoopType << 12;
  665. GT_REG_WRITE (snoopXbaseAddress, data);
  666. snoopHigh = (snoopHigh & 0xfff00000) >> 20;
  667. GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
  668. return true;
  669. }
  670. static int gt_read_config_dword (struct pci_controller *hose,
  671. pci_dev_t dev, int offset, u32 * value)
  672. {
  673. int bus = PCI_BUS (dev);
  674. if ((bus == local_buses[0]) || (bus == local_buses[1])) {
  675. *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
  676. offset | (PCI_FUNC(dev) << 8),
  677. PCI_DEV (dev));
  678. } else {
  679. *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
  680. offset | (PCI_FUNC(dev) << 8),
  681. PCI_DEV (dev), bus);
  682. }
  683. return 0;
  684. }
  685. static int gt_write_config_dword (struct pci_controller *hose,
  686. pci_dev_t dev, int offset, u32 value)
  687. {
  688. int bus = PCI_BUS (dev);
  689. if ((bus == local_buses[0]) || (bus == local_buses[1])) {
  690. pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
  691. offset | (PCI_FUNC(dev) << 8),
  692. PCI_DEV (dev), value);
  693. } else {
  694. pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
  695. offset | (PCI_FUNC(dev) << 8),
  696. PCI_DEV (dev), bus,
  697. value);
  698. }
  699. return 0;
  700. }
  701. static void gt_setup_ide (struct pci_controller *hose,
  702. pci_dev_t dev, struct pci_config_table *entry)
  703. {
  704. static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
  705. u32 bar_response, bar_value;
  706. int bar;
  707. if (CPCI750_SLAVE_TEST != 0)
  708. return;
  709. for (bar = 0; bar < 6; bar++) {
  710. /*ronen different function for 3rd bank. */
  711. unsigned int offset =
  712. (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
  713. pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
  714. 0x0);
  715. pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
  716. &bar_response);
  717. pciauto_region_allocate (bar_response &
  718. PCI_BASE_ADDRESS_SPACE_IO ? hose->
  719. pci_io : hose->pci_mem, ide_bar[bar],
  720. &bar_value);
  721. pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
  722. bar_value);
  723. }
  724. }
  725. #ifdef CONFIG_USE_CPCIDVI
  726. static void gt_setup_cpcidvi (struct pci_controller *hose,
  727. pci_dev_t dev, struct pci_config_table *entry)
  728. {
  729. u32 bar_value, pci_response;
  730. if (CPCI750_SLAVE_TEST != 0)
  731. return;
  732. pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
  733. pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
  734. pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
  735. pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
  736. pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
  737. pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
  738. pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
  739. pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
  740. gt_cpcidvi_rom.base = bar_value & 0xffffff00;
  741. gt_cpcidvi_rom.init = 1;
  742. }
  743. unsigned char gt_cpcidvi_in8(unsigned int offset)
  744. {
  745. unsigned char data;
  746. if (gt_cpcidvi_rom.init == 0) {
  747. return(0);
  748. }
  749. data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
  750. return(data);
  751. }
  752. void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
  753. {
  754. unsigned int off;
  755. if (gt_cpcidvi_rom.init == 0) {
  756. return;
  757. }
  758. off = data;
  759. off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
  760. in8(off);
  761. return;
  762. }
  763. #endif
  764. /* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
  765. /* and is curently not called *. */
  766. #if 0
  767. static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
  768. {
  769. unsigned char pin, irq;
  770. pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
  771. if (pin == 1) { /* only allow INT A */
  772. irq = pci_irq_swizzle[(PCI_HOST) hose->
  773. cfg_addr][PCI_DEV (dev)];
  774. if (irq)
  775. pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
  776. }
  777. }
  778. #endif
  779. struct pci_config_table gt_config_table[] = {
  780. #ifdef CONFIG_USE_CPCIDVI
  781. {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
  782. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
  783. #endif
  784. {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
  785. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
  786. {}
  787. };
  788. struct pci_controller pci0_hose = {
  789. /* fixup_irq: gt_fixup_irq, */
  790. config_table:gt_config_table,
  791. };
  792. struct pci_controller pci1_hose = {
  793. /* fixup_irq: gt_fixup_irq, */
  794. config_table:gt_config_table,
  795. };
  796. void pci_init_board (void)
  797. {
  798. unsigned int command;
  799. unsigned int slave;
  800. #ifdef CONFIG_PCI_PNP
  801. unsigned int bar;
  802. #endif
  803. #ifdef DEBUG
  804. gt_pci_bus_mode_display (PCI_HOST0);
  805. #endif
  806. #ifdef CONFIG_USE_CPCIDVI
  807. gt_cpcidvi_rom.init = 0;
  808. gt_cpcidvi_rom.base = 0;
  809. #endif
  810. slave = CPCI750_SLAVE_TEST;
  811. pci0_hose.config_table = gt_config_table;
  812. pci1_hose.config_table = gt_config_table;
  813. #ifdef CONFIG_USE_CPCIDVI
  814. gt_config_table[0].config_device = gt_setup_cpcidvi;
  815. #endif
  816. gt_config_table[1].config_device = gt_setup_ide;
  817. pci0_hose.first_busno = 0;
  818. pci0_hose.last_busno = 0xff;
  819. local_buses[0] = pci0_hose.first_busno;
  820. /* PCI memory space */
  821. pci_set_region (pci0_hose.regions + 0,
  822. CONFIG_SYS_PCI0_0_MEM_SPACE,
  823. CONFIG_SYS_PCI0_0_MEM_SPACE,
  824. CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
  825. /* PCI I/O space */
  826. pci_set_region (pci0_hose.regions + 1,
  827. CONFIG_SYS_PCI0_IO_SPACE_PCI,
  828. CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
  829. pci_set_ops (&pci0_hose,
  830. pci_hose_read_config_byte_via_dword,
  831. pci_hose_read_config_word_via_dword,
  832. gt_read_config_dword,
  833. pci_hose_write_config_byte_via_dword,
  834. pci_hose_write_config_word_via_dword,
  835. gt_write_config_dword);
  836. pci0_hose.region_count = 2;
  837. pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
  838. pci_register_hose (&pci0_hose);
  839. if (slave == 0) {
  840. pciArbiterEnable (PCI_HOST0);
  841. pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
  842. command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
  843. command |= PCI_COMMAND_MASTER;
  844. pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
  845. command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
  846. command |= PCI_COMMAND_MEMORY;
  847. pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
  848. #ifdef CONFIG_PCI_PNP
  849. pciauto_config_init(&pci0_hose);
  850. pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
  851. #endif
  852. #ifdef CONFIG_PCI_SCAN_SHOW
  853. printf("PCI: Bus Dev VenId DevId Class Int\n");
  854. #endif
  855. pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
  856. pci0_hose.first_busno);
  857. #ifdef DEBUG
  858. gt_pci_bus_mode_display (PCI_HOST1);
  859. #endif
  860. } else {
  861. pciArbiterDisable (PCI_HOST0);
  862. pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
  863. command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
  864. command |= PCI_COMMAND_MASTER;
  865. pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
  866. command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
  867. command |= PCI_COMMAND_MEMORY;
  868. pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
  869. pci0_hose.last_busno = pci0_hose.first_busno;
  870. }
  871. pci1_hose.first_busno = pci0_hose.last_busno + 1;
  872. pci1_hose.last_busno = 0xff;
  873. pci1_hose.current_busno = pci1_hose.first_busno;
  874. local_buses[1] = pci1_hose.first_busno;
  875. /* PCI memory space */
  876. pci_set_region (pci1_hose.regions + 0,
  877. CONFIG_SYS_PCI1_0_MEM_SPACE,
  878. CONFIG_SYS_PCI1_0_MEM_SPACE,
  879. CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
  880. /* PCI I/O space */
  881. pci_set_region (pci1_hose.regions + 1,
  882. CONFIG_SYS_PCI1_IO_SPACE_PCI,
  883. CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
  884. pci_set_ops (&pci1_hose,
  885. pci_hose_read_config_byte_via_dword,
  886. pci_hose_read_config_word_via_dword,
  887. gt_read_config_dword,
  888. pci_hose_write_config_byte_via_dword,
  889. pci_hose_write_config_word_via_dword,
  890. gt_write_config_dword);
  891. pci1_hose.region_count = 2;
  892. pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
  893. pci_register_hose (&pci1_hose);
  894. pciArbiterEnable (PCI_HOST1);
  895. pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
  896. command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
  897. command |= PCI_COMMAND_MASTER;
  898. pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
  899. #ifdef CONFIG_PCI_PNP
  900. pciauto_config_init(&pci1_hose);
  901. pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
  902. #endif
  903. pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
  904. command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
  905. command |= PCI_COMMAND_MEMORY;
  906. pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
  907. }
  908. #endif /* of CONFIG_PCI */