cpu_init.c 14 KB

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  1. /*
  2. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <mpc83xx.h>
  8. #include <ioports.h>
  9. #include <asm/io.h>
  10. #ifdef CONFIG_USB_EHCI_FSL
  11. #include <usb/ehci-fsl.h>
  12. #endif
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #ifdef CONFIG_QE
  15. extern qe_iop_conf_t qe_iop_conf_tab[];
  16. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  17. int open_drain, int assign);
  18. extern void qe_init(uint qe_base);
  19. extern void qe_reset(void);
  20. static void config_qe_ioports(void)
  21. {
  22. u8 port, pin;
  23. int dir, open_drain, assign;
  24. int i;
  25. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  26. port = qe_iop_conf_tab[i].port;
  27. pin = qe_iop_conf_tab[i].pin;
  28. dir = qe_iop_conf_tab[i].dir;
  29. open_drain = qe_iop_conf_tab[i].open_drain;
  30. assign = qe_iop_conf_tab[i].assign;
  31. qe_config_iopin(port, pin, dir, open_drain, assign);
  32. }
  33. }
  34. #endif
  35. /*
  36. * Breathe some life into the CPU...
  37. *
  38. * Set up the memory map,
  39. * initialize a bunch of registers,
  40. * initialize the UPM's
  41. */
  42. void cpu_init_f (volatile immap_t * im)
  43. {
  44. __be32 acr_mask =
  45. #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  46. ACR_PIPE_DEP |
  47. #endif
  48. #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  49. ACR_RPTCNT |
  50. #endif
  51. #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
  52. ACR_APARK |
  53. #endif
  54. #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
  55. ACR_PARKM |
  56. #endif
  57. 0;
  58. __be32 acr_val =
  59. #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  60. (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  61. #endif
  62. #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  63. (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  64. #endif
  65. #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
  66. (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
  67. #endif
  68. #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
  69. (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
  70. #endif
  71. 0;
  72. __be32 spcr_mask =
  73. #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  74. SPCR_OPT |
  75. #endif
  76. #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  77. SPCR_TSECEP |
  78. #endif
  79. #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  80. SPCR_TSEC1EP |
  81. #endif
  82. #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  83. SPCR_TSEC2EP |
  84. #endif
  85. 0;
  86. __be32 spcr_val =
  87. #ifdef CONFIG_SYS_SPCR_OPT
  88. (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
  89. #endif
  90. #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  91. (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
  92. #endif
  93. #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  94. (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
  95. #endif
  96. #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  97. (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
  98. #endif
  99. 0;
  100. __be32 sccr_mask =
  101. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  102. SCCR_ENCCM |
  103. #endif
  104. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  105. SCCR_PCICM |
  106. #endif
  107. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  108. SCCR_PCIEXP1CM |
  109. #endif
  110. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  111. SCCR_PCIEXP2CM |
  112. #endif
  113. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  114. SCCR_TSECCM |
  115. #endif
  116. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  117. SCCR_TSEC1CM |
  118. #endif
  119. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  120. SCCR_TSEC2CM |
  121. #endif
  122. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  123. SCCR_TSEC1ON |
  124. #endif
  125. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  126. SCCR_TSEC2ON |
  127. #endif
  128. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  129. SCCR_USBMPHCM |
  130. #endif
  131. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  132. SCCR_USBDRCM |
  133. #endif
  134. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  135. SCCR_SATACM |
  136. #endif
  137. 0;
  138. __be32 sccr_val =
  139. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  140. (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  141. #endif
  142. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  143. (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
  144. #endif
  145. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  146. (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
  147. #endif
  148. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  149. (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
  150. #endif
  151. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  152. (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
  153. #endif
  154. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  155. (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
  156. #endif
  157. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  158. (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
  159. #endif
  160. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  161. (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
  162. #endif
  163. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  164. (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
  165. #endif
  166. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  167. (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
  168. #endif
  169. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  170. (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
  171. #endif
  172. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  173. (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
  174. #endif
  175. 0;
  176. __be32 lcrr_mask =
  177. #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
  178. LCRR_DBYP |
  179. #endif
  180. #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
  181. LCRR_EADC |
  182. #endif
  183. #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
  184. LCRR_CLKDIV |
  185. #endif
  186. 0;
  187. __be32 lcrr_val =
  188. #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
  189. CONFIG_SYS_LCRR_DBYP |
  190. #endif
  191. #ifdef CONFIG_SYS_LCRR_EADC
  192. CONFIG_SYS_LCRR_EADC |
  193. #endif
  194. #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
  195. CONFIG_SYS_LCRR_CLKDIV |
  196. #endif
  197. 0;
  198. /* Pointer is writable since we allocated a register for it */
  199. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  200. /* Clear initial global data */
  201. memset ((void *) gd, 0, sizeof (gd_t));
  202. /* system performance tweaking */
  203. clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
  204. clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
  205. clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
  206. /* RSR - Reset Status Register - clear all status (4.6.1.3) */
  207. gd->arch.reset_status = __raw_readl(&im->reset.rsr);
  208. __raw_writel(~(RSR_RES), &im->reset.rsr);
  209. /* AER - Arbiter Event Register - store status */
  210. gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
  211. gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
  212. /*
  213. * RMR - Reset Mode Register
  214. * contains checkstop reset enable (4.6.1.4)
  215. */
  216. __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
  217. /* LCRR - Clock Ratio Register (10.3.1.16)
  218. * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
  219. */
  220. clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
  221. __raw_readl(&im->im_lbc.lcrr);
  222. isync();
  223. /* Enable Time Base & Decrementer ( so we will have udelay() )*/
  224. setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
  225. /* System General Purpose Register */
  226. #ifdef CONFIG_SYS_SICRH
  227. #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
  228. /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
  229. __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
  230. &im->sysconf.sicrh);
  231. #else
  232. __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
  233. #endif
  234. #endif
  235. #ifdef CONFIG_SYS_SICRL
  236. __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
  237. #endif
  238. #ifdef CONFIG_SYS_GPR1
  239. __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
  240. #endif
  241. #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
  242. __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
  243. #endif
  244. #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
  245. __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
  246. #endif
  247. #ifdef CONFIG_QE
  248. /* Config QE ioports */
  249. config_qe_ioports();
  250. #endif
  251. /* Set up preliminary BR/OR regs */
  252. init_early_memctl_regs();
  253. /* Local Access window setup */
  254. #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
  255. im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
  256. im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
  257. #else
  258. #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
  259. #endif
  260. #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
  261. im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
  262. im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
  263. #endif
  264. #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  265. im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
  266. im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
  267. #endif
  268. #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
  269. im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
  270. im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
  271. #endif
  272. #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
  273. im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
  274. im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
  275. #endif
  276. #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
  277. im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
  278. im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
  279. #endif
  280. #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
  281. im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
  282. im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
  283. #endif
  284. #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
  285. im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
  286. im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
  287. #endif
  288. #ifdef CONFIG_SYS_GPIO1_PRELIM
  289. im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
  290. im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
  291. #endif
  292. #ifdef CONFIG_SYS_GPIO2_PRELIM
  293. im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
  294. im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
  295. #endif
  296. #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
  297. uint32_t temp;
  298. struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
  299. /* Configure interface. */
  300. setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
  301. /* Wait for clock to stabilize */
  302. do {
  303. temp = __raw_readl(&ehci->control);
  304. udelay(1000);
  305. } while (!(temp & PHY_CLK_VALID));
  306. #endif
  307. }
  308. int cpu_init_r (void)
  309. {
  310. #ifdef CONFIG_QE
  311. uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
  312. qe_init(qe_base);
  313. qe_reset();
  314. #endif
  315. return 0;
  316. }
  317. /*
  318. * Print out the bus arbiter event
  319. */
  320. #if defined(CONFIG_DISPLAY_AER_FULL)
  321. static int print_83xx_arb_event(int force)
  322. {
  323. static char* event[] = {
  324. "Address Time Out",
  325. "Data Time Out",
  326. "Address Only Transfer Type",
  327. "External Control Word Transfer Type",
  328. "Reserved Transfer Type",
  329. "Transfer Error",
  330. "reserved",
  331. "reserved"
  332. };
  333. static char* master[] = {
  334. "e300 Core Data Transaction",
  335. "reserved",
  336. "e300 Core Instruction Fetch",
  337. "reserved",
  338. "TSEC1",
  339. "TSEC2",
  340. "USB MPH",
  341. "USB DR",
  342. "Encryption Core",
  343. "I2C Boot Sequencer",
  344. "JTAG",
  345. "reserved",
  346. "eSDHC",
  347. "PCI1",
  348. "PCI2",
  349. "DMA",
  350. "QUICC Engine 00",
  351. "QUICC Engine 01",
  352. "QUICC Engine 10",
  353. "QUICC Engine 11",
  354. "reserved",
  355. "reserved",
  356. "reserved",
  357. "reserved",
  358. "SATA1",
  359. "SATA2",
  360. "SATA3",
  361. "SATA4",
  362. "reserved",
  363. "PCI Express 1",
  364. "PCI Express 2",
  365. "TDM-DMAC"
  366. };
  367. static char *transfer[] = {
  368. "Address-only, Clean Block",
  369. "Address-only, lwarx reservation set",
  370. "Single-beat or Burst write",
  371. "reserved",
  372. "Address-only, Flush Block",
  373. "reserved",
  374. "Burst write",
  375. "reserved",
  376. "Address-only, sync",
  377. "Address-only, tlbsync",
  378. "Single-beat or Burst read",
  379. "Single-beat or Burst read",
  380. "Address-only, Kill Block",
  381. "Address-only, icbi",
  382. "Burst read",
  383. "reserved",
  384. "Address-only, eieio",
  385. "reserved",
  386. "Single-beat write",
  387. "reserved",
  388. "ecowx - Illegal single-beat write",
  389. "reserved",
  390. "reserved",
  391. "reserved",
  392. "Address-only, TLB Invalidate",
  393. "reserved",
  394. "Single-beat or Burst read",
  395. "reserved",
  396. "eciwx - Illegal single-beat read",
  397. "reserved",
  398. "Burst read",
  399. "reserved"
  400. };
  401. int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
  402. >> AEATR_EVENT_SHIFT;
  403. int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
  404. >> AEATR_MSTR_ID_SHIFT;
  405. int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
  406. >> AEATR_TBST_SHIFT;
  407. int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
  408. >> AEATR_TSIZE_SHIFT;
  409. int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
  410. >> AEATR_TTYPE_SHIFT;
  411. if (!force && !gd->arch.arbiter_event_address)
  412. return 0;
  413. puts("Arbiter Event Status:\n");
  414. printf(" Event Address: 0x%08lX\n",
  415. gd->arch.arbiter_event_address);
  416. printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
  417. printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
  418. printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
  419. tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
  420. printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
  421. return gd->arch.arbiter_event_address;
  422. }
  423. #elif defined(CONFIG_DISPLAY_AER_BRIEF)
  424. static int print_83xx_arb_event(int force)
  425. {
  426. if (!force && !gd->arch.arbiter_event_address)
  427. return 0;
  428. printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
  429. gd->arch.arbiter_event_attributes,
  430. gd->arch.arbiter_event_address);
  431. return gd->arch.arbiter_event_address;
  432. }
  433. #endif /* CONFIG_DISPLAY_AER_xxxx */
  434. /*
  435. * Figure out the cause of the reset
  436. */
  437. int prt_83xx_rsr(void)
  438. {
  439. static struct {
  440. ulong mask;
  441. char *desc;
  442. } bits[] = {
  443. {
  444. RSR_SWSR, "Software Soft"}, {
  445. RSR_SWHR, "Software Hard"}, {
  446. RSR_JSRS, "JTAG Soft"}, {
  447. RSR_CSHR, "Check Stop"}, {
  448. RSR_SWRS, "Software Watchdog"}, {
  449. RSR_BMRS, "Bus Monitor"}, {
  450. RSR_SRS, "External/Internal Soft"}, {
  451. RSR_HRS, "External/Internal Hard"}
  452. };
  453. static int n = sizeof bits / sizeof bits[0];
  454. ulong rsr = gd->arch.reset_status;
  455. int i;
  456. char *sep;
  457. puts("Reset Status:");
  458. sep = " ";
  459. for (i = 0; i < n; i++)
  460. if (rsr & bits[i].mask) {
  461. printf("%s%s", sep, bits[i].desc);
  462. sep = ", ";
  463. }
  464. puts("\n");
  465. #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
  466. print_83xx_arb_event(rsr & RSR_BMRS);
  467. #endif
  468. puts("\n");
  469. return 0;
  470. }