stm32mp1_ram.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <ram.h>
  10. #include <regmap.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include "stm32mp1_ddr.h"
  14. static const char *const clkname[] = {
  15. "ddrc1",
  16. "ddrc2",
  17. "ddrcapb",
  18. "ddrphycapb",
  19. "ddrphyc" /* LAST clock => used for get_rate() */
  20. };
  21. int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
  22. {
  23. unsigned long ddrphy_clk;
  24. unsigned long ddr_clk;
  25. struct clk clk;
  26. int ret;
  27. unsigned int idx;
  28. for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
  29. ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
  30. if (!ret)
  31. ret = clk_enable(&clk);
  32. if (ret) {
  33. printf("error for %s : %d\n", clkname[idx], ret);
  34. return ret;
  35. }
  36. }
  37. priv->clk = clk;
  38. ddrphy_clk = clk_get_rate(&priv->clk);
  39. debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
  40. mem_speed, (u32)(ddrphy_clk / 1000));
  41. /* max 10% frequency delta */
  42. ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
  43. if (ddr_clk > (mem_speed * 100)) {
  44. pr_err("DDR expected freq %d kHz, current is %d kHz\n",
  45. mem_speed, (u32)(ddrphy_clk / 1000));
  46. return -EINVAL;
  47. }
  48. return 0;
  49. }
  50. static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
  51. {
  52. struct ddr_info *priv = dev_get_priv(dev);
  53. int ret;
  54. unsigned int idx;
  55. struct clk axidcg;
  56. struct stm32mp1_ddr_config config;
  57. #define PARAM(x, y, z) \
  58. { .name = x, \
  59. .offset = offsetof(struct stm32mp1_ddr_config, y), \
  60. .size = sizeof(config.y) / sizeof(u32), \
  61. .present = z, \
  62. }
  63. #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
  64. #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
  65. #define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
  66. const struct {
  67. const char *name; /* name in DT */
  68. const u32 offset; /* offset in config struct */
  69. const u32 size; /* size of parameters */
  70. bool * const present; /* presence indication for opt */
  71. } param[] = {
  72. CTL_PARAM(reg),
  73. CTL_PARAM(timing),
  74. CTL_PARAM(map),
  75. CTL_PARAM(perf),
  76. PHY_PARAM(reg),
  77. PHY_PARAM(timing),
  78. PHY_PARAM_OPT(cal)
  79. };
  80. config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
  81. config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
  82. config.info.name = dev_read_string(dev, "st,mem-name");
  83. if (!config.info.name) {
  84. debug("%s: no st,mem-name\n", __func__);
  85. return -EINVAL;
  86. }
  87. printf("RAM: %s\n", config.info.name);
  88. for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
  89. ret = dev_read_u32_array(dev, param[idx].name,
  90. (void *)((u32)&config +
  91. param[idx].offset),
  92. param[idx].size);
  93. debug("%s: %s[0x%x] = %d\n", __func__,
  94. param[idx].name, param[idx].size, ret);
  95. if (ret &&
  96. (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
  97. pr_err("%s: Cannot read %s, error=%d\n",
  98. __func__, param[idx].name, ret);
  99. return -EINVAL;
  100. }
  101. if (param[idx].present) {
  102. /* save presence of optional parameters */
  103. *param[idx].present = true;
  104. if (ret == -FDT_ERR_NOTFOUND) {
  105. *param[idx].present = false;
  106. #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
  107. /* reset values if used later */
  108. memset((void *)((u32)&config +
  109. param[idx].offset),
  110. 0, param[idx].size * sizeof(u32));
  111. #endif
  112. }
  113. }
  114. }
  115. ret = clk_get_by_name(dev, "axidcg", &axidcg);
  116. if (ret) {
  117. debug("%s: Cannot found axidcg\n", __func__);
  118. return -EINVAL;
  119. }
  120. clk_disable(&axidcg); /* disable clock gating during init */
  121. stm32mp1_ddr_init(priv, &config);
  122. clk_enable(&axidcg); /* enable clock gating */
  123. /* check size */
  124. debug("%s : get_ram_size(%x, %x)\n", __func__,
  125. (u32)priv->info.base, (u32)STM32_DDR_SIZE);
  126. priv->info.size = get_ram_size((long *)priv->info.base,
  127. STM32_DDR_SIZE);
  128. debug("%s : %x\n", __func__, (u32)priv->info.size);
  129. /* check memory access for all memory */
  130. if (config.info.size != priv->info.size) {
  131. printf("DDR invalid size : 0x%x, expected 0x%x\n",
  132. priv->info.size, config.info.size);
  133. return -EINVAL;
  134. }
  135. return 0;
  136. }
  137. static int stm32mp1_ddr_probe(struct udevice *dev)
  138. {
  139. struct ddr_info *priv = dev_get_priv(dev);
  140. struct regmap *map;
  141. int ret;
  142. debug("STM32MP1 DDR probe\n");
  143. priv->dev = dev;
  144. ret = regmap_init_mem(dev_ofnode(dev), &map);
  145. if (ret)
  146. return ret;
  147. priv->ctl = regmap_get_range(map, 0);
  148. priv->phy = regmap_get_range(map, 1);
  149. priv->rcc = STM32_RCC_BASE;
  150. priv->info.base = STM32_DDR_BASE;
  151. #if !defined(CONFIG_STM32MP1_TRUSTED) && \
  152. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  153. priv->info.size = 0;
  154. return stm32mp1_ddr_setup(dev);
  155. #else
  156. priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
  157. return 0;
  158. #endif
  159. }
  160. static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
  161. {
  162. struct ddr_info *priv = dev_get_priv(dev);
  163. *info = priv->info;
  164. return 0;
  165. }
  166. static struct ram_ops stm32mp1_ddr_ops = {
  167. .get_info = stm32mp1_ddr_get_info,
  168. };
  169. static const struct udevice_id stm32mp1_ddr_ids[] = {
  170. { .compatible = "st,stm32mp1-ddr" },
  171. { }
  172. };
  173. U_BOOT_DRIVER(ddr_stm32mp1) = {
  174. .name = "stm32mp1_ddr",
  175. .id = UCLASS_RAM,
  176. .of_match = stm32mp1_ddr_ids,
  177. .ops = &stm32mp1_ddr_ops,
  178. .probe = stm32mp1_ddr_probe,
  179. .priv_auto_alloc_size = sizeof(struct ddr_info),
  180. };