stm32mp1_interactive.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <console.h>
  7. #include <cli.h>
  8. #include <clk.h>
  9. #include <malloc.h>
  10. #include <ram.h>
  11. #include <reset.h>
  12. #include "stm32mp1_ddr.h"
  13. #include "stm32mp1_tests.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. enum ddr_command {
  16. DDR_CMD_HELP,
  17. DDR_CMD_INFO,
  18. DDR_CMD_FREQ,
  19. DDR_CMD_RESET,
  20. DDR_CMD_PARAM,
  21. DDR_CMD_PRINT,
  22. DDR_CMD_EDIT,
  23. DDR_CMD_STEP,
  24. DDR_CMD_NEXT,
  25. DDR_CMD_GO,
  26. DDR_CMD_TEST,
  27. DDR_CMD_TUNING,
  28. DDR_CMD_UNKNOWN,
  29. };
  30. const char *step_str[] = {
  31. [STEP_DDR_RESET] = "DDR_RESET",
  32. [STEP_CTL_INIT] = "DDR_CTRL_INIT_DONE",
  33. [STEP_PHY_INIT] = "DDR PHY_INIT_DONE",
  34. [STEP_DDR_READY] = "DDR_READY",
  35. [STEP_RUN] = "RUN"
  36. };
  37. enum ddr_command stm32mp1_get_command(char *cmd, int argc)
  38. {
  39. const char *cmd_string[DDR_CMD_UNKNOWN] = {
  40. [DDR_CMD_HELP] = "help",
  41. [DDR_CMD_INFO] = "info",
  42. [DDR_CMD_FREQ] = "freq",
  43. [DDR_CMD_RESET] = "reset",
  44. [DDR_CMD_PARAM] = "param",
  45. [DDR_CMD_PRINT] = "print",
  46. [DDR_CMD_EDIT] = "edit",
  47. [DDR_CMD_STEP] = "step",
  48. [DDR_CMD_NEXT] = "next",
  49. [DDR_CMD_GO] = "go",
  50. #ifdef CONFIG_STM32MP1_DDR_TESTS
  51. [DDR_CMD_TEST] = "test",
  52. #endif
  53. #ifdef CONFIG_STM32MP1_DDR_TUNING
  54. [DDR_CMD_TUNING] = "tuning",
  55. #endif
  56. };
  57. /* min and max number of argument */
  58. const char cmd_arg[DDR_CMD_UNKNOWN][2] = {
  59. [DDR_CMD_HELP] = { 0, 0 },
  60. [DDR_CMD_INFO] = { 0, 255 },
  61. [DDR_CMD_FREQ] = { 0, 1 },
  62. [DDR_CMD_RESET] = { 0, 0 },
  63. [DDR_CMD_PARAM] = { 0, 2 },
  64. [DDR_CMD_PRINT] = { 0, 1 },
  65. [DDR_CMD_EDIT] = { 2, 2 },
  66. [DDR_CMD_STEP] = { 0, 1 },
  67. [DDR_CMD_NEXT] = { 0, 0 },
  68. [DDR_CMD_GO] = { 0, 0 },
  69. #ifdef CONFIG_STM32MP1_DDR_TESTS
  70. [DDR_CMD_TEST] = { 0, 255 },
  71. #endif
  72. #ifdef CONFIG_STM32MP1_DDR_TUNING
  73. [DDR_CMD_TUNING] = { 0, 255 },
  74. #endif
  75. };
  76. int i;
  77. for (i = 0; i < DDR_CMD_UNKNOWN; i++)
  78. if (!strcmp(cmd, cmd_string[i])) {
  79. if (argc - 1 < cmd_arg[i][0]) {
  80. printf("no enought argument (min=%d)\n",
  81. cmd_arg[i][0]);
  82. return DDR_CMD_UNKNOWN;
  83. } else if (argc - 1 > cmd_arg[i][1]) {
  84. printf("too many argument (max=%d)\n",
  85. cmd_arg[i][1]);
  86. return DDR_CMD_UNKNOWN;
  87. } else {
  88. return i;
  89. }
  90. }
  91. printf("unknown command %s\n", cmd);
  92. return DDR_CMD_UNKNOWN;
  93. }
  94. static void stm32mp1_do_usage(void)
  95. {
  96. const char *usage = {
  97. "commands:\n\n"
  98. "help displays help\n"
  99. "info displays DDR information\n"
  100. "info <param> <val> changes DDR information\n"
  101. " with <param> = step, name, size, speed or cal\n"
  102. "freq displays the DDR PHY frequency in kHz\n"
  103. "freq <freq> changes the DDR PHY frequency\n"
  104. "param [type|reg] prints input parameters\n"
  105. "param <reg> <val> edits parameters in step 0\n"
  106. "print [type|reg] dumps registers\n"
  107. "edit <reg> <val> modifies one register\n"
  108. "step lists the available step\n"
  109. "step <n> go to the step <n>\n"
  110. "next goes to the next step\n"
  111. "go continues the U-Boot SPL execution\n"
  112. "reset reboots machine\n"
  113. #ifdef CONFIG_STM32MP1_DDR_TESTS
  114. "test [help] | <n> [...] lists (with help) or executes test <n>\n"
  115. #endif
  116. #ifdef CONFIG_STM32MP1_DDR_TUNING
  117. "tuning [help] | <n> [...] lists (with help) or execute tuning <n>\n"
  118. #endif
  119. "\nwith for [type|reg]:\n"
  120. " all registers if absent\n"
  121. " <type> = ctl, phy\n"
  122. " or one category (static, timing, map, perf, cal, dyn)\n"
  123. " <reg> = name of the register\n"
  124. };
  125. puts(usage);
  126. }
  127. static bool stm32mp1_check_step(enum stm32mp1_ddr_interact_step step,
  128. enum stm32mp1_ddr_interact_step expected)
  129. {
  130. if (step != expected) {
  131. printf("invalid step %d:%s expecting %d:%s\n",
  132. step, step_str[step],
  133. expected,
  134. step_str[expected]);
  135. return false;
  136. }
  137. return true;
  138. }
  139. static void stm32mp1_do_info(struct ddr_info *priv,
  140. struct stm32mp1_ddr_config *config,
  141. enum stm32mp1_ddr_interact_step step,
  142. int argc, char * const argv[])
  143. {
  144. unsigned long value;
  145. static char *ddr_name;
  146. if (argc == 1) {
  147. printf("step = %d : %s\n", step, step_str[step]);
  148. printf("name = %s\n", config->info.name);
  149. printf("size = 0x%x\n", config->info.size);
  150. printf("speed = %d kHz\n", config->info.speed);
  151. printf("cal = %d\n", config->p_cal_present);
  152. return;
  153. }
  154. if (argc < 3) {
  155. printf("no enought parameter\n");
  156. return;
  157. }
  158. if (!strcmp(argv[1], "name")) {
  159. u32 i, name_len = 0;
  160. for (i = 2; i < argc; i++)
  161. name_len += strlen(argv[i]) + 1;
  162. if (ddr_name)
  163. free(ddr_name);
  164. ddr_name = malloc(name_len);
  165. config->info.name = ddr_name;
  166. if (!ddr_name) {
  167. printf("alloc error, length %d\n", name_len);
  168. return;
  169. }
  170. strcpy(ddr_name, argv[2]);
  171. for (i = 3; i < argc; i++) {
  172. strcat(ddr_name, " ");
  173. strcat(ddr_name, argv[i]);
  174. }
  175. printf("name = %s\n", ddr_name);
  176. return;
  177. }
  178. if (!strcmp(argv[1], "size")) {
  179. if (strict_strtoul(argv[2], 16, &value) < 0) {
  180. printf("invalid value %s\n", argv[2]);
  181. } else {
  182. config->info.size = value;
  183. printf("size = 0x%x\n", config->info.size);
  184. }
  185. return;
  186. }
  187. if (!strcmp(argv[1], "speed")) {
  188. if (strict_strtoul(argv[2], 10, &value) < 0) {
  189. printf("invalid value %s\n", argv[2]);
  190. } else {
  191. config->info.speed = value;
  192. printf("speed = %d kHz\n", config->info.speed);
  193. value = clk_get_rate(&priv->clk);
  194. printf("DDRPHY = %ld kHz\n", value / 1000);
  195. }
  196. return;
  197. }
  198. if (!strcmp(argv[1], "cal")) {
  199. if (strict_strtoul(argv[2], 10, &value) < 0 ||
  200. (value != 0 && value != 1)) {
  201. printf("invalid value %s\n", argv[2]);
  202. } else {
  203. config->p_cal_present = value;
  204. printf("cal = %d\n", config->p_cal_present);
  205. }
  206. return;
  207. }
  208. printf("argument %s invalid\n", argv[1]);
  209. }
  210. static bool stm32mp1_do_freq(struct ddr_info *priv,
  211. int argc, char * const argv[])
  212. {
  213. unsigned long ddrphy_clk;
  214. if (argc == 2) {
  215. if (strict_strtoul(argv[1], 0, &ddrphy_clk) < 0) {
  216. printf("invalid argument %s", argv[1]);
  217. return false;
  218. }
  219. if (clk_set_rate(&priv->clk, ddrphy_clk * 1000)) {
  220. printf("ERROR: update failed!\n");
  221. return false;
  222. }
  223. }
  224. ddrphy_clk = clk_get_rate(&priv->clk);
  225. printf("DDRPHY = %ld kHz\n", ddrphy_clk / 1000);
  226. if (argc == 2)
  227. return true;
  228. return false;
  229. }
  230. static void stm32mp1_do_param(enum stm32mp1_ddr_interact_step step,
  231. const struct stm32mp1_ddr_config *config,
  232. int argc, char * const argv[])
  233. {
  234. switch (argc) {
  235. case 1:
  236. stm32mp1_dump_param(config, NULL);
  237. break;
  238. case 2:
  239. if (stm32mp1_dump_param(config, argv[1]))
  240. printf("invalid argument %s\n",
  241. argv[1]);
  242. break;
  243. case 3:
  244. if (!stm32mp1_check_step(step, STEP_DDR_RESET))
  245. return;
  246. stm32mp1_edit_param(config, argv[1], argv[2]);
  247. break;
  248. }
  249. }
  250. static void stm32mp1_do_print(struct ddr_info *priv,
  251. int argc, char * const argv[])
  252. {
  253. switch (argc) {
  254. case 1:
  255. stm32mp1_dump_reg(priv, NULL);
  256. break;
  257. case 2:
  258. if (stm32mp1_dump_reg(priv, argv[1]))
  259. printf("invalid argument %s\n",
  260. argv[1]);
  261. break;
  262. }
  263. }
  264. static int stm32mp1_do_step(enum stm32mp1_ddr_interact_step step,
  265. int argc, char * const argv[])
  266. {
  267. int i;
  268. unsigned long value;
  269. switch (argc) {
  270. case 1:
  271. for (i = 0; i < ARRAY_SIZE(step_str); i++)
  272. printf("%d:%s\n", i, step_str[i]);
  273. break;
  274. case 2:
  275. if ((strict_strtoul(argv[1], 0,
  276. &value) < 0) ||
  277. value >= ARRAY_SIZE(step_str)) {
  278. printf("invalid argument %s\n",
  279. argv[1]);
  280. goto end;
  281. }
  282. if (value != STEP_DDR_RESET &&
  283. value <= step) {
  284. printf("invalid target %d:%s, current step is %d:%s\n",
  285. (int)value, step_str[value],
  286. step, step_str[step]);
  287. goto end;
  288. }
  289. printf("step to %d:%s\n",
  290. (int)value, step_str[value]);
  291. return (int)value;
  292. };
  293. end:
  294. return step;
  295. }
  296. #if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING)
  297. static const char * const s_result[] = {
  298. [TEST_PASSED] = "Pass",
  299. [TEST_FAILED] = "Failed",
  300. [TEST_ERROR] = "Error"
  301. };
  302. static void stm32mp1_ddr_subcmd(struct ddr_info *priv,
  303. int argc, char *argv[],
  304. const struct test_desc array[],
  305. const int array_nb)
  306. {
  307. int i;
  308. unsigned long value;
  309. int result;
  310. char string[50] = "";
  311. if (argc == 1) {
  312. printf("%s:%d\n", argv[0], array_nb);
  313. for (i = 0; i < array_nb; i++)
  314. printf("%d:%s:%s\n",
  315. i, array[i].name, array[i].usage);
  316. return;
  317. }
  318. if (argc > 1 && !strcmp(argv[1], "help")) {
  319. printf("%s:%d\n", argv[0], array_nb);
  320. for (i = 0; i < array_nb; i++)
  321. printf("%d:%s:%s:%s\n", i,
  322. array[i].name, array[i].usage, array[i].help);
  323. return;
  324. }
  325. if ((strict_strtoul(argv[1], 0, &value) < 0) ||
  326. value >= array_nb) {
  327. sprintf(string, "invalid argument %s",
  328. argv[1]);
  329. result = TEST_FAILED;
  330. goto end;
  331. }
  332. if (argc > (array[value].max_args + 2)) {
  333. sprintf(string, "invalid nb of args %d, max %d",
  334. argc - 2, array[value].max_args);
  335. result = TEST_FAILED;
  336. goto end;
  337. }
  338. printf("execute %d:%s\n", (int)value, array[value].name);
  339. clear_ctrlc();
  340. result = array[value].fct(priv->ctl, priv->phy,
  341. string, argc - 2, &argv[2]);
  342. end:
  343. printf("Result: %s [%s]\n", s_result[result], string);
  344. }
  345. #endif
  346. bool stm32mp1_ddr_interactive(void *priv,
  347. enum stm32mp1_ddr_interact_step step,
  348. const struct stm32mp1_ddr_config *config)
  349. {
  350. char buffer[CONFIG_SYS_CBSIZE];
  351. char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
  352. int argc;
  353. static int next_step = -1;
  354. if (next_step < 0 && step == STEP_DDR_RESET) {
  355. #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE_FORCE
  356. gd->flags &= ~(GD_FLG_SILENT |
  357. GD_FLG_DISABLE_CONSOLE);
  358. next_step = STEP_DDR_RESET;
  359. #else
  360. unsigned long start = get_timer(0);
  361. while (1) {
  362. if (tstc() && (getc() == 'd')) {
  363. next_step = STEP_DDR_RESET;
  364. break;
  365. }
  366. if (get_timer(start) > 100)
  367. break;
  368. }
  369. #endif
  370. }
  371. debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
  372. if (next_step < 0)
  373. return false;
  374. if (step < 0 || step > ARRAY_SIZE(step_str)) {
  375. printf("** step %d ** INVALID\n", step);
  376. return false;
  377. }
  378. printf("%d:%s\n", step, step_str[step]);
  379. if (next_step > step)
  380. return false;
  381. while (next_step == step) {
  382. cli_readline_into_buffer("DDR>", buffer, 0);
  383. argc = cli_simple_parse_line(buffer, argv);
  384. if (!argc)
  385. continue;
  386. switch (stm32mp1_get_command(argv[0], argc)) {
  387. case DDR_CMD_HELP:
  388. stm32mp1_do_usage();
  389. break;
  390. case DDR_CMD_INFO:
  391. stm32mp1_do_info(priv,
  392. (struct stm32mp1_ddr_config *)config,
  393. step, argc, argv);
  394. break;
  395. case DDR_CMD_FREQ:
  396. if (stm32mp1_do_freq(priv, argc, argv))
  397. next_step = STEP_DDR_RESET;
  398. break;
  399. case DDR_CMD_RESET:
  400. do_reset(NULL, 0, 0, NULL);
  401. break;
  402. case DDR_CMD_PARAM:
  403. stm32mp1_do_param(step, config, argc, argv);
  404. break;
  405. case DDR_CMD_PRINT:
  406. stm32mp1_do_print(priv, argc, argv);
  407. break;
  408. case DDR_CMD_EDIT:
  409. stm32mp1_edit_reg(priv, argv[1], argv[2]);
  410. break;
  411. case DDR_CMD_GO:
  412. next_step = STEP_RUN;
  413. break;
  414. case DDR_CMD_NEXT:
  415. next_step = step + 1;
  416. break;
  417. case DDR_CMD_STEP:
  418. next_step = stm32mp1_do_step(step, argc, argv);
  419. break;
  420. #ifdef CONFIG_STM32MP1_DDR_TESTS
  421. case DDR_CMD_TEST:
  422. if (!stm32mp1_check_step(step, STEP_DDR_READY))
  423. continue;
  424. stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb);
  425. break;
  426. #endif
  427. #ifdef CONFIG_STM32MP1_DDR_TUNING
  428. case DDR_CMD_TUNING:
  429. if (!stm32mp1_check_step(step, STEP_DDR_READY))
  430. continue;
  431. stm32mp1_ddr_subcmd(priv, argc, argv,
  432. tuning, tuning_nb);
  433. break;
  434. #endif
  435. default:
  436. break;
  437. }
  438. }
  439. return next_step == STEP_DDR_RESET;
  440. }