stm32mp1_ddr.h 3.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #ifndef _RAM_STM32MP1_DDR_H
  6. #define _RAM_STM32MP1_DDR_H
  7. enum stm32mp1_ddr_interact_step {
  8. STEP_DDR_RESET,
  9. STEP_CTL_INIT,
  10. STEP_PHY_INIT,
  11. STEP_DDR_READY,
  12. STEP_RUN,
  13. };
  14. /* DDR CTL and DDR PHY REGISTERS */
  15. struct stm32mp1_ddrctl;
  16. struct stm32mp1_ddrphy;
  17. /**
  18. * struct ddr_info
  19. *
  20. * @dev: pointer for the device
  21. * @info: UCLASS RAM information
  22. * @ctl: DDR controleur base address
  23. * @clk: DDR clock
  24. * @phy: DDR PHY base address
  25. * @rcc: rcc base address
  26. */
  27. struct ddr_info {
  28. struct udevice *dev;
  29. struct ram_info info;
  30. struct clk clk;
  31. struct stm32mp1_ddrctl *ctl;
  32. struct stm32mp1_ddrphy *phy;
  33. u32 rcc;
  34. };
  35. struct stm32mp1_ddrctrl_reg {
  36. u32 mstr;
  37. u32 mrctrl0;
  38. u32 mrctrl1;
  39. u32 derateen;
  40. u32 derateint;
  41. u32 pwrctl;
  42. u32 pwrtmg;
  43. u32 hwlpctl;
  44. u32 rfshctl0;
  45. u32 rfshctl3;
  46. u32 crcparctl0;
  47. u32 zqctl0;
  48. u32 dfitmg0;
  49. u32 dfitmg1;
  50. u32 dfilpcfg0;
  51. u32 dfiupd0;
  52. u32 dfiupd1;
  53. u32 dfiupd2;
  54. u32 dfiphymstr;
  55. u32 odtmap;
  56. u32 dbg0;
  57. u32 dbg1;
  58. u32 dbgcmd;
  59. u32 poisoncfg;
  60. u32 pccfg;
  61. };
  62. struct stm32mp1_ddrctrl_timing {
  63. u32 rfshtmg;
  64. u32 dramtmg0;
  65. u32 dramtmg1;
  66. u32 dramtmg2;
  67. u32 dramtmg3;
  68. u32 dramtmg4;
  69. u32 dramtmg5;
  70. u32 dramtmg6;
  71. u32 dramtmg7;
  72. u32 dramtmg8;
  73. u32 dramtmg14;
  74. u32 odtcfg;
  75. };
  76. struct stm32mp1_ddrctrl_map {
  77. u32 addrmap1;
  78. u32 addrmap2;
  79. u32 addrmap3;
  80. u32 addrmap4;
  81. u32 addrmap5;
  82. u32 addrmap6;
  83. u32 addrmap9;
  84. u32 addrmap10;
  85. u32 addrmap11;
  86. };
  87. struct stm32mp1_ddrctrl_perf {
  88. u32 sched;
  89. u32 sched1;
  90. u32 perfhpr1;
  91. u32 perflpr1;
  92. u32 perfwr1;
  93. u32 pcfgr_0;
  94. u32 pcfgw_0;
  95. u32 pcfgqos0_0;
  96. u32 pcfgqos1_0;
  97. u32 pcfgwqos0_0;
  98. u32 pcfgwqos1_0;
  99. u32 pcfgr_1;
  100. u32 pcfgw_1;
  101. u32 pcfgqos0_1;
  102. u32 pcfgqos1_1;
  103. u32 pcfgwqos0_1;
  104. u32 pcfgwqos1_1;
  105. };
  106. struct stm32mp1_ddrphy_reg {
  107. u32 pgcr;
  108. u32 aciocr;
  109. u32 dxccr;
  110. u32 dsgcr;
  111. u32 dcr;
  112. u32 odtcr;
  113. u32 zq0cr1;
  114. u32 dx0gcr;
  115. u32 dx1gcr;
  116. u32 dx2gcr;
  117. u32 dx3gcr;
  118. };
  119. struct stm32mp1_ddrphy_timing {
  120. u32 ptr0;
  121. u32 ptr1;
  122. u32 ptr2;
  123. u32 dtpr0;
  124. u32 dtpr1;
  125. u32 dtpr2;
  126. u32 mr0;
  127. u32 mr1;
  128. u32 mr2;
  129. u32 mr3;
  130. };
  131. struct stm32mp1_ddrphy_cal {
  132. u32 dx0dllcr;
  133. u32 dx0dqtr;
  134. u32 dx0dqstr;
  135. u32 dx1dllcr;
  136. u32 dx1dqtr;
  137. u32 dx1dqstr;
  138. u32 dx2dllcr;
  139. u32 dx2dqtr;
  140. u32 dx2dqstr;
  141. u32 dx3dllcr;
  142. u32 dx3dqtr;
  143. u32 dx3dqstr;
  144. };
  145. struct stm32mp1_ddr_info {
  146. const char *name;
  147. u32 speed; /* in kHZ */
  148. u32 size; /* memory size in byte = col * row * width */
  149. };
  150. struct stm32mp1_ddr_config {
  151. struct stm32mp1_ddr_info info;
  152. struct stm32mp1_ddrctrl_reg c_reg;
  153. struct stm32mp1_ddrctrl_timing c_timing;
  154. struct stm32mp1_ddrctrl_map c_map;
  155. struct stm32mp1_ddrctrl_perf c_perf;
  156. struct stm32mp1_ddrphy_reg p_reg;
  157. struct stm32mp1_ddrphy_timing p_timing;
  158. struct stm32mp1_ddrphy_cal p_cal;
  159. bool p_cal_present;
  160. };
  161. int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
  162. void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
  163. void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
  164. void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
  165. u32 rfshctl3,
  166. u32 pwrctl);
  167. void stm32mp1_ddr_init(
  168. struct ddr_info *priv,
  169. const struct stm32mp1_ddr_config *config);
  170. int stm32mp1_dump_reg(const struct ddr_info *priv,
  171. const char *name);
  172. void stm32mp1_edit_reg(const struct ddr_info *priv,
  173. char *name,
  174. char *string);
  175. int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
  176. const char *name);
  177. void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
  178. char *name,
  179. char *string);
  180. bool stm32mp1_ddr_interactive(
  181. void *priv,
  182. enum stm32mp1_ddr_interact_step step,
  183. const struct stm32mp1_ddr_config *config);
  184. #endif