stm32mp1_ddr.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <ram.h>
  8. #include <reset.h>
  9. #include <timer.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/ddr.h>
  12. #include <linux/iopoll.h>
  13. #include "stm32mp1_ddr.h"
  14. #include "stm32mp1_ddr_regs.h"
  15. #define RCC_DDRITFCR 0xD8
  16. #define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
  17. #define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
  18. #define RCC_DDRITFCR_DDRCORERST (BIT(16))
  19. #define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
  20. #define RCC_DDRITFCR_DPHYRST (BIT(18))
  21. #define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
  22. struct reg_desc {
  23. const char *name;
  24. u16 offset; /* offset for base address */
  25. u8 par_offset; /* offset for parameter array */
  26. };
  27. #define INVALID_OFFSET 0xFF
  28. #define DDRCTL_REG(x, y) \
  29. {#x,\
  30. offsetof(struct stm32mp1_ddrctl, x),\
  31. offsetof(struct y, x)}
  32. #define DDRPHY_REG(x, y) \
  33. {#x,\
  34. offsetof(struct stm32mp1_ddrphy, x),\
  35. offsetof(struct y, x)}
  36. #define DDR_REG_DYN(x) \
  37. {#x,\
  38. offsetof(struct stm32mp1_ddrctl, x),\
  39. INVALID_OFFSET}
  40. #define DDRPHY_REG_DYN(x) \
  41. {#x,\
  42. offsetof(struct stm32mp1_ddrphy, x),\
  43. INVALID_OFFSET}
  44. /***********************************************************
  45. * PARAMETERS: value get from device tree :
  46. * size / order need to be aligned with binding
  47. * modification NOT ALLOWED !!!
  48. ***********************************************************/
  49. #define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
  50. #define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
  51. #define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
  52. #define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
  53. #define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
  54. #define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
  55. #define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
  56. #define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
  57. static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
  58. DDRCTL_REG_REG(mstr),
  59. DDRCTL_REG_REG(mrctrl0),
  60. DDRCTL_REG_REG(mrctrl1),
  61. DDRCTL_REG_REG(derateen),
  62. DDRCTL_REG_REG(derateint),
  63. DDRCTL_REG_REG(pwrctl),
  64. DDRCTL_REG_REG(pwrtmg),
  65. DDRCTL_REG_REG(hwlpctl),
  66. DDRCTL_REG_REG(rfshctl0),
  67. DDRCTL_REG_REG(rfshctl3),
  68. DDRCTL_REG_REG(crcparctl0),
  69. DDRCTL_REG_REG(zqctl0),
  70. DDRCTL_REG_REG(dfitmg0),
  71. DDRCTL_REG_REG(dfitmg1),
  72. DDRCTL_REG_REG(dfilpcfg0),
  73. DDRCTL_REG_REG(dfiupd0),
  74. DDRCTL_REG_REG(dfiupd1),
  75. DDRCTL_REG_REG(dfiupd2),
  76. DDRCTL_REG_REG(dfiphymstr),
  77. DDRCTL_REG_REG(odtmap),
  78. DDRCTL_REG_REG(dbg0),
  79. DDRCTL_REG_REG(dbg1),
  80. DDRCTL_REG_REG(dbgcmd),
  81. DDRCTL_REG_REG(poisoncfg),
  82. DDRCTL_REG_REG(pccfg),
  83. };
  84. #define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
  85. static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
  86. DDRCTL_REG_TIMING(rfshtmg),
  87. DDRCTL_REG_TIMING(dramtmg0),
  88. DDRCTL_REG_TIMING(dramtmg1),
  89. DDRCTL_REG_TIMING(dramtmg2),
  90. DDRCTL_REG_TIMING(dramtmg3),
  91. DDRCTL_REG_TIMING(dramtmg4),
  92. DDRCTL_REG_TIMING(dramtmg5),
  93. DDRCTL_REG_TIMING(dramtmg6),
  94. DDRCTL_REG_TIMING(dramtmg7),
  95. DDRCTL_REG_TIMING(dramtmg8),
  96. DDRCTL_REG_TIMING(dramtmg14),
  97. DDRCTL_REG_TIMING(odtcfg),
  98. };
  99. #define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
  100. static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
  101. DDRCTL_REG_MAP(addrmap1),
  102. DDRCTL_REG_MAP(addrmap2),
  103. DDRCTL_REG_MAP(addrmap3),
  104. DDRCTL_REG_MAP(addrmap4),
  105. DDRCTL_REG_MAP(addrmap5),
  106. DDRCTL_REG_MAP(addrmap6),
  107. DDRCTL_REG_MAP(addrmap9),
  108. DDRCTL_REG_MAP(addrmap10),
  109. DDRCTL_REG_MAP(addrmap11),
  110. };
  111. #define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
  112. static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
  113. DDRCTL_REG_PERF(sched),
  114. DDRCTL_REG_PERF(sched1),
  115. DDRCTL_REG_PERF(perfhpr1),
  116. DDRCTL_REG_PERF(perflpr1),
  117. DDRCTL_REG_PERF(perfwr1),
  118. DDRCTL_REG_PERF(pcfgr_0),
  119. DDRCTL_REG_PERF(pcfgw_0),
  120. DDRCTL_REG_PERF(pcfgqos0_0),
  121. DDRCTL_REG_PERF(pcfgqos1_0),
  122. DDRCTL_REG_PERF(pcfgwqos0_0),
  123. DDRCTL_REG_PERF(pcfgwqos1_0),
  124. DDRCTL_REG_PERF(pcfgr_1),
  125. DDRCTL_REG_PERF(pcfgw_1),
  126. DDRCTL_REG_PERF(pcfgqos0_1),
  127. DDRCTL_REG_PERF(pcfgqos1_1),
  128. DDRCTL_REG_PERF(pcfgwqos0_1),
  129. DDRCTL_REG_PERF(pcfgwqos1_1),
  130. };
  131. #define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
  132. static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
  133. DDRPHY_REG_REG(pgcr),
  134. DDRPHY_REG_REG(aciocr),
  135. DDRPHY_REG_REG(dxccr),
  136. DDRPHY_REG_REG(dsgcr),
  137. DDRPHY_REG_REG(dcr),
  138. DDRPHY_REG_REG(odtcr),
  139. DDRPHY_REG_REG(zq0cr1),
  140. DDRPHY_REG_REG(dx0gcr),
  141. DDRPHY_REG_REG(dx1gcr),
  142. DDRPHY_REG_REG(dx2gcr),
  143. DDRPHY_REG_REG(dx3gcr),
  144. };
  145. #define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
  146. static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
  147. DDRPHY_REG_TIMING(ptr0),
  148. DDRPHY_REG_TIMING(ptr1),
  149. DDRPHY_REG_TIMING(ptr2),
  150. DDRPHY_REG_TIMING(dtpr0),
  151. DDRPHY_REG_TIMING(dtpr1),
  152. DDRPHY_REG_TIMING(dtpr2),
  153. DDRPHY_REG_TIMING(mr0),
  154. DDRPHY_REG_TIMING(mr1),
  155. DDRPHY_REG_TIMING(mr2),
  156. DDRPHY_REG_TIMING(mr3),
  157. };
  158. #define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
  159. static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
  160. DDRPHY_REG_CAL(dx0dllcr),
  161. DDRPHY_REG_CAL(dx0dqtr),
  162. DDRPHY_REG_CAL(dx0dqstr),
  163. DDRPHY_REG_CAL(dx1dllcr),
  164. DDRPHY_REG_CAL(dx1dqtr),
  165. DDRPHY_REG_CAL(dx1dqstr),
  166. DDRPHY_REG_CAL(dx2dllcr),
  167. DDRPHY_REG_CAL(dx2dqtr),
  168. DDRPHY_REG_CAL(dx2dqstr),
  169. DDRPHY_REG_CAL(dx3dllcr),
  170. DDRPHY_REG_CAL(dx3dqtr),
  171. DDRPHY_REG_CAL(dx3dqstr),
  172. };
  173. /**************************************************************
  174. * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
  175. **************************************************************/
  176. #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
  177. static const struct reg_desc ddr_dyn[] = {
  178. DDR_REG_DYN(stat),
  179. DDR_REG_DYN(init0),
  180. DDR_REG_DYN(dfimisc),
  181. DDR_REG_DYN(dfistat),
  182. DDR_REG_DYN(swctl),
  183. DDR_REG_DYN(swstat),
  184. DDR_REG_DYN(pctrl_0),
  185. DDR_REG_DYN(pctrl_1),
  186. };
  187. #define DDR_REG_DYN_SIZE ARRAY_SIZE(ddr_dyn)
  188. static const struct reg_desc ddrphy_dyn[] = {
  189. DDRPHY_REG_DYN(pir),
  190. DDRPHY_REG_DYN(pgsr),
  191. DDRPHY_REG_DYN(zq0sr0),
  192. DDRPHY_REG_DYN(zq0sr1),
  193. DDRPHY_REG_DYN(dx0gsr0),
  194. DDRPHY_REG_DYN(dx0gsr1),
  195. DDRPHY_REG_DYN(dx1gsr0),
  196. DDRPHY_REG_DYN(dx1gsr1),
  197. DDRPHY_REG_DYN(dx2gsr0),
  198. DDRPHY_REG_DYN(dx2gsr1),
  199. DDRPHY_REG_DYN(dx3gsr0),
  200. DDRPHY_REG_DYN(dx3gsr1),
  201. };
  202. #define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
  203. #endif
  204. /*****************************************************************
  205. * REGISTERS ARRAY: used to parse device tree and interactive mode
  206. *****************************************************************/
  207. enum reg_type {
  208. REG_REG,
  209. REG_TIMING,
  210. REG_PERF,
  211. REG_MAP,
  212. REGPHY_REG,
  213. REGPHY_TIMING,
  214. REGPHY_CAL,
  215. #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
  216. /* dynamic registers => managed in driver or not changed,
  217. * can be dumped in interactive mode
  218. */
  219. REG_DYN,
  220. REGPHY_DYN,
  221. #endif
  222. REG_TYPE_NB
  223. };
  224. enum base_type {
  225. DDR_BASE,
  226. DDRPHY_BASE,
  227. NONE_BASE
  228. };
  229. struct ddr_reg_info {
  230. const char *name;
  231. const struct reg_desc *desc;
  232. u8 size;
  233. enum base_type base;
  234. };
  235. #define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
  236. const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
  237. [REG_REG] = {
  238. "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
  239. [REG_TIMING] = {
  240. "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
  241. [REG_PERF] = {
  242. "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
  243. [REG_MAP] = {
  244. "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
  245. [REGPHY_REG] = {
  246. "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
  247. [REGPHY_TIMING] = {
  248. "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
  249. [REGPHY_CAL] = {
  250. "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
  251. #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
  252. [REG_DYN] = {
  253. "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
  254. [REGPHY_DYN] = {
  255. "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
  256. #endif
  257. };
  258. const char *base_name[] = {
  259. [DDR_BASE] = "ctl",
  260. [DDRPHY_BASE] = "phy",
  261. };
  262. static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
  263. {
  264. if (base == DDRPHY_BASE)
  265. return (u32)priv->phy;
  266. else
  267. return (u32)priv->ctl;
  268. }
  269. static void set_reg(const struct ddr_info *priv,
  270. enum reg_type type,
  271. const void *param)
  272. {
  273. unsigned int i;
  274. unsigned int *ptr, value;
  275. enum base_type base = ddr_registers[type].base;
  276. u32 base_addr = get_base_addr(priv, base);
  277. const struct reg_desc *desc = ddr_registers[type].desc;
  278. debug("init %s\n", ddr_registers[type].name);
  279. for (i = 0; i < ddr_registers[type].size; i++) {
  280. ptr = (unsigned int *)(base_addr + desc[i].offset);
  281. if (desc[i].par_offset == INVALID_OFFSET) {
  282. pr_err("invalid parameter offset for %s", desc[i].name);
  283. } else {
  284. value = *((u32 *)((u32)param +
  285. desc[i].par_offset));
  286. writel(value, ptr);
  287. debug("[0x%x] %s= 0x%08x\n",
  288. (u32)ptr, desc[i].name, value);
  289. }
  290. }
  291. }
  292. #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
  293. static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
  294. {
  295. unsigned int *ptr;
  296. ptr = (unsigned int *)(base_addr + desc->offset);
  297. printf("%s= 0x%08x\n", desc->name, readl(ptr));
  298. }
  299. static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
  300. {
  301. unsigned int *ptr;
  302. ptr = (unsigned int *)(par_addr + desc->par_offset);
  303. printf("%s= 0x%08x\n", desc->name, readl(ptr));
  304. }
  305. static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
  306. {
  307. unsigned int i, j;
  308. const struct reg_desc *desc;
  309. for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
  310. desc = ddr_registers[i].desc;
  311. for (j = 0; j < ddr_registers[i].size; j++) {
  312. if (strcmp(name, desc[j].name) == 0) {
  313. *type = i;
  314. return &desc[j];
  315. }
  316. }
  317. }
  318. *type = REG_TYPE_NB;
  319. return NULL;
  320. }
  321. int stm32mp1_dump_reg(const struct ddr_info *priv,
  322. const char *name)
  323. {
  324. unsigned int i, j;
  325. const struct reg_desc *desc;
  326. u32 base_addr;
  327. enum base_type p_base;
  328. enum reg_type type;
  329. const char *p_name;
  330. enum base_type filter = NONE_BASE;
  331. int result = -1;
  332. if (name) {
  333. if (strcmp(name, base_name[DDR_BASE]) == 0)
  334. filter = DDR_BASE;
  335. else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
  336. filter = DDRPHY_BASE;
  337. }
  338. for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
  339. p_base = ddr_registers[i].base;
  340. p_name = ddr_registers[i].name;
  341. if (!name || (filter == p_base || !strcmp(name, p_name))) {
  342. result = 0;
  343. desc = ddr_registers[i].desc;
  344. base_addr = get_base_addr(priv, p_base);
  345. printf("==%s.%s==\n", base_name[p_base], p_name);
  346. for (j = 0; j < ddr_registers[i].size; j++)
  347. stm32mp1_dump_reg_desc(base_addr, &desc[j]);
  348. }
  349. }
  350. if (result) {
  351. desc = found_reg(name, &type);
  352. if (desc) {
  353. p_base = ddr_registers[type].base;
  354. base_addr = get_base_addr(priv, p_base);
  355. stm32mp1_dump_reg_desc(base_addr, desc);
  356. result = 0;
  357. }
  358. }
  359. return result;
  360. }
  361. void stm32mp1_edit_reg(const struct ddr_info *priv,
  362. char *name, char *string)
  363. {
  364. unsigned long *ptr, value;
  365. enum reg_type type;
  366. enum base_type base;
  367. const struct reg_desc *desc;
  368. u32 base_addr;
  369. desc = found_reg(name, &type);
  370. if (!desc) {
  371. printf("%s not found\n", name);
  372. return;
  373. }
  374. if (strict_strtoul(string, 16, &value) < 0) {
  375. printf("invalid value %s\n", string);
  376. return;
  377. }
  378. base = ddr_registers[type].base;
  379. base_addr = get_base_addr(priv, base);
  380. ptr = (unsigned long *)(base_addr + desc->offset);
  381. writel(value, ptr);
  382. printf("%s= 0x%08x\n", desc->name, readl(ptr));
  383. }
  384. static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
  385. enum reg_type type)
  386. {
  387. u32 par_addr = 0x0;
  388. switch (type) {
  389. case REG_REG:
  390. par_addr = (u32)&config->c_reg;
  391. break;
  392. case REG_TIMING:
  393. par_addr = (u32)&config->c_timing;
  394. break;
  395. case REG_PERF:
  396. par_addr = (u32)&config->c_perf;
  397. break;
  398. case REG_MAP:
  399. par_addr = (u32)&config->c_map;
  400. break;
  401. case REGPHY_REG:
  402. par_addr = (u32)&config->p_reg;
  403. break;
  404. case REGPHY_TIMING:
  405. par_addr = (u32)&config->p_timing;
  406. break;
  407. case REGPHY_CAL:
  408. par_addr = (u32)&config->p_cal;
  409. break;
  410. case REG_DYN:
  411. case REGPHY_DYN:
  412. case REG_TYPE_NB:
  413. par_addr = (u32)NULL;
  414. break;
  415. }
  416. return par_addr;
  417. }
  418. int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
  419. const char *name)
  420. {
  421. unsigned int i, j;
  422. const struct reg_desc *desc;
  423. u32 par_addr;
  424. enum base_type p_base;
  425. enum reg_type type;
  426. const char *p_name;
  427. enum base_type filter = NONE_BASE;
  428. int result = -EINVAL;
  429. if (name) {
  430. if (strcmp(name, base_name[DDR_BASE]) == 0)
  431. filter = DDR_BASE;
  432. else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
  433. filter = DDRPHY_BASE;
  434. }
  435. for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
  436. par_addr = get_par_addr(config, i);
  437. if (!par_addr)
  438. continue;
  439. p_base = ddr_registers[i].base;
  440. p_name = ddr_registers[i].name;
  441. if (!name || (filter == p_base || !strcmp(name, p_name))) {
  442. result = 0;
  443. desc = ddr_registers[i].desc;
  444. printf("==%s.%s==\n", base_name[p_base], p_name);
  445. for (j = 0; j < ddr_registers[i].size; j++)
  446. stm32mp1_dump_param_desc(par_addr, &desc[j]);
  447. }
  448. }
  449. if (result) {
  450. desc = found_reg(name, &type);
  451. if (desc) {
  452. par_addr = get_par_addr(config, type);
  453. if (par_addr) {
  454. stm32mp1_dump_param_desc(par_addr, desc);
  455. result = 0;
  456. }
  457. }
  458. }
  459. return result;
  460. }
  461. void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
  462. char *name, char *string)
  463. {
  464. unsigned long *ptr, value;
  465. enum reg_type type;
  466. const struct reg_desc *desc;
  467. u32 par_addr;
  468. desc = found_reg(name, &type);
  469. if (!desc) {
  470. printf("%s not found\n", name);
  471. return;
  472. }
  473. if (strict_strtoul(string, 16, &value) < 0) {
  474. printf("invalid value %s\n", string);
  475. return;
  476. }
  477. par_addr = get_par_addr(config, type);
  478. if (!par_addr) {
  479. printf("no parameter %s\n", name);
  480. return;
  481. }
  482. ptr = (unsigned long *)(par_addr + desc->par_offset);
  483. writel(value, ptr);
  484. printf("%s= 0x%08x\n", desc->name, readl(ptr));
  485. }
  486. #endif
  487. __weak bool stm32mp1_ddr_interactive(void *priv,
  488. enum stm32mp1_ddr_interact_step step,
  489. const struct stm32mp1_ddr_config *config)
  490. {
  491. return false;
  492. }
  493. #define INTERACTIVE(step)\
  494. stm32mp1_ddr_interactive(priv, step, config)
  495. static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
  496. {
  497. u32 pgsr;
  498. int ret;
  499. ret = readl_poll_timeout(&phy->pgsr, pgsr,
  500. pgsr & (DDRPHYC_PGSR_IDONE |
  501. DDRPHYC_PGSR_DTERR |
  502. DDRPHYC_PGSR_DTIERR |
  503. DDRPHYC_PGSR_DFTERR |
  504. DDRPHYC_PGSR_RVERR |
  505. DDRPHYC_PGSR_RVEIRR),
  506. 1000000);
  507. debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
  508. (u32)&phy->pgsr, pgsr, ret);
  509. }
  510. void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
  511. {
  512. pir |= DDRPHYC_PIR_INIT;
  513. writel(pir, &phy->pir);
  514. debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
  515. (u32)&phy->pir, pir, readl(&phy->pir));
  516. /* need to wait 10 configuration clock before start polling */
  517. udelay(10);
  518. /* Wait DRAM initialization and Gate Training Evaluation complete */
  519. ddrphy_idone_wait(phy);
  520. }
  521. /* start quasi dynamic register update */
  522. static void start_sw_done(struct stm32mp1_ddrctl *ctl)
  523. {
  524. clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
  525. }
  526. /* wait quasi dynamic register update */
  527. static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
  528. {
  529. int ret;
  530. u32 swstat;
  531. setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
  532. ret = readl_poll_timeout(&ctl->swstat, swstat,
  533. swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
  534. 1000000);
  535. if (ret)
  536. panic("Timeout initialising DRAM : DDR->swstat = %x\n",
  537. swstat);
  538. debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
  539. }
  540. /* wait quasi dynamic register update */
  541. static void wait_operating_mode(struct ddr_info *priv, int mode)
  542. {
  543. u32 stat, val, mask, val2 = 0, mask2 = 0;
  544. int ret;
  545. mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
  546. val = mode;
  547. /* self-refresh due to software => check also STAT.selfref_type */
  548. if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
  549. mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
  550. val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
  551. } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
  552. /* normal mode: handle also automatic self refresh */
  553. mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
  554. DDRCTRL_STAT_SELFREF_TYPE_MASK;
  555. val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
  556. DDRCTRL_STAT_SELFREF_TYPE_ASR;
  557. }
  558. ret = readl_poll_timeout(&priv->ctl->stat, stat,
  559. ((stat & mask) == val) ||
  560. (mask2 && ((stat & mask2) == val2)),
  561. 1000000);
  562. if (ret)
  563. panic("Timeout DRAM : DDR->stat = %x\n", stat);
  564. debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
  565. }
  566. void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
  567. {
  568. start_sw_done(ctl);
  569. /* quasi-dynamic register update*/
  570. setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
  571. clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
  572. DDRCTRL_PWRCTL_SELFREF_EN);
  573. clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
  574. wait_sw_done_ack(ctl);
  575. }
  576. void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
  577. u32 rfshctl3, u32 pwrctl)
  578. {
  579. start_sw_done(ctl);
  580. if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
  581. clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
  582. if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
  583. setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
  584. if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
  585. setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
  586. setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
  587. wait_sw_done_ack(ctl);
  588. }
  589. /* board-specific DDR power initializations. */
  590. __weak int board_ddr_power_init(enum ddr_type ddr_type)
  591. {
  592. return 0;
  593. }
  594. __maybe_unused
  595. void stm32mp1_ddr_init(struct ddr_info *priv,
  596. const struct stm32mp1_ddr_config *config)
  597. {
  598. u32 pir;
  599. int ret = -EINVAL;
  600. char bus_width;
  601. switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
  602. case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
  603. bus_width = 8;
  604. break;
  605. case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
  606. bus_width = 16;
  607. break;
  608. default:
  609. bus_width = 32;
  610. break;
  611. }
  612. if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
  613. ret = board_ddr_power_init(STM32MP_DDR3);
  614. else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
  615. if (bus_width == 32)
  616. ret = board_ddr_power_init(STM32MP_LPDDR2_32);
  617. else
  618. ret = board_ddr_power_init(STM32MP_LPDDR2_16);
  619. } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
  620. if (bus_width == 32)
  621. ret = board_ddr_power_init(STM32MP_LPDDR3_32);
  622. else
  623. ret = board_ddr_power_init(STM32MP_LPDDR3_16);
  624. }
  625. if (ret)
  626. panic("ddr power init failed\n");
  627. start:
  628. debug("name = %s\n", config->info.name);
  629. debug("speed = %d kHz\n", config->info.speed);
  630. debug("size = 0x%x\n", config->info.size);
  631. /*
  632. * 1. Program the DWC_ddr_umctl2 registers
  633. * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
  634. */
  635. /* Assert All DDR part */
  636. setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
  637. setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
  638. setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
  639. setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
  640. setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
  641. setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
  642. /* 1.2. start CLOCK */
  643. if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
  644. panic("invalid DRAM clock : %d kHz\n",
  645. config->info.speed);
  646. /* 1.3. deassert reset */
  647. /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
  648. clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
  649. clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
  650. /* De-assert presetn once the clocks are active
  651. * and stable via DDRCAPBRST bit
  652. */
  653. clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
  654. /* 1.4. wait 128 cycles to permit initialization of end logic */
  655. udelay(2);
  656. /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
  657. if (INTERACTIVE(STEP_DDR_RESET))
  658. goto start;
  659. /* 1.5. initialize registers ddr_umctl2 */
  660. /* Stop uMCTL2 before PHY is ready */
  661. clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
  662. debug("[0x%08x] dfimisc = 0x%08x\n",
  663. (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
  664. set_reg(priv, REG_REG, &config->c_reg);
  665. set_reg(priv, REG_TIMING, &config->c_timing);
  666. set_reg(priv, REG_MAP, &config->c_map);
  667. /* skip CTRL init, SDRAM init is done by PHY PUBL */
  668. clrsetbits_le32(&priv->ctl->init0,
  669. DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
  670. DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
  671. set_reg(priv, REG_PERF, &config->c_perf);
  672. if (INTERACTIVE(STEP_CTL_INIT))
  673. goto start;
  674. /* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
  675. clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
  676. clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
  677. clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
  678. /* 3. start PHY init by accessing relevant PUBL registers
  679. * (DXGCR, DCR, PTR*, MR*, DTPR*)
  680. */
  681. set_reg(priv, REGPHY_REG, &config->p_reg);
  682. set_reg(priv, REGPHY_TIMING, &config->p_timing);
  683. if (config->p_cal_present)
  684. set_reg(priv, REGPHY_CAL, &config->p_cal);
  685. if (INTERACTIVE(STEP_PHY_INIT))
  686. goto start;
  687. /* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
  688. * Perform DDR PHY DRAM initialization and Gate Training Evaluation
  689. */
  690. ddrphy_idone_wait(priv->phy);
  691. /* 5. Indicate to PUBL that controller performs SDRAM initialization
  692. * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
  693. * DRAM init is done by PHY, init0.skip_dram.init = 1
  694. */
  695. pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
  696. DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
  697. if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
  698. pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
  699. stm32mp1_ddrphy_init(priv->phy, pir);
  700. /* 6. SET DFIMISC.dfi_init_complete_en to 1 */
  701. /* Enable quasi-dynamic register programming*/
  702. start_sw_done(priv->ctl);
  703. setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
  704. wait_sw_done_ack(priv->ctl);
  705. /* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
  706. * by monitoring STAT.operating_mode signal
  707. */
  708. /* wait uMCTL2 ready */
  709. wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
  710. if (config->p_cal_present) {
  711. debug("DDR DQS training skipped.\n");
  712. } else {
  713. debug("DDR DQS training : ");
  714. /* 8. Disable Auto refresh and power down by setting
  715. * - RFSHCTL3.dis_au_refresh = 1
  716. * - PWRCTL.powerdown_en = 0
  717. * - DFIMISC.dfiinit_complete_en = 0
  718. */
  719. stm32mp1_refresh_disable(priv->ctl);
  720. /* 9. Program PUBL PGCR to enable refresh during training and rank to train
  721. * not done => keep the programed value in PGCR
  722. */
  723. /* 10. configure PUBL PIR register to specify which training step to run */
  724. /* warning : RVTRN is not supported by this PUBL */
  725. stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
  726. /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
  727. ddrphy_idone_wait(priv->phy);
  728. /* 12. set back registers in step 8 to the orginal values if desidered */
  729. stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
  730. config->c_reg.pwrctl);
  731. } /* if (config->p_cal_present) */
  732. /* enable uMCTL2 AXI port 0 and 1 */
  733. setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
  734. setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
  735. if (INTERACTIVE(STEP_DDR_READY))
  736. goto start;
  737. }