cache.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  10. #include <asm/cache.h>
  11. static inline unsigned long CACHE_SET(unsigned char cache)
  12. {
  13. if (cache == ICACHE)
  14. return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
  15. >> ICM_CFG_OFF_ISET);
  16. else
  17. return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
  18. >> DCM_CFG_OFF_DSET);
  19. }
  20. static inline unsigned long CACHE_WAY(unsigned char cache)
  21. {
  22. if (cache == ICACHE)
  23. return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
  24. >> ICM_CFG_OFF_IWAY);
  25. else
  26. return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
  27. >> DCM_CFG_OFF_DWAY);
  28. }
  29. static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
  30. {
  31. if (cache == ICACHE)
  32. return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
  33. >> ICM_CFG_OFF_ISZ) - 1);
  34. else
  35. return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
  36. >> DCM_CFG_OFF_DSZ) - 1);
  37. }
  38. #endif
  39. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  40. void invalidate_icache_all(void)
  41. {
  42. unsigned long end, line_size;
  43. line_size = CACHE_LINE_SIZE(ICACHE);
  44. end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
  45. do {
  46. end -= line_size;
  47. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  48. end -= line_size;
  49. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  50. end -= line_size;
  51. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  52. end -= line_size;
  53. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  54. } while (end > 0);
  55. }
  56. void invalidate_icache_range(unsigned long start, unsigned long end)
  57. {
  58. unsigned long line_size;
  59. line_size = CACHE_LINE_SIZE(ICACHE);
  60. while (end > start) {
  61. asm volatile (
  62. "\n\tcctl %0, L1I_VA_INVAL"
  63. :
  64. : "r"(start)
  65. );
  66. start += line_size;
  67. }
  68. }
  69. void icache_enable(void)
  70. {
  71. asm volatile (
  72. "mfsr $p0, $mr8\n\t"
  73. "ori $p0, $p0, 0x01\n\t"
  74. "mtsr $p0, $mr8\n\t"
  75. "isb\n\t"
  76. );
  77. }
  78. void icache_disable(void)
  79. {
  80. asm volatile (
  81. "mfsr $p0, $mr8\n\t"
  82. "li $p1, ~0x01\n\t"
  83. "and $p0, $p0, $p1\n\t"
  84. "mtsr $p0, $mr8\n\t"
  85. "isb\n\t"
  86. );
  87. }
  88. int icache_status(void)
  89. {
  90. int ret;
  91. asm volatile (
  92. "mfsr $p0, $mr8\n\t"
  93. "andi %0, $p0, 0x01\n\t"
  94. : "=r" (ret)
  95. :
  96. : "memory"
  97. );
  98. return ret;
  99. }
  100. #else
  101. void invalidate_icache_all(void)
  102. {
  103. }
  104. void invalidate_icache_range(unsigned long start, unsigned long end)
  105. {
  106. }
  107. void icache_enable(void)
  108. {
  109. }
  110. void icache_disable(void)
  111. {
  112. }
  113. int icache_status(void)
  114. {
  115. return 0;
  116. }
  117. #endif
  118. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  119. void dcache_wbinval_all(void)
  120. {
  121. unsigned long end, line_size;
  122. line_size = CACHE_LINE_SIZE(DCACHE);
  123. end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
  124. do {
  125. end -= line_size;
  126. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  127. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  128. end -= line_size;
  129. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  130. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  131. end -= line_size;
  132. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  133. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  134. end -= line_size;
  135. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  136. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  137. } while (end > 0);
  138. }
  139. void flush_dcache_range(unsigned long start, unsigned long end)
  140. {
  141. unsigned long line_size;
  142. line_size = CACHE_LINE_SIZE(DCACHE);
  143. while (end > start) {
  144. asm volatile (
  145. "\n\tcctl %0, L1D_VA_WB"
  146. "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
  147. );
  148. start += line_size;
  149. }
  150. }
  151. void invalidate_dcache_range(unsigned long start, unsigned long end)
  152. {
  153. unsigned long line_size;
  154. line_size = CACHE_LINE_SIZE(DCACHE);
  155. while (end > start) {
  156. asm volatile (
  157. "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
  158. );
  159. start += line_size;
  160. }
  161. }
  162. void dcache_enable(void)
  163. {
  164. asm volatile (
  165. "mfsr $p0, $mr8\n\t"
  166. "ori $p0, $p0, 0x02\n\t"
  167. "mtsr $p0, $mr8\n\t"
  168. "isb\n\t"
  169. );
  170. }
  171. void dcache_disable(void)
  172. {
  173. asm volatile (
  174. "mfsr $p0, $mr8\n\t"
  175. "li $p1, ~0x02\n\t"
  176. "and $p0, $p0, $p1\n\t"
  177. "mtsr $p0, $mr8\n\t"
  178. "isb\n\t"
  179. );
  180. }
  181. int dcache_status(void)
  182. {
  183. int ret;
  184. asm volatile (
  185. "mfsr $p0, $mr8\n\t"
  186. "andi %0, $p0, 0x02\n\t"
  187. : "=r" (ret)
  188. :
  189. : "memory"
  190. );
  191. return ret;
  192. }
  193. #else
  194. void dcache_wbinval_all(void)
  195. {
  196. }
  197. void flush_dcache_range(unsigned long start, unsigned long end)
  198. {
  199. }
  200. void invalidate_dcache_range(unsigned long start, unsigned long end)
  201. {
  202. }
  203. void dcache_enable(void)
  204. {
  205. }
  206. void dcache_disable(void)
  207. {
  208. }
  209. int dcache_status(void)
  210. {
  211. return 0;
  212. }
  213. #endif
  214. void flush_dcache_all(void)
  215. {
  216. dcache_wbinval_all();
  217. }
  218. void cache_flush(void)
  219. {
  220. flush_dcache_all();
  221. invalidate_icache_all();
  222. }
  223. void flush_cache(unsigned long addr, unsigned long size)
  224. {
  225. flush_dcache_range(addr, addr + size);
  226. invalidate_icache_range(addr, addr + size);
  227. }