cache.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/cache.h>
  9. #include <asm/cacheops.h>
  10. #ifdef CONFIG_MIPS_L2_CACHE
  11. #include <asm/cm.h>
  12. #endif
  13. #include <asm/io.h>
  14. #include <asm/mipsregs.h>
  15. #include <asm/system.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. static void probe_l2(void)
  18. {
  19. #ifdef CONFIG_MIPS_L2_CACHE
  20. unsigned long conf2, sl;
  21. bool l2c = false;
  22. if (!(read_c0_config1() & MIPS_CONF_M))
  23. return;
  24. conf2 = read_c0_config2();
  25. if (__mips_isa_rev >= 6) {
  26. l2c = conf2 & MIPS_CONF_M;
  27. if (l2c)
  28. l2c = read_c0_config3() & MIPS_CONF_M;
  29. if (l2c)
  30. l2c = read_c0_config4() & MIPS_CONF_M;
  31. if (l2c)
  32. l2c = read_c0_config5() & MIPS_CONF5_L2C;
  33. }
  34. if (l2c && config_enabled(CONFIG_MIPS_CM)) {
  35. gd->arch.l2_line_size = mips_cm_l2_line_size();
  36. } else if (l2c) {
  37. /* We don't know how to retrieve L2 config on this system */
  38. BUG();
  39. } else {
  40. sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
  41. gd->arch.l2_line_size = sl ? (2 << sl) : 0;
  42. }
  43. #endif
  44. }
  45. void mips_cache_probe(void)
  46. {
  47. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  48. unsigned long conf1, il, dl;
  49. conf1 = read_c0_config1();
  50. il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
  51. dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
  52. gd->arch.l1i_line_size = il ? (2 << il) : 0;
  53. gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
  54. #endif
  55. probe_l2();
  56. }
  57. static inline unsigned long icache_line_size(void)
  58. {
  59. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  60. return gd->arch.l1i_line_size;
  61. #else
  62. return CONFIG_SYS_ICACHE_LINE_SIZE;
  63. #endif
  64. }
  65. static inline unsigned long dcache_line_size(void)
  66. {
  67. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  68. return gd->arch.l1d_line_size;
  69. #else
  70. return CONFIG_SYS_DCACHE_LINE_SIZE;
  71. #endif
  72. }
  73. static inline unsigned long scache_line_size(void)
  74. {
  75. #ifdef CONFIG_MIPS_L2_CACHE
  76. return gd->arch.l2_line_size;
  77. #else
  78. return CONFIG_SYS_SCACHE_LINE_SIZE;
  79. #endif
  80. }
  81. #define cache_loop(start, end, lsize, ops...) do { \
  82. const void *addr = (const void *)(start & ~(lsize - 1)); \
  83. const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
  84. const unsigned int cache_ops[] = { ops }; \
  85. unsigned int i; \
  86. \
  87. if (!lsize) \
  88. break; \
  89. \
  90. for (; addr <= aend; addr += lsize) { \
  91. for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
  92. mips_cache(cache_ops[i], addr); \
  93. } \
  94. } while (0)
  95. void flush_cache(ulong start_addr, ulong size)
  96. {
  97. unsigned long ilsize = icache_line_size();
  98. unsigned long dlsize = dcache_line_size();
  99. unsigned long slsize = scache_line_size();
  100. /* aend will be miscalculated when size is zero, so we return here */
  101. if (size == 0)
  102. return;
  103. if ((ilsize == dlsize) && !slsize) {
  104. /* flush I-cache & D-cache simultaneously */
  105. cache_loop(start_addr, start_addr + size, ilsize,
  106. HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
  107. goto ops_done;
  108. }
  109. /* flush D-cache */
  110. cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
  111. /* flush L2 cache */
  112. cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
  113. /* flush I-cache */
  114. cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
  115. ops_done:
  116. /* ensure cache ops complete before any further memory accesses */
  117. sync();
  118. /* ensure the pipeline doesn't contain now-invalid instructions */
  119. instruction_hazard_barrier();
  120. }
  121. void __weak flush_dcache_range(ulong start_addr, ulong stop)
  122. {
  123. unsigned long lsize = dcache_line_size();
  124. unsigned long slsize = scache_line_size();
  125. /* aend will be miscalculated when size is zero, so we return here */
  126. if (start_addr == stop)
  127. return;
  128. cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
  129. /* flush L2 cache */
  130. cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
  131. /* ensure cache ops complete before any further memory accesses */
  132. sync();
  133. }
  134. void invalidate_dcache_range(ulong start_addr, ulong stop)
  135. {
  136. unsigned long lsize = dcache_line_size();
  137. unsigned long slsize = scache_line_size();
  138. /* aend will be miscalculated when size is zero, so we return here */
  139. if (start_addr == stop)
  140. return;
  141. /* invalidate L2 cache */
  142. cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
  143. cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
  144. /* ensure cache ops complete before any further memory accesses */
  145. sync();
  146. }
  147. int dcache_status(void)
  148. {
  149. unsigned int cca = read_c0_config() & CONF_CM_CMASK;
  150. return cca != CONF_CM_UNCACHED;
  151. }
  152. void dcache_enable(void)
  153. {
  154. puts("Not supported!\n");
  155. }
  156. void dcache_disable(void)
  157. {
  158. /* change CCA to uncached */
  159. change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
  160. /* ensure the pipeline doesn't contain now-invalid instructions */
  161. instruction_hazard_barrier();
  162. }