cacheops.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Cache operations for the cache instruction.
  4. *
  5. * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
  6. * (C) Copyright 1999 Silicon Graphics, Inc.
  7. */
  8. #ifndef __ASM_CACHEOPS_H
  9. #define __ASM_CACHEOPS_H
  10. #include <asm/cache.h>
  11. #ifndef __ASSEMBLY__
  12. static inline void mips_cache(int op, const volatile void *addr)
  13. {
  14. #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
  15. __builtin_mips_cache(op, addr);
  16. #else
  17. __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
  18. #endif
  19. }
  20. #define MIPS32_WHICH_ICACHE 0x0
  21. #define MIPS32_FETCH_AND_LOCK 0x7
  22. #define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
  23. /* Prefetch and lock instructions into cache */
  24. static inline void icache_lock(void *func, size_t len)
  25. {
  26. int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
  27. for (i = 0; i < lines; i++) {
  28. asm volatile (" cache %0, %1(%2)"
  29. : /* No Output */
  30. : "I" ICACHE_LOAD_LOCK,
  31. "n" (i * ARCH_DMA_MINALIGN),
  32. "r" (func)
  33. : /* No Clobbers */);
  34. }
  35. }
  36. #endif /* !__ASSEMBLY__ */
  37. /*
  38. * Cache Operations available on all MIPS processors with R4000-style caches
  39. */
  40. #define INDEX_INVALIDATE_I 0x00
  41. #define INDEX_WRITEBACK_INV_D 0x01
  42. #define INDEX_LOAD_TAG_I 0x04
  43. #define INDEX_LOAD_TAG_D 0x05
  44. #define INDEX_STORE_TAG_I 0x08
  45. #define INDEX_STORE_TAG_D 0x09
  46. #if defined(CONFIG_CPU_LOONGSON2)
  47. #define HIT_INVALIDATE_I 0x00
  48. #else
  49. #define HIT_INVALIDATE_I 0x10
  50. #endif
  51. #define HIT_INVALIDATE_D 0x11
  52. #define HIT_WRITEBACK_INV_D 0x15
  53. /*
  54. * R4000-specific cacheops
  55. */
  56. #define CREATE_DIRTY_EXCL_D 0x0d
  57. #define FILL 0x14
  58. #define HIT_WRITEBACK_I 0x18
  59. #define HIT_WRITEBACK_D 0x19
  60. /*
  61. * R4000SC and R4400SC-specific cacheops
  62. */
  63. #define INDEX_INVALIDATE_SI 0x02
  64. #define INDEX_WRITEBACK_INV_SD 0x03
  65. #define INDEX_LOAD_TAG_SI 0x06
  66. #define INDEX_LOAD_TAG_SD 0x07
  67. #define INDEX_STORE_TAG_SI 0x0A
  68. #define INDEX_STORE_TAG_SD 0x0B
  69. #define CREATE_DIRTY_EXCL_SD 0x0f
  70. #define HIT_INVALIDATE_SI 0x12
  71. #define HIT_INVALIDATE_SD 0x13
  72. #define HIT_WRITEBACK_INV_SD 0x17
  73. #define HIT_WRITEBACK_SD 0x1b
  74. #define HIT_SET_VIRTUAL_SI 0x1e
  75. #define HIT_SET_VIRTUAL_SD 0x1f
  76. /*
  77. * R5000-specific cacheops
  78. */
  79. #define R5K_PAGE_INVALIDATE_S 0x17
  80. /*
  81. * RM7000-specific cacheops
  82. */
  83. #define PAGE_INVALIDATE_T 0x16
  84. /*
  85. * R10000-specific cacheops
  86. *
  87. * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
  88. * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
  89. */
  90. #define INDEX_WRITEBACK_INV_S 0x03
  91. #define INDEX_LOAD_TAG_S 0x07
  92. #define INDEX_STORE_TAG_S 0x0B
  93. #define HIT_INVALIDATE_S 0x13
  94. #define CACHE_BARRIER 0x14
  95. #define HIT_WRITEBACK_INV_S 0x17
  96. #define INDEX_LOAD_DATA_I 0x18
  97. #define INDEX_LOAD_DATA_D 0x19
  98. #define INDEX_LOAD_DATA_S 0x1b
  99. #define INDEX_STORE_DATA_I 0x1c
  100. #define INDEX_STORE_DATA_D 0x1d
  101. #define INDEX_STORE_DATA_S 0x1f
  102. #endif /* __ASM_CACHEOPS_H */