cpu.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <asm/armv8/mmu.h>
  8. #include <asm/cache.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/cache.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #define VERSAL_MEM_MAP_USED 5
  15. #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  16. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  17. #define TCM_MAP 1
  18. #else
  19. #define TCM_MAP 0
  20. #endif
  21. /* +1 is end of list which needs to be empty */
  22. #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  23. static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
  24. {
  25. .virt = 0x80000000UL,
  26. .phys = 0x80000000UL,
  27. .size = 0x70000000UL,
  28. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29. PTE_BLOCK_NON_SHARE |
  30. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31. }, {
  32. .virt = 0xf0000000UL,
  33. .phys = 0xf0000000UL,
  34. .size = 0x0fe00000UL,
  35. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  36. PTE_BLOCK_NON_SHARE |
  37. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  38. }, {
  39. .virt = 0x400000000UL,
  40. .phys = 0x400000000UL,
  41. .size = 0x200000000UL,
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43. PTE_BLOCK_NON_SHARE |
  44. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  45. }, {
  46. .virt = 0x600000000UL,
  47. .phys = 0x600000000UL,
  48. .size = 0x800000000UL,
  49. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  50. PTE_BLOCK_INNER_SHARE
  51. }, {
  52. .virt = 0xe00000000UL,
  53. .phys = 0xe00000000UL,
  54. .size = 0xf200000000UL,
  55. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56. PTE_BLOCK_NON_SHARE |
  57. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58. }
  59. };
  60. void mem_map_fill(void)
  61. {
  62. int banks = VERSAL_MEM_MAP_USED;
  63. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  64. versal_mem_map[banks].virt = 0xffe00000UL;
  65. versal_mem_map[banks].phys = 0xffe00000UL;
  66. versal_mem_map[banks].size = 0x00200000UL;
  67. versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  68. PTE_BLOCK_INNER_SHARE;
  69. banks = banks + 1;
  70. #endif
  71. for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  72. /* Zero size means no more DDR that's this is end */
  73. if (!gd->bd->bi_dram[i].size)
  74. break;
  75. #if defined(CONFIG_VERSAL_NO_DDR)
  76. if (gd->bd->bi_dram[i].start < 0x80000000UL ||
  77. gd->bd->bi_dram[i].start > 0x100000000UL) {
  78. printf("Ignore caches over %llx/%llx\n",
  79. gd->bd->bi_dram[i].start,
  80. gd->bd->bi_dram[i].size);
  81. continue;
  82. }
  83. #endif
  84. versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  85. versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  86. versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
  87. versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  88. PTE_BLOCK_INNER_SHARE;
  89. banks = banks + 1;
  90. }
  91. }
  92. struct mm_region *mem_map = versal_mem_map;
  93. u64 get_page_table_size(void)
  94. {
  95. return 0x14000;
  96. }
  97. #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
  98. int arm_reserve_mmu(void)
  99. {
  100. tcm_init(TCM_LOCK);
  101. gd->arch.tlb_size = PGTABLE_SIZE;
  102. gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
  103. return 0;
  104. }
  105. #endif