clock.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2020
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra210 Clock control functions */
  7. #include <common.h>
  8. #include <errno.h>
  9. #include <asm/cache.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sysctr.h>
  13. #include <asm/arch/tegra.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <asm/arch-tegra/timer.h>
  16. #include <div64.h>
  17. #include <fdtdec.h>
  18. /*
  19. * Clock types that we can use as a source. The Tegra210 has muxes for the
  20. * peripheral clocks, and in most cases there are four options for the clock
  21. * source. This gives us a clock 'type' and exploits what commonality exists
  22. * in the device.
  23. *
  24. * Letters are obvious, except for T which means CLK_M, and S which means the
  25. * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  26. * datasheet) and PLL_M are different things. The former is the basic
  27. * clock supplied to the SOC from an external oscillator. The latter is the
  28. * memory clock PLL.
  29. *
  30. * See definitions in clock_id in the header file.
  31. */
  32. enum clock_type_id {
  33. CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
  34. CLOCK_TYPE_MCPA, /* and so on */
  35. CLOCK_TYPE_MCPT,
  36. CLOCK_TYPE_PCM,
  37. CLOCK_TYPE_PCMT,
  38. CLOCK_TYPE_PDCT,
  39. CLOCK_TYPE_ACPT,
  40. CLOCK_TYPE_ASPTE,
  41. CLOCK_TYPE_PDD2T,
  42. CLOCK_TYPE_PCST,
  43. CLOCK_TYPE_DP,
  44. CLOCK_TYPE_PC2CC3M,
  45. CLOCK_TYPE_PC2CC3S_T,
  46. CLOCK_TYPE_PC2CC3M_T,
  47. CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
  48. CLOCK_TYPE_MC2CC3P_A,
  49. CLOCK_TYPE_M,
  50. CLOCK_TYPE_MCPTM2C2C3,
  51. CLOCK_TYPE_PC2CC3T_S,
  52. CLOCK_TYPE_AC2CC3P_TS2,
  53. CLOCK_TYPE_PC01C00_C42C41TC40,
  54. CLOCK_TYPE_COUNT,
  55. CLOCK_TYPE_NONE = -1, /* invalid clock type */
  56. };
  57. enum {
  58. CLOCK_MAX_MUX = 8 /* number of source options for each clock */
  59. };
  60. /*
  61. * Clock source mux for each clock type. This just converts our enum into
  62. * a list of mux sources for use by the code.
  63. *
  64. * Note:
  65. * The extra column in each clock source array is used to store the mask
  66. * bits in its register for the source.
  67. */
  68. #define CLK(x) CLOCK_ID_ ## x
  69. static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
  70. { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
  71. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  72. MASK_BITS_31_30},
  73. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
  74. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  75. MASK_BITS_31_30},
  76. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  77. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  78. MASK_BITS_31_30},
  79. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
  80. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  81. MASK_BITS_31_30},
  82. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  83. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  84. MASK_BITS_31_30},
  85. { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
  86. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  87. MASK_BITS_31_30},
  88. { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  89. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  90. MASK_BITS_31_30},
  91. { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
  92. CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
  93. MASK_BITS_31_29},
  94. { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
  95. CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
  96. MASK_BITS_31_29},
  97. { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
  98. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  99. MASK_BITS_31_28},
  100. /* CLOCK_TYPE_DP */
  101. { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  102. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  103. MASK_BITS_31_28},
  104. /* Additional clock types on Tegra114+ */
  105. /* CLOCK_TYPE_PC2CC3M */
  106. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  107. CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
  108. MASK_BITS_31_29},
  109. /* CLOCK_TYPE_PC2CC3S_T */
  110. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  111. CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
  112. MASK_BITS_31_29},
  113. /* CLOCK_TYPE_PC2CC3M_T */
  114. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  115. CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
  116. MASK_BITS_31_29},
  117. /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
  118. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  119. CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
  120. MASK_BITS_31_29},
  121. /* CLOCK_TYPE_MC2CC3P_A */
  122. { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  123. CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
  124. MASK_BITS_31_29},
  125. /* CLOCK_TYPE_M */
  126. { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
  127. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  128. MASK_BITS_31_30},
  129. /* CLOCK_TYPE_MCPTM2C2C3 */
  130. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  131. CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
  132. MASK_BITS_31_29},
  133. /* CLOCK_TYPE_PC2CC3T_S */
  134. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  135. CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
  136. MASK_BITS_31_29},
  137. /* CLOCK_TYPE_AC2CC3P_TS2 */
  138. { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  139. CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
  140. MASK_BITS_31_29},
  141. /* CLOCK_TYPE_PC01C00_C42C41TC40 */
  142. { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
  143. CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
  144. MASK_BITS_31_29},
  145. };
  146. /*
  147. * Clock type for each peripheral clock source. We put the name in each
  148. * record just so it is easy to match things up
  149. */
  150. #define TYPE(name, type) type
  151. static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  152. /* 0x00 */
  153. TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
  154. TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
  155. TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
  156. TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
  157. TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
  158. TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
  159. TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
  160. TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
  161. /* 0x08 */
  162. TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
  163. TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
  164. TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
  165. TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
  166. TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
  167. TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
  168. TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
  169. TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
  170. /* 0x10 */
  171. TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
  172. TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
  173. TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
  174. TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
  175. TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
  176. TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
  177. TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
  178. TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
  179. /* 0x18 */
  180. TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
  181. TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
  182. TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
  183. TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
  184. TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
  185. TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
  186. TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
  187. TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
  188. /* 0x20 */
  189. TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
  190. TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
  191. TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
  192. TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
  193. TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
  194. TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
  195. TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
  196. TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
  197. /* 0x28 */
  198. TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
  199. TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
  200. TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
  201. TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
  202. TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
  203. TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
  204. TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
  205. TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
  206. /* 0x30 */
  207. TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
  208. TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
  209. TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
  210. TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
  211. TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
  212. TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
  213. TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
  214. TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
  215. /* 0x38 */
  216. TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
  217. TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
  218. TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
  219. TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
  220. TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
  221. TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
  222. TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
  223. TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
  224. /* 0x40 */
  225. TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
  226. TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
  227. TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
  228. TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
  229. TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
  230. TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
  231. TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
  232. TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
  233. /* 0x48 */
  234. TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
  235. TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
  236. TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
  237. TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
  238. TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
  239. TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
  240. TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
  241. TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
  242. /* 0x50 */
  243. TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
  244. TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
  245. TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
  246. TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
  247. TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
  248. TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
  249. TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
  250. TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
  251. /* 0x58 */
  252. TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
  253. TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
  254. TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
  255. TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
  256. TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
  257. TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
  258. TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
  259. TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
  260. /* 0x60 */
  261. TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
  262. TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
  263. TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
  264. TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
  265. TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
  266. TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
  267. TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
  268. TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
  269. /* 0x68 */
  270. TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
  271. TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
  272. TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
  273. TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
  274. TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
  275. TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
  276. TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
  277. TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
  278. /* 0x70 */
  279. TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
  280. TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
  281. TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
  282. TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
  283. TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
  284. TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
  285. TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
  286. TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
  287. /* 0x78 */
  288. TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
  289. TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
  290. TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
  291. TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
  292. TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
  293. TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
  294. TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
  295. TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
  296. /* 0x80 */
  297. TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
  298. TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
  299. TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
  300. TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
  301. TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
  302. TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
  303. TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
  304. TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
  305. /* 0x88 */
  306. TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
  307. TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
  308. TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
  309. TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
  310. TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
  311. TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
  312. TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
  313. TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
  314. /* 0x90 */
  315. TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
  316. TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
  317. };
  318. /*
  319. * This array translates a periph_id to a periphc_internal_id
  320. *
  321. * Not present/matched up:
  322. * uint vi_sensor; _VI_SENSOR_0, 0x1A8
  323. * SPDIF - which is both 0x08 and 0x0c
  324. *
  325. */
  326. #define NONE(name) (-1)
  327. #define OFFSET(name, value) PERIPHC_ ## name
  328. #define INTERNAL_ID(id) (id & 0x000000ff)
  329. static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  330. /* Low word: 31:0 */
  331. NONE(CPU),
  332. NONE(COP),
  333. NONE(TRIGSYS),
  334. NONE(ISPB),
  335. NONE(RESERVED4),
  336. NONE(TMR),
  337. PERIPHC_UART1,
  338. PERIPHC_UART2, /* and vfir 0x68 */
  339. /* 8 */
  340. NONE(GPIO),
  341. PERIPHC_SDMMC2,
  342. PERIPHC_SPDIF_IN,
  343. PERIPHC_I2S2,
  344. PERIPHC_I2C1,
  345. NONE(RESERVED13),
  346. PERIPHC_SDMMC1,
  347. PERIPHC_SDMMC4,
  348. /* 16 */
  349. NONE(TCW),
  350. PERIPHC_PWM,
  351. PERIPHC_I2S3,
  352. NONE(RESERVED19),
  353. PERIPHC_VI,
  354. NONE(RESERVED21),
  355. NONE(USBD),
  356. NONE(ISP),
  357. /* 24 */
  358. NONE(RESERVED24),
  359. NONE(RESERVED25),
  360. PERIPHC_DISP2,
  361. PERIPHC_DISP1,
  362. PERIPHC_HOST1X,
  363. NONE(VCP),
  364. PERIPHC_I2S1,
  365. NONE(CACHE2),
  366. /* Middle word: 63:32 */
  367. NONE(MEM),
  368. NONE(AHBDMA),
  369. NONE(APBDMA),
  370. NONE(RESERVED35),
  371. NONE(RESERVED36),
  372. NONE(STAT_MON),
  373. NONE(RESERVED38),
  374. NONE(FUSE),
  375. /* 40 */
  376. NONE(KFUSE),
  377. PERIPHC_SBC1, /* SBCx = SPIx */
  378. PERIPHC_NOR,
  379. NONE(RESERVED43),
  380. PERIPHC_SBC2,
  381. NONE(XIO),
  382. PERIPHC_SBC3,
  383. PERIPHC_I2C5,
  384. /* 48 */
  385. NONE(DSI),
  386. NONE(RESERVED49),
  387. PERIPHC_HSI,
  388. NONE(RESERVED51),
  389. NONE(CSI),
  390. NONE(RESERVED53),
  391. PERIPHC_I2C2,
  392. PERIPHC_UART3,
  393. /* 56 */
  394. NONE(MIPI_CAL),
  395. PERIPHC_EMC,
  396. NONE(USB2),
  397. NONE(USB3),
  398. NONE(RESERVED60),
  399. PERIPHC_VDE,
  400. NONE(BSEA),
  401. NONE(BSEV),
  402. /* Upper word 95:64 */
  403. NONE(RESERVED64),
  404. PERIPHC_UART4,
  405. PERIPHC_UART5,
  406. PERIPHC_I2C3,
  407. PERIPHC_SBC4,
  408. PERIPHC_SDMMC3,
  409. NONE(PCIE),
  410. PERIPHC_OWR,
  411. /* 72 */
  412. NONE(AFI),
  413. PERIPHC_CSITE,
  414. NONE(PCIEXCLK),
  415. NONE(AVPUCQ),
  416. NONE(LA),
  417. NONE(TRACECLKIN),
  418. NONE(SOC_THERM),
  419. NONE(DTV),
  420. /* 80 */
  421. NONE(RESERVED80),
  422. PERIPHC_I2CSLOW,
  423. NONE(DSIB),
  424. PERIPHC_TSEC,
  425. NONE(RESERVED84),
  426. NONE(RESERVED85),
  427. NONE(RESERVED86),
  428. NONE(EMUCIF),
  429. /* 88 */
  430. NONE(RESERVED88),
  431. NONE(XUSB_HOST),
  432. NONE(RESERVED90),
  433. PERIPHC_MSENC,
  434. NONE(RESERVED92),
  435. NONE(RESERVED93),
  436. NONE(RESERVED94),
  437. NONE(XUSB_DEV),
  438. /* V word: 31:0 */
  439. NONE(CPUG),
  440. NONE(CPULP),
  441. NONE(V_RESERVED2),
  442. PERIPHC_MSELECT,
  443. NONE(V_RESERVED4),
  444. PERIPHC_I2S4,
  445. PERIPHC_I2S5,
  446. PERIPHC_I2C4,
  447. /* 104 */
  448. PERIPHC_SBC5,
  449. PERIPHC_SBC6,
  450. PERIPHC_AUDIO,
  451. NONE(APBIF),
  452. NONE(V_RESERVED12),
  453. NONE(V_RESERVED13),
  454. NONE(V_RESERVED14),
  455. PERIPHC_HDA2CODEC2X,
  456. /* 112 */
  457. NONE(ATOMICS),
  458. NONE(V_RESERVED17),
  459. NONE(V_RESERVED18),
  460. NONE(V_RESERVED19),
  461. NONE(V_RESERVED20),
  462. NONE(V_RESERVED21),
  463. NONE(V_RESERVED22),
  464. PERIPHC_ACTMON,
  465. /* 120 */
  466. NONE(EXTPERIPH1),
  467. NONE(EXTPERIPH2),
  468. NONE(EXTPERIPH3),
  469. NONE(OOB),
  470. PERIPHC_SATA,
  471. PERIPHC_HDA,
  472. NONE(TZRAM),
  473. NONE(SE),
  474. /* W word: 31:0 */
  475. NONE(HDA2HDMICODEC),
  476. NONE(SATACOLD),
  477. NONE(W_RESERVED2),
  478. NONE(W_RESERVED3),
  479. NONE(W_RESERVED4),
  480. NONE(W_RESERVED5),
  481. NONE(W_RESERVED6),
  482. NONE(W_RESERVED7),
  483. /* 136 */
  484. NONE(CEC),
  485. NONE(W_RESERVED9),
  486. NONE(W_RESERVED10),
  487. NONE(W_RESERVED11),
  488. NONE(W_RESERVED12),
  489. NONE(W_RESERVED13),
  490. NONE(XUSB_PADCTL),
  491. NONE(W_RESERVED15),
  492. /* 144 */
  493. NONE(W_RESERVED16),
  494. NONE(W_RESERVED17),
  495. NONE(W_RESERVED18),
  496. NONE(W_RESERVED19),
  497. NONE(W_RESERVED20),
  498. NONE(ENTROPY),
  499. NONE(DDS),
  500. NONE(W_RESERVED23),
  501. /* 152 */
  502. NONE(W_RESERVED24),
  503. NONE(W_RESERVED25),
  504. NONE(W_RESERVED26),
  505. NONE(DVFS),
  506. NONE(XUSB_SS),
  507. NONE(W_RESERVED29),
  508. NONE(W_RESERVED30),
  509. NONE(W_RESERVED31),
  510. /* X word: 31:0 */
  511. NONE(SPARE),
  512. NONE(X_RESERVED1),
  513. NONE(X_RESERVED2),
  514. NONE(X_RESERVED3),
  515. NONE(CAM_MCLK),
  516. NONE(CAM_MCLK2),
  517. PERIPHC_I2C6,
  518. NONE(X_RESERVED7),
  519. /* 168 */
  520. NONE(X_RESERVED8),
  521. NONE(X_RESERVED9),
  522. NONE(X_RESERVED10),
  523. NONE(VIM2_CLK),
  524. NONE(X_RESERVED12),
  525. NONE(X_RESERVED13),
  526. NONE(EMC_DLL),
  527. NONE(X_RESERVED15),
  528. /* 176 */
  529. NONE(X_RESERVED16),
  530. NONE(CLK72MHZ),
  531. NONE(VIC),
  532. NONE(X_RESERVED19),
  533. NONE(X_RESERVED20),
  534. NONE(DPAUX),
  535. NONE(SOR0),
  536. NONE(X_RESERVED23),
  537. /* 184 */
  538. NONE(GPU),
  539. NONE(X_RESERVED25),
  540. NONE(X_RESERVED26),
  541. NONE(X_RESERVED27),
  542. NONE(X_RESERVED28),
  543. NONE(X_RESERVED29),
  544. NONE(X_RESERVED30),
  545. NONE(X_RESERVED31),
  546. /* Y: 192 (192 - 223) */
  547. NONE(Y_RESERVED0),
  548. PERIPHC_SDMMC_LEGACY_TM,
  549. PERIPHC_NVDEC,
  550. PERIPHC_NVJPG,
  551. NONE(Y_RESERVED4),
  552. PERIPHC_DMIC3, /* 197 */
  553. PERIPHC_APE, /* 198 */
  554. NONE(Y_RESERVED7),
  555. /* 200 */
  556. NONE(Y_RESERVED8),
  557. NONE(Y_RESERVED9),
  558. NONE(Y_RESERVED10),
  559. NONE(Y_RESERVED11),
  560. NONE(Y_RESERVED12),
  561. NONE(Y_RESERVED13),
  562. NONE(Y_RESERVED14),
  563. NONE(Y_RESERVED15),
  564. /* 208 */
  565. PERIPHC_VI_I2C, /* 208 */
  566. NONE(Y_RESERVED17),
  567. NONE(Y_RESERVED18),
  568. PERIPHC_QSPI, /* 211 */
  569. NONE(Y_RESERVED20),
  570. NONE(Y_RESERVED21),
  571. NONE(Y_RESERVED22),
  572. NONE(Y_RESERVED23),
  573. /* 216 */
  574. NONE(Y_RESERVED24),
  575. NONE(Y_RESERVED25),
  576. NONE(Y_RESERVED26),
  577. PERIPHC_NVENC, /* 219 */
  578. NONE(Y_RESERVED28),
  579. NONE(Y_RESERVED29),
  580. NONE(Y_RESERVED30),
  581. NONE(Y_RESERVED31),
  582. };
  583. /*
  584. * PLL divider shift/mask tables for all PLL IDs.
  585. */
  586. struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
  587. /*
  588. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
  589. * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
  590. */
  591. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  592. .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */
  593. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  594. .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
  595. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  596. .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */
  597. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  598. .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */
  599. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
  600. .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */
  601. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
  602. .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */
  603. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  604. .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */
  605. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  606. .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
  607. { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
  608. .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
  609. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
  610. .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
  611. };
  612. /*
  613. * Get the oscillator frequency, from the corresponding hardware configuration
  614. * field. Note that Tegra30+ support 3 new higher freqs, but we map back
  615. * to the old T20 freqs. Support for the higher oscillators is TBD.
  616. */
  617. enum clock_osc_freq clock_get_osc_freq(void)
  618. {
  619. struct clk_rst_ctlr *clkrst =
  620. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  621. u32 reg;
  622. reg = readl(&clkrst->crc_osc_ctrl);
  623. reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
  624. /*
  625. * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
  626. * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
  627. */
  628. if (reg == 5) {
  629. debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
  630. /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
  631. return 4;
  632. }
  633. /*
  634. * Map to most common (T20) freqs (except 38.4, handled above):
  635. * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
  636. */
  637. return reg >> 2;
  638. }
  639. /* Returns a pointer to the clock source register for a peripheral */
  640. u32 *get_periph_source_reg(enum periph_id periph_id)
  641. {
  642. struct clk_rst_ctlr *clkrst =
  643. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  644. enum periphc_internal_id internal_id;
  645. /* Coresight is a special case */
  646. if (periph_id == PERIPH_ID_CSI)
  647. return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
  648. assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
  649. internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
  650. assert(internal_id != -1);
  651. if (internal_id < PERIPHC_VW_FIRST)
  652. /* L, H, U */
  653. return &clkrst->crc_clk_src[internal_id];
  654. if (internal_id < PERIPHC_X_FIRST) {
  655. /* VW */
  656. internal_id -= PERIPHC_VW_FIRST;
  657. return &clkrst->crc_clk_src_vw[internal_id];
  658. }
  659. if (internal_id < PERIPHC_Y_FIRST) {
  660. /* X */
  661. internal_id -= PERIPHC_X_FIRST;
  662. return &clkrst->crc_clk_src_x[internal_id];
  663. }
  664. /* Y */
  665. internal_id -= PERIPHC_Y_FIRST;
  666. return &clkrst->crc_clk_src_y[internal_id];
  667. }
  668. int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
  669. int *divider_bits, int *type)
  670. {
  671. enum periphc_internal_id internal_id;
  672. if (!clock_periph_id_isvalid(periph_id))
  673. return -1;
  674. internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
  675. if (!periphc_internal_id_isvalid(internal_id))
  676. return -1;
  677. *type = clock_periph_type[internal_id];
  678. if (!clock_type_id_isvalid(*type))
  679. return -1;
  680. *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
  681. if (*type == CLOCK_TYPE_PC2CC3M_T16)
  682. *divider_bits = 16;
  683. else
  684. *divider_bits = 8;
  685. return 0;
  686. }
  687. enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
  688. {
  689. enum periphc_internal_id internal_id;
  690. int type;
  691. if (!clock_periph_id_isvalid(periph_id))
  692. return CLOCK_ID_NONE;
  693. internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
  694. if (!periphc_internal_id_isvalid(internal_id))
  695. return CLOCK_ID_NONE;
  696. type = clock_periph_type[internal_id];
  697. if (!clock_type_id_isvalid(type))
  698. return CLOCK_ID_NONE;
  699. return clock_source[type][source];
  700. }
  701. /**
  702. * Given a peripheral ID and the required source clock, this returns which
  703. * value should be programmed into the source mux for that peripheral.
  704. *
  705. * There is special code here to handle the one source type with 5 sources.
  706. *
  707. * @param periph_id peripheral to start
  708. * @param source PLL id of required parent clock
  709. * @param mux_bits Set to number of bits in mux register: 2 or 4
  710. * @param divider_bits Set to number of divider bits (8 or 16)
  711. * @return mux value (0-4, or -1 if not found)
  712. */
  713. int get_periph_clock_source(enum periph_id periph_id,
  714. enum clock_id parent, int *mux_bits, int *divider_bits)
  715. {
  716. enum clock_type_id type;
  717. int mux, err;
  718. err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
  719. assert(!err);
  720. for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
  721. if (clock_source[type][mux] == parent)
  722. return mux;
  723. /* if we get here, either us or the caller has made a mistake */
  724. printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
  725. parent);
  726. return -1;
  727. }
  728. void clock_set_enable(enum periph_id periph_id, int enable)
  729. {
  730. struct clk_rst_ctlr *clkrst =
  731. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  732. u32 *clk;
  733. u32 reg;
  734. /* Enable/disable the clock to this peripheral */
  735. assert(clock_periph_id_isvalid(periph_id));
  736. if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
  737. clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
  738. else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
  739. clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
  740. else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
  741. clk = &clkrst->crc_clk_out_enb_x;
  742. else
  743. clk = &clkrst->crc_clk_out_enb_y;
  744. reg = readl(clk);
  745. if (enable)
  746. reg |= PERIPH_MASK(periph_id);
  747. else
  748. reg &= ~PERIPH_MASK(periph_id);
  749. writel(reg, clk);
  750. }
  751. void reset_set_enable(enum periph_id periph_id, int enable)
  752. {
  753. struct clk_rst_ctlr *clkrst =
  754. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  755. u32 *reset;
  756. u32 reg;
  757. /* Enable/disable reset to the peripheral */
  758. assert(clock_periph_id_isvalid(periph_id));
  759. if (periph_id < PERIPH_ID_VW_FIRST)
  760. reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
  761. else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
  762. reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
  763. else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
  764. reset = &clkrst->crc_rst_devices_x;
  765. else
  766. reset = &clkrst->crc_rst_devices_y;
  767. reg = readl(reset);
  768. if (enable)
  769. reg |= PERIPH_MASK(periph_id);
  770. else
  771. reg &= ~PERIPH_MASK(periph_id);
  772. writel(reg, reset);
  773. }
  774. #ifdef CONFIG_OF_CONTROL
  775. /*
  776. * Convert a device tree clock ID to our peripheral ID. They are mostly
  777. * the same but we are very cautious so we check that a valid clock ID is
  778. * provided.
  779. *
  780. * @param clk_id Clock ID according to tegra210 device tree binding
  781. * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  782. */
  783. enum periph_id clk_id_to_periph_id(int clk_id)
  784. {
  785. if (clk_id > PERIPH_ID_COUNT)
  786. return PERIPH_ID_NONE;
  787. switch (clk_id) {
  788. case PERIPH_ID_RESERVED4:
  789. case PERIPH_ID_RESERVED25:
  790. case PERIPH_ID_RESERVED35:
  791. case PERIPH_ID_RESERVED36:
  792. case PERIPH_ID_RESERVED38:
  793. case PERIPH_ID_RESERVED43:
  794. case PERIPH_ID_RESERVED49:
  795. case PERIPH_ID_RESERVED53:
  796. case PERIPH_ID_RESERVED64:
  797. case PERIPH_ID_RESERVED84:
  798. case PERIPH_ID_RESERVED85:
  799. case PERIPH_ID_RESERVED86:
  800. case PERIPH_ID_RESERVED88:
  801. case PERIPH_ID_RESERVED90:
  802. case PERIPH_ID_RESERVED92:
  803. case PERIPH_ID_RESERVED93:
  804. case PERIPH_ID_RESERVED94:
  805. case PERIPH_ID_V_RESERVED2:
  806. case PERIPH_ID_V_RESERVED4:
  807. case PERIPH_ID_V_RESERVED17:
  808. case PERIPH_ID_V_RESERVED18:
  809. case PERIPH_ID_V_RESERVED19:
  810. case PERIPH_ID_V_RESERVED20:
  811. case PERIPH_ID_V_RESERVED21:
  812. case PERIPH_ID_V_RESERVED22:
  813. case PERIPH_ID_W_RESERVED2:
  814. case PERIPH_ID_W_RESERVED3:
  815. case PERIPH_ID_W_RESERVED4:
  816. case PERIPH_ID_W_RESERVED5:
  817. case PERIPH_ID_W_RESERVED6:
  818. case PERIPH_ID_W_RESERVED7:
  819. case PERIPH_ID_W_RESERVED9:
  820. case PERIPH_ID_W_RESERVED10:
  821. case PERIPH_ID_W_RESERVED11:
  822. case PERIPH_ID_W_RESERVED12:
  823. case PERIPH_ID_W_RESERVED13:
  824. case PERIPH_ID_W_RESERVED15:
  825. case PERIPH_ID_W_RESERVED16:
  826. case PERIPH_ID_W_RESERVED17:
  827. case PERIPH_ID_W_RESERVED18:
  828. case PERIPH_ID_W_RESERVED19:
  829. case PERIPH_ID_W_RESERVED20:
  830. case PERIPH_ID_W_RESERVED23:
  831. case PERIPH_ID_W_RESERVED29:
  832. case PERIPH_ID_W_RESERVED30:
  833. case PERIPH_ID_W_RESERVED31:
  834. return PERIPH_ID_NONE;
  835. default:
  836. return clk_id;
  837. }
  838. }
  839. #endif /* CONFIG_OF_CONTROL */
  840. /*
  841. * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
  842. * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
  843. */
  844. void tegra210_setup_pllp(void)
  845. {
  846. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  847. u32 reg;
  848. /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
  849. /* OUT1 */
  850. /* Assert RSTN before enable */
  851. reg = PLLP_OUT1_RSTN_EN;
  852. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  853. /* Set divisor and reenable */
  854. reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
  855. | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
  856. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  857. /* OUT3, 4 */
  858. /* Assert RSTN before enable */
  859. reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
  860. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  861. /* Set divisor and reenable */
  862. reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
  863. | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
  864. | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
  865. | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
  866. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  867. /*
  868. * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
  869. * you can change PLLP_BASE DIVP here. Currently defaults
  870. * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
  871. * See Table 13 in section 5.1.4 in T210 TRM for more info.
  872. */
  873. }
  874. void clock_early_init(void)
  875. {
  876. struct clk_rst_ctlr *clkrst =
  877. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  878. struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
  879. u32 data;
  880. tegra210_setup_pllp();
  881. /*
  882. * PLLC output frequency set to 600Mhz
  883. * PLLD output frequency set to 925Mhz
  884. */
  885. switch (clock_get_osc_freq()) {
  886. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  887. clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
  888. clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
  889. break;
  890. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  891. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  892. clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
  893. break;
  894. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  895. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  896. clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
  897. break;
  898. case CLOCK_OSC_FREQ_19_2:
  899. clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
  900. clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
  901. break;
  902. case CLOCK_OSC_FREQ_38_4:
  903. clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
  904. clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
  905. break;
  906. default:
  907. /*
  908. * These are not supported. It is too early to print a
  909. * message and the UART likely won't work anyway due to the
  910. * oscillator being wrong.
  911. */
  912. break;
  913. }
  914. /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
  915. clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
  916. (1 << PLLC_IDDQ));
  917. udelay(2);
  918. /*
  919. * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
  920. * to pll_out[1]
  921. */
  922. clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
  923. (1 << PLLC_RESET));
  924. udelay(2);
  925. /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
  926. data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);
  927. writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
  928. udelay(2);
  929. }
  930. unsigned int clk_m_get_rate(unsigned parent_rate)
  931. {
  932. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  933. u32 value, div;
  934. value = readl(&clkrst->crc_spare_reg0);
  935. div = ((value >> 2) & 0x3) + 1;
  936. return parent_rate / div;
  937. }
  938. void arch_timer_init(void)
  939. {
  940. struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
  941. u32 freq, val;
  942. freq = clock_get_rate(CLOCK_ID_CLK_M);
  943. debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
  944. if (current_el() == 3)
  945. asm("msr cntfrq_el0, %0\n" : : "r" (freq));
  946. /* Only Tegra114+ has the System Counter regs */
  947. debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
  948. writel(freq, &sysctr->cntfid0);
  949. val = readl(&sysctr->cntcr);
  950. val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
  951. writel(val, &sysctr->cntcr);
  952. debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
  953. }
  954. #define PLLREFE_MISC 0x4c8
  955. #define PLLREFE_MISC_LOCK BIT(27)
  956. #define PLLREFE_MISC_IDDQ BIT(24)
  957. #define PLLREFE_BASE 0x4c4
  958. #define PLLREFE_BASE_BYPASS BIT(31)
  959. #define PLLREFE_BASE_ENABLE BIT(30)
  960. #define PLLREFE_BASE_REF_DIS BIT(29)
  961. #define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
  962. #define PLLREFE_BASE_KVCO BIT(26)
  963. #define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
  964. #define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
  965. #define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
  966. static int tegra_pllref_enable(void)
  967. {
  968. u32 value;
  969. unsigned long start;
  970. /*
  971. * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
  972. * Recovery Mode or Boot from USB", sub-section "PLLREFE".
  973. */
  974. value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
  975. value &= ~PLLREFE_MISC_IDDQ;
  976. writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC);
  977. udelay(5);
  978. value = PLLREFE_BASE_ENABLE |
  979. PLLREFE_BASE_KCP(0) |
  980. PLLREFE_BASE_DIVP(0) |
  981. PLLREFE_BASE_DIVN(0x41) |
  982. PLLREFE_BASE_DIVM(4);
  983. writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE);
  984. debug("waiting for pllrefe lock\n");
  985. start = get_timer(0);
  986. while (get_timer(start) < 250) {
  987. value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
  988. if (value & PLLREFE_MISC_LOCK)
  989. break;
  990. }
  991. if (!(value & PLLREFE_MISC_LOCK)) {
  992. debug(" timeout\n");
  993. return -ETIMEDOUT;
  994. }
  995. debug(" done\n");
  996. return 0;
  997. }
  998. #define PLLE_SS_CNTL 0x68
  999. #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
  1000. #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
  1001. #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
  1002. #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
  1003. #define PLLE_SS_CNTL_SSCBYP (1 << 12)
  1004. #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
  1005. #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
  1006. #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
  1007. #define PLLE_BASE 0x0e8
  1008. #define PLLE_BASE_ENABLE (1 << 31)
  1009. #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
  1010. #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
  1011. #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
  1012. #define PLLE_MISC 0x0ec
  1013. #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
  1014. #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
  1015. #define PLLE_MISC_LOCK (1 << 11)
  1016. #define PLLE_PTS (1 << 8)
  1017. #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
  1018. #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
  1019. #define PLLE_MISC_KVCO (1 << 0)
  1020. #define PLLE_AUX 0x48c
  1021. #define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
  1022. #define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
  1023. #define PLLE_AUX_SEQ_ENABLE (1 << 24)
  1024. #define PLLE_AUX_SS_SWCTL (1 << 6)
  1025. #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
  1026. #define PLLE_AUX_USE_LOCKDET (1 << 3)
  1027. int tegra_plle_enable(void)
  1028. {
  1029. u32 value;
  1030. unsigned long start;
  1031. /* PLLREF feeds PLLE */
  1032. tegra_pllref_enable();
  1033. /*
  1034. * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
  1035. * Recovery Mode or Boot from USB", sub-section "PLLEs".
  1036. */
  1037. /* 1. Select XTAL as the source */
  1038. value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
  1039. value &= ~PLLE_AUX_REF_SEL_PLLREFE;
  1040. writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
  1041. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  1042. value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
  1043. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  1044. /* 2. Wait 5 us */
  1045. udelay(5);
  1046. /*
  1047. * 3. Program the following registers to generate a low jitter 100MHz
  1048. * clock.
  1049. */
  1050. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  1051. value &= ~PLLE_BASE_PLDIV_CML(0x1f);
  1052. value &= ~PLLE_BASE_NDIV(0xff);
  1053. value &= ~PLLE_BASE_MDIV(0xff);
  1054. value |= PLLE_BASE_PLDIV_CML(0xe);
  1055. value |= PLLE_BASE_NDIV(0x7d);
  1056. value |= PLLE_BASE_MDIV(2);
  1057. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  1058. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  1059. value |= PLLE_PTS;
  1060. value &= ~PLLE_MISC_KCP(3);
  1061. value &= ~PLLE_MISC_VREG_CTRL(3);
  1062. value &= ~PLLE_MISC_KVCO;
  1063. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  1064. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  1065. value |= PLLE_BASE_ENABLE;
  1066. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  1067. /* 4. Wait for LOCK */
  1068. debug("waiting for plle lock\n");
  1069. start = get_timer(0);
  1070. while (get_timer(start) < 250) {
  1071. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  1072. if (value & PLLE_MISC_LOCK)
  1073. break;
  1074. }
  1075. if (!(value & PLLE_MISC_LOCK)) {
  1076. debug(" timeout\n");
  1077. return -ETIMEDOUT;
  1078. }
  1079. debug(" done\n");
  1080. /* 5. Enable SSA */
  1081. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  1082. value &= ~PLLE_SS_CNTL_SSCINC(0xff);
  1083. value |= PLLE_SS_CNTL_SSCINC(1);
  1084. value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
  1085. value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
  1086. value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
  1087. value |= PLLE_SS_CNTL_SSCMAX(0x21);
  1088. value &= ~PLLE_SS_CNTL_SSCINVERT;
  1089. value &= ~PLLE_SS_CNTL_SSCCENTER;
  1090. value &= ~PLLE_SS_CNTL_BYPASS_SS;
  1091. value &= ~PLLE_SS_CNTL_SSCBYP;
  1092. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  1093. /* 6. Wait 300 ns */
  1094. udelay(1);
  1095. value &= ~PLLE_SS_CNTL_INTERP_RESET;
  1096. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  1097. return 0;
  1098. }
  1099. struct periph_clk_init periph_clk_init_table[] = {
  1100. { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
  1101. { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
  1102. { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
  1103. { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
  1104. { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
  1105. { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
  1106. { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
  1107. { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
  1108. { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
  1109. { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
  1110. { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
  1111. { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
  1112. { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
  1113. { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
  1114. { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
  1115. { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
  1116. { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
  1117. { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
  1118. { -1, },
  1119. };