board.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <ns16550.h>
  11. #include <spl.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  15. #include <asm/arch/clock.h>
  16. #endif
  17. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  18. #include <asm/arch/funcmux.h>
  19. #endif
  20. #if IS_ENABLED(CONFIG_TEGRA_MC)
  21. #include <asm/arch/mc.h>
  22. #endif
  23. #include <asm/arch/tegra.h>
  24. #include <asm/arch-tegra/ap.h>
  25. #include <asm/arch-tegra/board.h>
  26. #include <asm/arch-tegra/cboot.h>
  27. #include <asm/arch-tegra/pmc.h>
  28. #include <asm/arch-tegra/sys_proto.h>
  29. #include <asm/arch-tegra/warmboot.h>
  30. void save_boot_params_ret(void);
  31. DECLARE_GLOBAL_DATA_PTR;
  32. enum {
  33. /* UARTs which we can enable */
  34. UARTA = 1 << 0,
  35. UARTB = 1 << 1,
  36. UARTC = 1 << 2,
  37. UARTD = 1 << 3,
  38. UARTE = 1 << 4,
  39. UART_COUNT = 5,
  40. };
  41. static bool from_spl __attribute__ ((section(".data")));
  42. #ifndef CONFIG_SPL_BUILD
  43. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  44. unsigned long r3)
  45. {
  46. from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  47. /*
  48. * The logic for this is somewhat indirect. The purpose of the marker
  49. * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
  50. * was loaded from a read-only instance of itself, which is something
  51. * that can happen in secure boot setups. So basically the presence
  52. * of the marker is an indication that U-Boot was loaded by one such
  53. * special variant of U-Boot. Conversely, the absence of the marker
  54. * indicates that this instance of U-Boot was loaded by something
  55. * other than a special U-Boot. This could be SPL, but it could just
  56. * as well be one of any number of other first stage bootloaders.
  57. */
  58. if (from_spl)
  59. cboot_save_boot_params(r0, r1, r2, r3);
  60. save_boot_params_ret();
  61. }
  62. #endif
  63. bool spl_was_boot_source(void)
  64. {
  65. return from_spl;
  66. }
  67. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  68. #if !defined(CONFIG_TEGRA124)
  69. #error tegra_cpu_is_non_secure has only been validated on Tegra124
  70. #endif
  71. bool tegra_cpu_is_non_secure(void)
  72. {
  73. /*
  74. * This register reads 0xffffffff in non-secure mode. This register
  75. * only implements bits 31:20, so the lower bits will always read 0 in
  76. * secure mode. Thus, the lower bits are an indicator for secure vs.
  77. * non-secure mode.
  78. */
  79. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  80. uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  81. return (mc_s_cfg0 & 1) == 1;
  82. }
  83. #endif
  84. #if IS_ENABLED(CONFIG_TEGRA_MC)
  85. /* Read the RAM size directly from the memory controller */
  86. static phys_size_t query_sdram_size(void)
  87. {
  88. struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  89. u32 emem_cfg;
  90. phys_size_t size_bytes;
  91. emem_cfg = readl(&mc->mc_emem_cfg);
  92. #if defined(CONFIG_TEGRA20)
  93. debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  94. size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  95. #else
  96. debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  97. #ifndef CONFIG_PHYS_64BIT
  98. /*
  99. * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  100. * and will wrap. Clip the reported size to the maximum that a 32-bit
  101. * variable can represent (rounded to a page).
  102. */
  103. if (emem_cfg >= 4096) {
  104. size_bytes = U32_MAX & ~(0x1000 - 1);
  105. } else
  106. #endif
  107. {
  108. /* RAM size EMC is programmed to. */
  109. size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
  110. #ifndef CONFIG_ARM64
  111. /*
  112. * If all RAM fits within 32-bits, it can be accessed without
  113. * LPAE, so go test the RAM size. Otherwise, we can't access
  114. * all the RAM, and get_ram_size() would get confused, so
  115. * avoid using it. There's no reason we should need this
  116. * validation step anyway.
  117. */
  118. if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  119. size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  120. size_bytes);
  121. #endif
  122. }
  123. #endif
  124. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
  125. /* External memory limited to 2047 MB due to IROM/HI-VEC */
  126. if (size_bytes == SZ_2G)
  127. size_bytes -= SZ_1M;
  128. #endif
  129. return size_bytes;
  130. }
  131. #endif
  132. int dram_init(void)
  133. {
  134. int err;
  135. /* try to initialize DRAM from cboot DTB first */
  136. err = cboot_dram_init();
  137. if (err == 0)
  138. return 0;
  139. #if IS_ENABLED(CONFIG_TEGRA_MC)
  140. /* We do not initialise DRAM here. We just query the size */
  141. gd->ram_size = query_sdram_size();
  142. #endif
  143. return 0;
  144. }
  145. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  146. static int uart_configs[] = {
  147. #if defined(CONFIG_TEGRA20)
  148. #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  149. FUNCMUX_UART1_UAA_UAB,
  150. #elif defined(CONFIG_TEGRA_UARTA_GPU)
  151. FUNCMUX_UART1_GPU,
  152. #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  153. FUNCMUX_UART1_SDIO1,
  154. #else
  155. FUNCMUX_UART1_IRRX_IRTX,
  156. #endif
  157. FUNCMUX_UART2_UAD,
  158. -1,
  159. FUNCMUX_UART4_GMC,
  160. -1,
  161. #elif defined(CONFIG_TEGRA30)
  162. FUNCMUX_UART1_ULPI, /* UARTA */
  163. -1,
  164. -1,
  165. -1,
  166. -1,
  167. #elif defined(CONFIG_TEGRA114)
  168. -1,
  169. -1,
  170. -1,
  171. FUNCMUX_UART4_GMI, /* UARTD */
  172. -1,
  173. #elif defined(CONFIG_TEGRA124)
  174. FUNCMUX_UART1_KBC, /* UARTA */
  175. -1,
  176. -1,
  177. FUNCMUX_UART4_GPIO, /* UARTD */
  178. -1,
  179. #else /* Tegra210 */
  180. FUNCMUX_UART1_UART1, /* UARTA */
  181. -1,
  182. -1,
  183. FUNCMUX_UART4_UART4, /* UARTD */
  184. -1,
  185. #endif
  186. };
  187. /**
  188. * Set up the specified uarts
  189. *
  190. * @param uarts_ids Mask containing UARTs to init (UARTx)
  191. */
  192. static void setup_uarts(int uart_ids)
  193. {
  194. static enum periph_id id_for_uart[] = {
  195. PERIPH_ID_UART1,
  196. PERIPH_ID_UART2,
  197. PERIPH_ID_UART3,
  198. PERIPH_ID_UART4,
  199. PERIPH_ID_UART5,
  200. };
  201. size_t i;
  202. for (i = 0; i < UART_COUNT; i++) {
  203. if (uart_ids & (1 << i)) {
  204. enum periph_id id = id_for_uart[i];
  205. funcmux_select(id, uart_configs[i]);
  206. clock_ll_start_uart(id);
  207. }
  208. }
  209. }
  210. #endif
  211. void board_init_uart_f(void)
  212. {
  213. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  214. int uart_ids = 0; /* bit mask of which UART ids to enable */
  215. #ifdef CONFIG_TEGRA_ENABLE_UARTA
  216. uart_ids |= UARTA;
  217. #endif
  218. #ifdef CONFIG_TEGRA_ENABLE_UARTB
  219. uart_ids |= UARTB;
  220. #endif
  221. #ifdef CONFIG_TEGRA_ENABLE_UARTC
  222. uart_ids |= UARTC;
  223. #endif
  224. #ifdef CONFIG_TEGRA_ENABLE_UARTD
  225. uart_ids |= UARTD;
  226. #endif
  227. #ifdef CONFIG_TEGRA_ENABLE_UARTE
  228. uart_ids |= UARTE;
  229. #endif
  230. setup_uarts(uart_ids);
  231. #endif
  232. }
  233. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  234. static struct ns16550_platdata ns16550_com1_pdata = {
  235. .base = CONFIG_SYS_NS16550_COM1,
  236. .reg_shift = 2,
  237. .clock = CONFIG_SYS_NS16550_CLK,
  238. .fcr = UART_FCR_DEFVAL,
  239. };
  240. U_BOOT_DEVICE(ns16550_com1) = {
  241. "ns16550_serial", &ns16550_com1_pdata
  242. };
  243. #endif
  244. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  245. void enable_caches(void)
  246. {
  247. /* Enable D-cache. I-cache is already enabled in start.S */
  248. dcache_enable();
  249. }
  250. #endif