board.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <ram.h>
  11. #include <syscon.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/boot_mode.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/periph.h>
  17. #include <asm/arch-rockchip/misc.h>
  18. #include <power/regulator.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. __weak int rk_board_late_init(void)
  21. {
  22. return 0;
  23. }
  24. int board_late_init(void)
  25. {
  26. setup_boot_mode();
  27. return rk_board_late_init();
  28. }
  29. int board_init(void)
  30. {
  31. int ret;
  32. #ifdef CONFIG_DM_REGULATOR
  33. ret = regulators_enable_boot_on(false);
  34. if (ret)
  35. debug("%s: Cannot enable boot on regulator\n", __func__);
  36. #endif
  37. return 0;
  38. }
  39. #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  40. void enable_caches(void)
  41. {
  42. /* Enable D-cache. I-cache is already enabled in start.S */
  43. dcache_enable();
  44. }
  45. #endif
  46. #if defined(CONFIG_USB_GADGET)
  47. #include <usb.h>
  48. #if defined(CONFIG_USB_GADGET_DWC2_OTG)
  49. #include <usb/dwc2_udc.h>
  50. static struct dwc2_plat_otg_data otg_data = {
  51. .rx_fifo_sz = 512,
  52. .np_tx_fifo_sz = 16,
  53. .tx_fifo_sz = 128,
  54. };
  55. int board_usb_init(int index, enum usb_init_type init)
  56. {
  57. ofnode node;
  58. const char *mode;
  59. bool matched = false;
  60. /* find the usb_otg node */
  61. node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
  62. while (ofnode_valid(node)) {
  63. mode = ofnode_read_string(node, "dr_mode");
  64. if (mode && strcmp(mode, "otg") == 0) {
  65. matched = true;
  66. break;
  67. }
  68. node = ofnode_by_compatible(node, "snps,dwc2");
  69. }
  70. if (!matched) {
  71. debug("Not found usb_otg device\n");
  72. return -ENODEV;
  73. }
  74. otg_data.regs_otg = ofnode_get_addr(node);
  75. #ifdef CONFIG_ROCKCHIP_RK3288
  76. int ret;
  77. u32 phandle, offset;
  78. ofnode phy_node;
  79. ret = ofnode_read_u32(node, "phys", &phandle);
  80. if (ret)
  81. return ret;
  82. node = ofnode_get_by_phandle(phandle);
  83. if (!ofnode_valid(node)) {
  84. debug("Not found usb phy device\n");
  85. return -ENODEV;
  86. }
  87. phy_node = ofnode_get_parent(node);
  88. if (!ofnode_valid(node)) {
  89. debug("Not found usb phy device\n");
  90. return -ENODEV;
  91. }
  92. otg_data.phy_of_node = phy_node;
  93. ret = ofnode_read_u32(node, "reg", &offset);
  94. if (ret)
  95. return ret;
  96. otg_data.regs_phy = offset +
  97. (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  98. #endif
  99. return dwc2_udc_probe(&otg_data);
  100. }
  101. int board_usb_cleanup(int index, enum usb_init_type init)
  102. {
  103. return 0;
  104. }
  105. #endif /* CONFIG_USB_GADGET_DWC2_OTG */
  106. #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
  107. #include <dwc3-uboot.h>
  108. static struct dwc3_device dwc3_device_data = {
  109. .maximum_speed = USB_SPEED_HIGH,
  110. .base = 0xfe800000,
  111. .dr_mode = USB_DR_MODE_PERIPHERAL,
  112. .index = 0,
  113. .dis_u2_susphy_quirk = 1,
  114. .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
  115. };
  116. int usb_gadget_handle_interrupts(void)
  117. {
  118. dwc3_uboot_handle_interrupt(0);
  119. return 0;
  120. }
  121. int board_usb_init(int index, enum usb_init_type init)
  122. {
  123. return dwc3_uboot_init(&dwc3_device_data);
  124. }
  125. #endif /* CONFIG_USB_DWC3_GADGET */
  126. #endif /* CONFIG_USB_GADGET */
  127. #if CONFIG_IS_ENABLED(FASTBOOT)
  128. int fastboot_set_reboot_flag(void)
  129. {
  130. printf("Setting reboot to fastboot flag ...\n");
  131. /* Set boot mode to fastboot */
  132. writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
  133. return 0;
  134. }
  135. #endif
  136. #ifdef CONFIG_MISC_INIT_R
  137. __weak int misc_init_r(void)
  138. {
  139. const u32 cpuid_offset = 0x7;
  140. const u32 cpuid_length = 0x10;
  141. u8 cpuid[cpuid_length];
  142. int ret;
  143. ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
  144. if (ret)
  145. return ret;
  146. ret = rockchip_cpuid_set(cpuid, cpuid_length);
  147. if (ret)
  148. return ret;
  149. ret = rockchip_setup_macaddr();
  150. return ret;
  151. }
  152. #endif