cpu.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * (C) Copyright 2009
  7. * Marvell Semiconductor <www.marvell.com>
  8. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <u-boot/md5.h>
  17. #include <asm/arch/cpu.h>
  18. #define BUFLEN 16
  19. void reset_cpu(unsigned long ignored)
  20. {
  21. struct orion5x_cpu_registers *cpureg =
  22. (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
  23. writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  24. &cpureg->rstoutn_mask);
  25. writel(readl(&cpureg->sys_soft_rst) | 1,
  26. &cpureg->sys_soft_rst);
  27. while (1)
  28. ;
  29. }
  30. /*
  31. * Compute Window Size field value from size expressed in bytes
  32. * Used with the Base register to set the address window size and location.
  33. * Must be programmed from LSB to MSB as sequence of ones followed by
  34. * sequence of zeros. The number of ones specifies the size of the window in
  35. * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
  36. * NOTES:
  37. * 1) A sizeval equal to 0x0 specifies 4 GiB.
  38. * 2) A return value of 0x0 specifies 64 KiB.
  39. */
  40. unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
  41. {
  42. /*
  43. * Calculate the number of 64 KiB blocks needed minus one (rounding up).
  44. * For sizeval > 0 this is equivalent to:
  45. * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
  46. */
  47. sizeval = (sizeval - 1) >> 16;
  48. /*
  49. * Propagate 'one' bits to the right by 'oring' them.
  50. * We need only treat bits 15-0.
  51. */
  52. sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
  53. sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
  54. sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
  55. sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
  56. return sizeval;
  57. }
  58. /*
  59. * orion5x_config_adr_windows - Configure address Windows
  60. *
  61. * There are 8 address windows supported by Orion5x Soc to addess different
  62. * devices. Each window can be configured for size, BAR and remap addr
  63. * Below configuration is standard for most of the cases
  64. *
  65. * If remap function not used, remap_lo must be set as base
  66. *
  67. * NOTES:
  68. *
  69. * 1) in order to avoid windows with inconsistent control and base values
  70. * (which could prevent access to BOOTCS and hence execution from FLASH)
  71. * always disable window before writing the base value then reenable it
  72. * by writing the control value.
  73. *
  74. * 2) in order to avoid losing access to BOOTCS when disabling window 7,
  75. * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
  76. * then configure windows 6 for its own target.
  77. *
  78. * Reference Documentation:
  79. * Mbus-L to Mbus Bridge Registers Configuration.
  80. * (Sec 25.1 and 25.3 of Datasheet)
  81. */
  82. int orion5x_config_adr_windows(void)
  83. {
  84. struct orion5x_win_registers *winregs =
  85. (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
  86. /* Disable window 0, configure it for its intended target, enable it. */
  87. writel(0, &winregs[0].ctrl);
  88. writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
  89. writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
  90. writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
  91. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
  92. ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
  93. ORION5X_WIN_ENABLE), &winregs[0].ctrl);
  94. /* Disable window 1, configure it for its intended target, enable it. */
  95. writel(0, &winregs[1].ctrl);
  96. writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
  97. writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
  98. writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
  99. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
  100. ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
  101. ORION5X_WIN_ENABLE), &winregs[1].ctrl);
  102. /* Disable window 2, configure it for its intended target, enable it. */
  103. writel(0, &winregs[2].ctrl);
  104. writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
  105. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
  106. ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
  107. ORION5X_WIN_ENABLE), &winregs[2].ctrl);
  108. /* Disable window 3, configure it for its intended target, enable it. */
  109. writel(0, &winregs[3].ctrl);
  110. writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
  111. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
  112. ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
  113. ORION5X_WIN_ENABLE), &winregs[3].ctrl);
  114. /* Disable window 4, configure it for its intended target, enable it. */
  115. writel(0, &winregs[4].ctrl);
  116. writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
  117. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
  118. ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
  119. ORION5X_WIN_ENABLE), &winregs[4].ctrl);
  120. /* Disable window 5, configure it for its intended target, enable it. */
  121. writel(0, &winregs[5].ctrl);
  122. writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
  123. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
  124. ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
  125. ORION5X_WIN_ENABLE), &winregs[5].ctrl);
  126. /* Disable window 6, configure it for FLASH, enable it. */
  127. writel(0, &winregs[6].ctrl);
  128. writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
  129. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
  130. ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
  131. ORION5X_WIN_ENABLE), &winregs[6].ctrl);
  132. /* Disable window 7, configure it for FLASH, enable it. */
  133. writel(0, &winregs[7].ctrl);
  134. writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
  135. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
  136. ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
  137. ORION5X_WIN_ENABLE), &winregs[7].ctrl);
  138. /* Disable window 6, configure it for its intended target, enable it. */
  139. writel(0, &winregs[6].ctrl);
  140. writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
  141. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
  142. ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
  143. ORION5X_WIN_ENABLE), &winregs[6].ctrl);
  144. return 0;
  145. }
  146. /*
  147. * Orion5x identification is done through PCIE space.
  148. */
  149. u32 orion5x_device_id(void)
  150. {
  151. return readl(PCIE_DEV_ID_OFF) >> 16;
  152. }
  153. u32 orion5x_device_rev(void)
  154. {
  155. return readl(PCIE_DEV_REV_OFF) & 0xff;
  156. }
  157. #if defined(CONFIG_DISPLAY_CPUINFO)
  158. /* Display device and revision IDs.
  159. * This function must cover all known device/revision
  160. * combinations, not only the one for which u-boot is
  161. * compiled; this way, one can identify actual HW in
  162. * case of a mismatch.
  163. */
  164. int print_cpuinfo(void)
  165. {
  166. char dev_str[7]; /* room enough for 0x0000 plus null byte */
  167. char rev_str[5]; /* room enough for 0x00 plus null byte */
  168. char *dev_name = NULL;
  169. char *rev_name = NULL;
  170. u32 dev = orion5x_device_id();
  171. u32 rev = orion5x_device_rev();
  172. if (dev == MV88F5181_DEV_ID) {
  173. dev_name = "MV88F5181";
  174. if (rev == MV88F5181_REV_B1)
  175. rev_name = "B1";
  176. else if (rev == MV88F5181L_REV_A1) {
  177. dev_name = "MV88F5181L";
  178. rev_name = "A1";
  179. } else if (rev == MV88F5181L_REV_A0) {
  180. dev_name = "MV88F5181L";
  181. rev_name = "A0";
  182. }
  183. } else if (dev == MV88F5182_DEV_ID) {
  184. dev_name = "MV88F5182";
  185. if (rev == MV88F5182_REV_A2)
  186. rev_name = "A2";
  187. } else if (dev == MV88F5281_DEV_ID) {
  188. dev_name = "MV88F5281";
  189. if (rev == MV88F5281_REV_D2)
  190. rev_name = "D2";
  191. else if (rev == MV88F5281_REV_D1)
  192. rev_name = "D1";
  193. else if (rev == MV88F5281_REV_D0)
  194. rev_name = "D0";
  195. } else if (dev == MV88F6183_DEV_ID) {
  196. dev_name = "MV88F6183";
  197. if (rev == MV88F6183_REV_B0)
  198. rev_name = "B0";
  199. }
  200. if (dev_name == NULL) {
  201. sprintf(dev_str, "0x%04x", dev);
  202. dev_name = dev_str;
  203. }
  204. if (rev_name == NULL) {
  205. sprintf(rev_str, "0x%02x", rev);
  206. rev_name = rev_str;
  207. }
  208. printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
  209. return 0;
  210. }
  211. #endif /* CONFIG_DISPLAY_CPUINFO */
  212. #ifdef CONFIG_ARCH_CPU_INIT
  213. int arch_cpu_init(void)
  214. {
  215. /* Enable and invalidate L2 cache in write through mode */
  216. invalidate_l2_cache();
  217. #ifdef CONFIG_SPL_BUILD
  218. orion5x_config_adr_windows();
  219. #endif
  220. return 0;
  221. }
  222. #endif /* CONFIG_ARCH_CPU_INIT */
  223. /*
  224. * SOC specific misc init
  225. */
  226. #if defined(CONFIG_ARCH_MISC_INIT)
  227. int arch_misc_init(void)
  228. {
  229. u32 temp;
  230. /*CPU streaming & write allocate */
  231. temp = readfr_extra_feature_reg();
  232. temp &= ~(1 << 28); /* disable wr alloc */
  233. writefr_extra_feature_reg(temp);
  234. temp = readfr_extra_feature_reg();
  235. temp &= ~(1 << 29); /* streaming disabled */
  236. writefr_extra_feature_reg(temp);
  237. /* L2Cache settings */
  238. temp = readfr_extra_feature_reg();
  239. /* Disable L2C pre fetch - Set bit 24 */
  240. temp |= (1 << 24);
  241. /* enable L2C - Set bit 22 */
  242. temp |= (1 << 22);
  243. writefr_extra_feature_reg(temp);
  244. icache_enable();
  245. /* Change reset vector to address 0x0 */
  246. temp = get_cr();
  247. set_cr(temp & ~CR_V);
  248. /* Set CPIOs and MPPs - values provided by board
  249. include file */
  250. writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
  251. writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
  252. writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
  253. writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
  254. writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
  255. writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
  256. /* initialize timer */
  257. timer_init_r();
  258. return 0;
  259. }
  260. #endif /* CONFIG_ARCH_MISC_INIT */
  261. #ifdef CONFIG_MVGBE
  262. int cpu_eth_init(bd_t *bis)
  263. {
  264. mvgbe_initialize(bis);
  265. return 0;
  266. }
  267. #endif