board.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Common board functions for AM33XX based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <debug_uart.h>
  12. #include <errno.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <ns16550.h>
  16. #include <spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/i2c.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/io.h>
  28. #include <asm/emif.h>
  29. #include <asm/gpio.h>
  30. #include <asm/omap_common.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <linux/errno.h>
  35. #include <linux/compiler.h>
  36. #include <linux/usb/ch9.h>
  37. #include <linux/usb/gadget.h>
  38. #include <linux/usb/musb.h>
  39. #include <asm/omap_musb.h>
  40. #include <asm/davinci_rtc.h>
  41. #define AM43XX_EMIF_BASE 0x4C000000
  42. #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
  43. #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
  44. #define AM43XX_SDRAM_TYPE_SHIFT 29
  45. #define AM43XX_SDRAM_TYPE_DDR3 3
  46. #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
  47. #define AM43XX_RDWRLVLFULL_START 0x80000000
  48. DECLARE_GLOBAL_DATA_PTR;
  49. int dram_init(void)
  50. {
  51. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  52. sdram_init();
  53. #endif
  54. /* dram_init must store complete ramsize in gd->ram_size */
  55. gd->ram_size = get_ram_size(
  56. (void *)CONFIG_SYS_SDRAM_BASE,
  57. CONFIG_MAX_RAM_BANK_SIZE);
  58. return 0;
  59. }
  60. int dram_init_banksize(void)
  61. {
  62. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  63. gd->bd->bi_dram[0].size = gd->ram_size;
  64. return 0;
  65. }
  66. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  67. static const struct ns16550_platdata am33xx_serial[] = {
  68. { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  69. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  70. # ifdef CONFIG_SYS_NS16550_COM2
  71. { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  72. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  73. # ifdef CONFIG_SYS_NS16550_COM3
  74. { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  75. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  76. { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  77. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  78. { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  79. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  80. { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  81. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  82. # endif
  83. # endif
  84. };
  85. U_BOOT_DEVICES(am33xx_uarts) = {
  86. { "ns16550_serial", &am33xx_serial[0] },
  87. # ifdef CONFIG_SYS_NS16550_COM2
  88. { "ns16550_serial", &am33xx_serial[1] },
  89. # ifdef CONFIG_SYS_NS16550_COM3
  90. { "ns16550_serial", &am33xx_serial[2] },
  91. { "ns16550_serial", &am33xx_serial[3] },
  92. { "ns16550_serial", &am33xx_serial[4] },
  93. { "ns16550_serial", &am33xx_serial[5] },
  94. # endif
  95. # endif
  96. };
  97. #ifdef CONFIG_DM_I2C
  98. static const struct omap_i2c_platdata am33xx_i2c[] = {
  99. { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
  100. { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
  101. { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
  102. };
  103. U_BOOT_DEVICES(am33xx_i2c) = {
  104. { "i2c_omap", &am33xx_i2c[0] },
  105. { "i2c_omap", &am33xx_i2c[1] },
  106. { "i2c_omap", &am33xx_i2c[2] },
  107. };
  108. #endif
  109. #if CONFIG_IS_ENABLED(DM_GPIO)
  110. static const struct omap_gpio_platdata am33xx_gpio[] = {
  111. { 0, AM33XX_GPIO0_BASE },
  112. { 1, AM33XX_GPIO1_BASE },
  113. { 2, AM33XX_GPIO2_BASE },
  114. { 3, AM33XX_GPIO3_BASE },
  115. #ifdef CONFIG_AM43XX
  116. { 4, AM33XX_GPIO4_BASE },
  117. { 5, AM33XX_GPIO5_BASE },
  118. #endif
  119. };
  120. U_BOOT_DEVICES(am33xx_gpios) = {
  121. { "gpio_omap", &am33xx_gpio[0] },
  122. { "gpio_omap", &am33xx_gpio[1] },
  123. { "gpio_omap", &am33xx_gpio[2] },
  124. { "gpio_omap", &am33xx_gpio[3] },
  125. #ifdef CONFIG_AM43XX
  126. { "gpio_omap", &am33xx_gpio[4] },
  127. { "gpio_omap", &am33xx_gpio[5] },
  128. #endif
  129. };
  130. #endif
  131. #endif
  132. #if !CONFIG_IS_ENABLED(DM_GPIO)
  133. static const struct gpio_bank gpio_bank_am33xx[] = {
  134. { (void *)AM33XX_GPIO0_BASE },
  135. { (void *)AM33XX_GPIO1_BASE },
  136. { (void *)AM33XX_GPIO2_BASE },
  137. { (void *)AM33XX_GPIO3_BASE },
  138. #ifdef CONFIG_AM43XX
  139. { (void *)AM33XX_GPIO4_BASE },
  140. { (void *)AM33XX_GPIO5_BASE },
  141. #endif
  142. };
  143. const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  144. #endif
  145. #if defined(CONFIG_MMC_OMAP_HS)
  146. int cpu_mmc_init(bd_t *bis)
  147. {
  148. int ret;
  149. ret = omap_mmc_init(0, 0, 0, -1, -1);
  150. if (ret)
  151. return ret;
  152. return omap_mmc_init(1, 0, 0, -1, -1);
  153. }
  154. #endif
  155. /*
  156. * RTC only with DDR in self-refresh mode magic value, checked against during
  157. * boot to see if we have a valid config. This should be in sync with the value
  158. * that will be in drivers/soc/ti/pm33xx.c.
  159. */
  160. #define RTC_MAGIC_VAL 0x8cd0
  161. /* Board type field bit shift for RTC only with DDR in self-refresh mode */
  162. #define RTC_BOARD_TYPE_SHIFT 16
  163. /* AM33XX has two MUSB controllers which can be host or gadget */
  164. #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
  165. (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
  166. (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
  167. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
  168. static struct musb_hdrc_config musb_config = {
  169. .multipoint = 1,
  170. .dyn_fifo = 1,
  171. .num_eps = 16,
  172. .ram_bits = 12,
  173. };
  174. #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
  175. static struct ti_musb_platdata usb0 = {
  176. .base = (void *)USB0_OTG_BASE,
  177. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
  178. .plat = {
  179. .config = &musb_config,
  180. .power = 50,
  181. .platform_ops = &musb_dsps_ops,
  182. },
  183. };
  184. static struct ti_musb_platdata usb1 = {
  185. .base = (void *)USB1_OTG_BASE,
  186. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
  187. .plat = {
  188. .config = &musb_config,
  189. .power = 50,
  190. .platform_ops = &musb_dsps_ops,
  191. },
  192. };
  193. U_BOOT_DEVICES(am33xx_usbs) = {
  194. #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
  195. { "ti-musb-peripheral", &usb0 },
  196. #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
  197. { "ti-musb-host", &usb0 },
  198. #endif
  199. #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
  200. { "ti-musb-peripheral", &usb1 },
  201. #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
  202. { "ti-musb-host", &usb1 },
  203. #endif
  204. };
  205. int arch_misc_init(void)
  206. {
  207. return 0;
  208. }
  209. #else
  210. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  211. /* USB 2.0 PHY Control */
  212. #define CM_PHY_PWRDN (1 << 0)
  213. #define CM_PHY_OTG_PWRDN (1 << 1)
  214. #define OTGVDET_EN (1 << 19)
  215. #define OTGSESSENDEN (1 << 20)
  216. static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
  217. {
  218. if (on) {
  219. clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
  220. OTGVDET_EN | OTGSESSENDEN);
  221. } else {
  222. clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
  223. }
  224. }
  225. #ifdef CONFIG_AM335X_USB0
  226. static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
  227. {
  228. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
  229. }
  230. struct omap_musb_board_data otg0_board_data = {
  231. .set_phy_power = am33xx_otg0_set_phy_power,
  232. };
  233. static struct musb_hdrc_platform_data otg0_plat = {
  234. .mode = CONFIG_AM335X_USB0_MODE,
  235. .config = &musb_config,
  236. .power = 50,
  237. .platform_ops = &musb_dsps_ops,
  238. .board_data = &otg0_board_data,
  239. };
  240. #endif
  241. #ifdef CONFIG_AM335X_USB1
  242. static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
  243. {
  244. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
  245. }
  246. struct omap_musb_board_data otg1_board_data = {
  247. .set_phy_power = am33xx_otg1_set_phy_power,
  248. };
  249. static struct musb_hdrc_platform_data otg1_plat = {
  250. .mode = CONFIG_AM335X_USB1_MODE,
  251. .config = &musb_config,
  252. .power = 50,
  253. .platform_ops = &musb_dsps_ops,
  254. .board_data = &otg1_board_data,
  255. };
  256. #endif
  257. int arch_misc_init(void)
  258. {
  259. #ifdef CONFIG_AM335X_USB0
  260. musb_register(&otg0_plat, &otg0_board_data,
  261. (void *)USB0_OTG_BASE);
  262. #endif
  263. #ifdef CONFIG_AM335X_USB1
  264. musb_register(&otg1_plat, &otg1_board_data,
  265. (void *)USB1_OTG_BASE);
  266. #endif
  267. return 0;
  268. }
  269. #endif
  270. #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  271. int arch_misc_init(void)
  272. {
  273. struct udevice *dev;
  274. int ret;
  275. ret = uclass_first_device(UCLASS_MISC, &dev);
  276. if (ret || !dev)
  277. return ret;
  278. #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
  279. ret = usb_ether_init();
  280. if (ret) {
  281. pr_err("USB ether init failed\n");
  282. return ret;
  283. }
  284. #endif
  285. return 0;
  286. }
  287. #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  288. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  289. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
  290. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
  291. static void rtc32k_unlock(struct davinci_rtc *rtc)
  292. {
  293. /*
  294. * Unlock the RTC's registers. For more details please see the
  295. * RTC_SS section of the TRM. In order to unlock we need to
  296. * write these specific values (keys) in this order.
  297. */
  298. writel(RTC_KICK0R_WE, &rtc->kick0r);
  299. writel(RTC_KICK1R_WE, &rtc->kick1r);
  300. }
  301. #endif
  302. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  303. /*
  304. * Write contents of the RTC_SCRATCH1 register based on board type
  305. * Two things are passed
  306. * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
  307. * control gets to kernel, kernel reads the scratchpad register and gets to
  308. * know that bootloader has rtc_only support.
  309. *
  310. * Second important thing is the board type (16:31). This is needed in the
  311. * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
  312. * identify the board type and we go ahead and copy the board strings to
  313. * am43xx_board_name.
  314. */
  315. void update_rtc_magic(void)
  316. {
  317. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  318. u32 magic = RTC_MAGIC_VAL;
  319. magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
  320. rtc32k_unlock(rtc);
  321. /* write magic */
  322. writel(magic, &rtc->scratch1);
  323. }
  324. #endif
  325. /*
  326. * In the case of non-SPL based booting we'll want to call these
  327. * functions a tiny bit later as it will require gd to be set and cleared
  328. * and that's not true in s_init in this case so we cannot do it there.
  329. */
  330. int board_early_init_f(void)
  331. {
  332. set_mux_conf_regs();
  333. prcm_init();
  334. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  335. update_rtc_magic();
  336. #endif
  337. return 0;
  338. }
  339. /*
  340. * This function is the place to do per-board things such as ramp up the
  341. * MPU clock frequency.
  342. */
  343. __weak void am33xx_spl_board_init(void)
  344. {
  345. }
  346. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  347. static void rtc32k_enable(void)
  348. {
  349. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  350. rtc32k_unlock(rtc);
  351. /* Enable the RTC 32K OSC by setting bits 3 and 6. */
  352. writel((1 << 3) | (1 << 6), &rtc->osc);
  353. }
  354. #endif
  355. static void uart_soft_reset(void)
  356. {
  357. struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  358. u32 regval;
  359. regval = readl(&uart_base->uartsyscfg);
  360. regval |= UART_RESET;
  361. writel(regval, &uart_base->uartsyscfg);
  362. while ((readl(&uart_base->uartsyssts) &
  363. UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  364. ;
  365. /* Disable smart idle */
  366. regval = readl(&uart_base->uartsyscfg);
  367. regval |= UART_SMART_IDLE_EN;
  368. writel(regval, &uart_base->uartsyscfg);
  369. }
  370. static void watchdog_disable(void)
  371. {
  372. struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  373. writel(0xAAAA, &wdtimer->wdtwspr);
  374. while (readl(&wdtimer->wdtwwps) != 0x0)
  375. ;
  376. writel(0x5555, &wdtimer->wdtwspr);
  377. while (readl(&wdtimer->wdtwwps) != 0x0)
  378. ;
  379. }
  380. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  381. /*
  382. * Check if we are executing rtc-only + DDR mode, and resume from it if needed
  383. */
  384. static void rtc_only(void)
  385. {
  386. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  387. struct prm_device_inst *prm_device =
  388. (struct prm_device_inst *)PRM_DEVICE_INST;
  389. u32 scratch1, sdrc;
  390. void (*resume_func)(void);
  391. scratch1 = readl(&rtc->scratch1);
  392. /*
  393. * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
  394. * written to this register when we want to wake up from RTC only
  395. * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
  396. * bits 0-15: RTC_MAGIC_VAL
  397. * bits 16-31: board type (needed for sdram_init)
  398. */
  399. if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
  400. return;
  401. rtc32k_unlock(rtc);
  402. /* Clear RTC magic */
  403. writel(0, &rtc->scratch1);
  404. /*
  405. * Update board type based on value stored on RTC_SCRATCH1, this
  406. * is done so that we don't need to read the board type from eeprom
  407. * over i2c bus which is expensive
  408. */
  409. rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
  410. /*
  411. * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
  412. * are resuming from self-refresh. This avoids an unnecessary re-init
  413. * of the DDR. The re-init takes time and we would need to wait for
  414. * it to complete before accessing DDR to avoid L3 NOC errors.
  415. */
  416. writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
  417. rtc_only_prcm_init();
  418. sdram_init();
  419. /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
  420. /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
  421. sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
  422. sdrc &= AM43XX_SDRAM_TYPE_MASK;
  423. sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
  424. if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
  425. writel(AM43XX_RDWRLVLFULL_START,
  426. AM43XX_EMIF_BASE +
  427. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  428. mdelay(1);
  429. am43xx_wait:
  430. sdrc = readl(AM43XX_EMIF_BASE +
  431. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  432. if (sdrc == AM43XX_RDWRLVLFULL_START)
  433. goto am43xx_wait;
  434. }
  435. resume_func = (void *)readl(&rtc->scratch0);
  436. if (resume_func)
  437. resume_func();
  438. }
  439. #endif
  440. void s_init(void)
  441. {
  442. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  443. rtc_only();
  444. #endif
  445. }
  446. void early_system_init(void)
  447. {
  448. /*
  449. * The ROM will only have set up sufficient pinmux to allow for the
  450. * first 4KiB NOR to be read, we must finish doing what we know of
  451. * the NOR mux in this space in order to continue.
  452. */
  453. #ifdef CONFIG_NOR_BOOT
  454. enable_norboot_pin_mux();
  455. #endif
  456. watchdog_disable();
  457. set_uart_mux_conf();
  458. setup_early_clocks();
  459. uart_soft_reset();
  460. #ifdef CONFIG_SPL_BUILD
  461. /*
  462. * Save the boot parameters passed from romcode.
  463. * We cannot delay the saving further than this,
  464. * to prevent overwrites.
  465. */
  466. save_omap_boot_params();
  467. #endif
  468. #ifdef CONFIG_DEBUG_UART_OMAP
  469. debug_uart_init();
  470. #endif
  471. #ifdef CONFIG_SPL_BUILD
  472. spl_early_init();
  473. #endif
  474. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  475. do_board_detect();
  476. #endif
  477. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  478. /* Enable RTC32K clock */
  479. rtc32k_enable();
  480. #endif
  481. }
  482. #ifdef CONFIG_SPL_BUILD
  483. void board_init_f(ulong dummy)
  484. {
  485. hw_data_init();
  486. early_system_init();
  487. board_early_init_f();
  488. sdram_init();
  489. /* dram_init must store complete ramsize in gd->ram_size */
  490. gd->ram_size = get_ram_size(
  491. (void *)CONFIG_SYS_SDRAM_BASE,
  492. CONFIG_MAX_RAM_BANK_SIZE);
  493. }
  494. #endif
  495. #endif
  496. int arch_cpu_init_dm(void)
  497. {
  498. hw_data_init();
  499. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  500. early_system_init();
  501. #endif
  502. return 0;
  503. }