board-g12a.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/boot.h>
  10. #include <asm/arch/eth.h>
  11. #include <asm/arch/g12a.h>
  12. #include <asm/arch/mem.h>
  13. #include <asm/arch/meson-vpu.h>
  14. #include <asm/io.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <linux/sizes.h>
  17. #include <usb.h>
  18. #include <linux/usb/otg.h>
  19. #include <asm/arch/usb.h>
  20. #include <usb/dwc2_udc.h>
  21. #include <phy.h>
  22. #include <clk.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int meson_get_boot_device(void)
  25. {
  26. return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
  27. }
  28. /* Configure the reserved memory zones exported by the secure registers
  29. * into EFI and DTB reserved memory entries.
  30. */
  31. void meson_init_reserved_memory(void *fdt)
  32. {
  33. u64 bl31_size, bl31_start;
  34. u64 bl32_size, bl32_start;
  35. u32 reg;
  36. /*
  37. * Get ARM Trusted Firmware reserved memory zones in :
  38. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  39. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  40. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  41. */
  42. reg = readl(G12A_AO_SEC_GP_CFG3);
  43. bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
  44. >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  45. bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  46. bl31_start = readl(G12A_AO_SEC_GP_CFG5);
  47. bl32_start = readl(G12A_AO_SEC_GP_CFG4);
  48. /* Add BL31 reserved zone */
  49. if (bl31_start && bl31_size)
  50. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  51. /* Add BL32 reserved zone */
  52. if (bl32_start && bl32_size)
  53. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  54. #if defined(CONFIG_VIDEO_MESON)
  55. meson_vpu_rsv_fb(fdt);
  56. #endif
  57. }
  58. phys_size_t get_effective_memsize(void)
  59. {
  60. /* Size is reported in MiB, convert it in bytes */
  61. return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
  62. >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
  63. }
  64. static struct mm_region g12a_mem_map[] = {
  65. {
  66. .virt = 0x0UL,
  67. .phys = 0x0UL,
  68. .size = 0xf5000000UL,
  69. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  70. PTE_BLOCK_INNER_SHARE
  71. }, {
  72. .virt = 0xf5000000UL,
  73. .phys = 0xf5000000UL,
  74. .size = 0x0b000000UL,
  75. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  76. PTE_BLOCK_NON_SHARE |
  77. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  78. }, {
  79. /* List terminator */
  80. 0,
  81. }
  82. };
  83. struct mm_region *mem_map = g12a_mem_map;
  84. static void g12a_enable_external_mdio(void)
  85. {
  86. writel(0x0, ETH_PHY_CNTL2);
  87. }
  88. static void g12a_enable_internal_mdio(void)
  89. {
  90. /* Fire up the PHY PLL */
  91. writel(0x29c0040a, ETH_PLL_CNTL0);
  92. writel(0x927e0000, ETH_PLL_CNTL1);
  93. writel(0xac5f49e5, ETH_PLL_CNTL2);
  94. writel(0x00000000, ETH_PLL_CNTL3);
  95. writel(0x00000000, ETH_PLL_CNTL4);
  96. writel(0x20200000, ETH_PLL_CNTL5);
  97. writel(0x0000c002, ETH_PLL_CNTL6);
  98. writel(0x00000023, ETH_PLL_CNTL7);
  99. writel(0x39c0040a, ETH_PLL_CNTL0);
  100. writel(0x19c0040a, ETH_PLL_CNTL0);
  101. /* Select the internal MDIO */
  102. writel(0x33000180, ETH_PHY_CNTL0);
  103. writel(0x00074043, ETH_PHY_CNTL1);
  104. writel(0x00000260, ETH_PHY_CNTL2);
  105. }
  106. /* Configure the Ethernet MAC with the requested interface mode
  107. * with some optional flags.
  108. */
  109. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  110. {
  111. switch (mode) {
  112. case PHY_INTERFACE_MODE_RGMII:
  113. case PHY_INTERFACE_MODE_RGMII_ID:
  114. case PHY_INTERFACE_MODE_RGMII_RXID:
  115. case PHY_INTERFACE_MODE_RGMII_TXID:
  116. /* Set RGMII mode */
  117. setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
  118. G12A_ETH_REG_0_TX_PHASE(1) |
  119. G12A_ETH_REG_0_TX_RATIO(4) |
  120. G12A_ETH_REG_0_PHY_CLK_EN |
  121. G12A_ETH_REG_0_CLK_EN);
  122. g12a_enable_external_mdio();
  123. break;
  124. case PHY_INTERFACE_MODE_RMII:
  125. /* Set RMII mode */
  126. out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
  127. G12A_ETH_REG_0_INVERT_RMII_CLK |
  128. G12A_ETH_REG_0_CLK_EN);
  129. /* Use G12A RMII Internal PHY */
  130. if (flags & MESON_USE_INTERNAL_RMII_PHY)
  131. g12a_enable_internal_mdio();
  132. else
  133. g12a_enable_external_mdio();
  134. break;
  135. default:
  136. printf("Invalid Ethernet interface mode\n");
  137. return;
  138. }
  139. /* Enable power gate */
  140. clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
  141. }
  142. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
  143. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  144. static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
  145. int board_usb_init(int index, enum usb_init_type init)
  146. {
  147. struct fdtdec_phandle_args args;
  148. const void *blob = gd->fdt_blob;
  149. int node, dwc2_node;
  150. struct udevice *dev, *clk_dev;
  151. struct clk clk;
  152. int ret;
  153. /* find the usb glue node */
  154. node = fdt_node_offset_by_compatible(blob, -1,
  155. "amlogic,meson-g12a-usb-ctrl");
  156. if (node < 0) {
  157. debug("Not found usb-control node\n");
  158. return -ENODEV;
  159. }
  160. if (!fdtdec_get_is_enabled(blob, node)) {
  161. debug("usb is disabled in the device tree\n");
  162. return -ENODEV;
  163. }
  164. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  165. if (ret) {
  166. debug("Not found usb-control device\n");
  167. return ret;
  168. }
  169. /* find the dwc2 node */
  170. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  171. "amlogic,meson-g12a-usb");
  172. if (dwc2_node < 0) {
  173. debug("Not found dwc2 node\n");
  174. return -ENODEV;
  175. }
  176. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  177. debug("dwc2 is disabled in the device tree\n");
  178. return -ENODEV;
  179. }
  180. meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  181. if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  182. debug("usbotg: can't get base address\n");
  183. return -ENODATA;
  184. }
  185. /* Enable clock */
  186. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  187. "#clock-cells", 0, 0, &args);
  188. if (ret) {
  189. debug("usbotg has no clocks defined in the device tree\n");
  190. return ret;
  191. }
  192. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  193. if (ret)
  194. return ret;
  195. if (args.args_count != 1) {
  196. debug("Can't find clock ID in the device tree\n");
  197. return -ENODATA;
  198. }
  199. clk.dev = clk_dev;
  200. clk.id = args.args[0];
  201. ret = clk_enable(&clk);
  202. if (ret) {
  203. debug("Failed to enable usbotg clock\n");
  204. return ret;
  205. }
  206. meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  207. "g-rx-fifo-size", 0);
  208. meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  209. "g-np-tx-fifo-size", 0);
  210. meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  211. "g-tx-fifo-size", 0);
  212. /* Switch to peripheral mode */
  213. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  214. if (ret)
  215. return ret;
  216. return dwc2_udc_probe(&meson_g12a_dwc2_data);
  217. }
  218. int board_usb_cleanup(int index, enum usb_init_type init)
  219. {
  220. const void *blob = gd->fdt_blob;
  221. struct udevice *dev;
  222. int node;
  223. int ret;
  224. /* find the usb glue node */
  225. node = fdt_node_offset_by_compatible(blob, -1,
  226. "amlogic,meson-g12a-usb-ctrl");
  227. if (node < 0)
  228. return -ENODEV;
  229. if (!fdtdec_get_is_enabled(blob, node))
  230. return -ENODEV;
  231. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  232. if (ret)
  233. return ret;
  234. /* Switch to OTG mode */
  235. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
  236. if (ret)
  237. return ret;
  238. return 0;
  239. }
  240. #endif