board-axg.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/boot.h>
  10. #include <asm/arch/eth.h>
  11. #include <asm/arch/axg.h>
  12. #include <asm/arch/mem.h>
  13. #include <asm/io.h>
  14. #include <asm/armv8/mmu.h>
  15. #include <linux/sizes.h>
  16. #include <phy.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int meson_get_boot_device(void)
  19. {
  20. return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
  21. }
  22. /* Configure the reserved memory zones exported by the secure registers
  23. * into EFI and DTB reserved memory entries.
  24. */
  25. void meson_init_reserved_memory(void *fdt)
  26. {
  27. u64 bl31_size, bl31_start;
  28. u64 bl32_size, bl32_start;
  29. u32 reg;
  30. /*
  31. * Get ARM Trusted Firmware reserved memory zones in :
  32. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  33. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  34. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  35. */
  36. reg = readl(AXG_AO_SEC_GP_CFG3);
  37. bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
  38. >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  39. bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  40. bl31_start = readl(AXG_AO_SEC_GP_CFG5);
  41. bl32_start = readl(AXG_AO_SEC_GP_CFG4);
  42. /* Add BL31 reserved zone */
  43. if (bl31_start && bl31_size)
  44. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  45. /* Add BL32 reserved zone */
  46. if (bl32_start && bl32_size)
  47. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  48. }
  49. phys_size_t get_effective_memsize(void)
  50. {
  51. /* Size is reported in MiB, convert it in bytes */
  52. return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
  53. >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
  54. }
  55. static struct mm_region axg_mem_map[] = {
  56. {
  57. .virt = 0x0UL,
  58. .phys = 0x0UL,
  59. .size = 0x80000000UL,
  60. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  61. PTE_BLOCK_INNER_SHARE
  62. }, {
  63. .virt = 0xf0000000UL,
  64. .phys = 0xf0000000UL,
  65. .size = 0x10000000UL,
  66. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  67. PTE_BLOCK_NON_SHARE |
  68. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  69. }, {
  70. /* List terminator */
  71. 0,
  72. }
  73. };
  74. struct mm_region *mem_map = axg_mem_map;
  75. /* Configure the Ethernet MAC with the requested interface mode
  76. * with some optional flags.
  77. */
  78. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  79. {
  80. switch (mode) {
  81. case PHY_INTERFACE_MODE_RGMII:
  82. case PHY_INTERFACE_MODE_RGMII_ID:
  83. case PHY_INTERFACE_MODE_RGMII_RXID:
  84. case PHY_INTERFACE_MODE_RGMII_TXID:
  85. /* Set RGMII mode */
  86. setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  87. AXG_ETH_REG_0_TX_PHASE(1) |
  88. AXG_ETH_REG_0_TX_RATIO(4) |
  89. AXG_ETH_REG_0_PHY_CLK_EN |
  90. AXG_ETH_REG_0_CLK_EN);
  91. break;
  92. case PHY_INTERFACE_MODE_RMII:
  93. /* Set RMII mode */
  94. out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
  95. AXG_ETH_REG_0_INVERT_RMII_CLK |
  96. AXG_ETH_REG_0_CLK_EN);
  97. break;
  98. default:
  99. printf("Invalid Ethernet interface mode\n");
  100. return;
  101. }
  102. /* Enable power gate */
  103. clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
  104. }