init.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Configuration for MediaTek MT8518 SoC
  4. *
  5. * Copyright (C) 2019 MediaTek Inc.
  6. * Author: Mingming Lee <mingming.lee@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <fdtdec.h>
  13. #include <ram.h>
  14. #include <asm/arch/misc.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <asm/cache.h>
  17. #include <asm/sections.h>
  18. #include <dm/uclass.h>
  19. #include <dt-bindings/clock/mt8518-clk.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int dram_init(void)
  22. {
  23. int ret;
  24. ret = fdtdec_setup_memory_banksize();
  25. if (ret)
  26. return ret;
  27. return fdtdec_setup_mem_size_base();
  28. }
  29. int dram_init_banksize(void)
  30. {
  31. gd->bd->bi_dram[0].start = gd->ram_base;
  32. gd->bd->bi_dram[0].size = gd->ram_size;
  33. return 0;
  34. }
  35. void reset_cpu(ulong addr)
  36. {
  37. psci_system_reset();
  38. }
  39. int print_cpuinfo(void)
  40. {
  41. printf("CPU: MediaTek MT8518\n");
  42. return 0;
  43. }
  44. static struct mm_region mt8518_mem_map[] = {
  45. {
  46. /* DDR */
  47. .virt = 0x40000000UL,
  48. .phys = 0x40000000UL,
  49. .size = 0x20000000UL,
  50. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  51. }, {
  52. .virt = 0x00000000UL,
  53. .phys = 0x00000000UL,
  54. .size = 0x20000000UL,
  55. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56. PTE_BLOCK_NON_SHARE |
  57. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58. }, {
  59. 0,
  60. }
  61. };
  62. struct mm_region *mem_map = mt8518_mem_map;