cpu.c 1.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <net.h>
  8. #include <netdev.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/clk.h>
  11. #include <asm/arch/wdt.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/io.h>
  14. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  15. static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
  16. void reset_cpu(ulong addr)
  17. {
  18. /* Enable watchdog clock */
  19. setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
  20. /* To be compatible with the original U-Boot code:
  21. * addr: - 0: perform hard reset.
  22. * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
  23. if (addr == 0) {
  24. /* Reset pulse length is 13005 peripheral clock frames */
  25. writel(13000, &wdt->pulse);
  26. /* Force WDOG_RESET2 and RESOUT_N signal active */
  27. writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
  28. | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
  29. } else {
  30. /* Force match output active */
  31. writel(0x01, &wdt->emr);
  32. /* Internal reset on match output (no pulse on "RESOUT_N") */
  33. writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
  34. }
  35. while (1)
  36. /* NOP */;
  37. }
  38. #if defined(CONFIG_ARCH_CPU_INIT)
  39. int arch_cpu_init(void)
  40. {
  41. /*
  42. * It might be necessary to flush data cache, if U-Boot is loaded
  43. * from kickstart bootloader, e.g. from S1L loader
  44. */
  45. flush_dcache_all();
  46. return 0;
  47. }
  48. #else
  49. #error "You have to select CONFIG_ARCH_CPU_INIT"
  50. #endif
  51. #if defined(CONFIG_DISPLAY_CPUINFO)
  52. int print_cpuinfo(void)
  53. {
  54. printf("CPU: NXP LPC32XX\n");
  55. printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
  56. printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
  57. printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
  58. return 0;
  59. }
  60. #endif
  61. #ifdef CONFIG_LPC32XX_ETH
  62. int cpu_eth_init(bd_t *bis)
  63. {
  64. lpc32xx_eth_initialize(bis);
  65. return 0;
  66. }
  67. #endif