psci-mx7.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #include <cpu_func.h>
  7. #include <asm/cache.h>
  8. #include <asm/io.h>
  9. #include <asm/psci.h>
  10. #include <asm/secure.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/armv7.h>
  13. #include <asm/gic.h>
  14. #include <linux/bitops.h>
  15. #include <common.h>
  16. #include <fsl_wdog.h>
  17. #define GPC_LPCR_A7_BSC 0x0
  18. #define GPC_LPCR_A7_AD 0x4
  19. #define GPC_SLPCR 0x14
  20. #define GPC_PGC_ACK_SEL_A7 0x24
  21. #define GPC_IMR1_CORE0 0x30
  22. #define GPC_SLOT0_CFG 0xb0
  23. #define GPC_CPU_PGC_SW_PUP_REQ 0xf0
  24. #define GPC_CPU_PGC_SW_PDN_REQ 0xfc
  25. #define GPC_PGC_C0 0x800
  26. #define GPC_PGC_C0 0x800
  27. #define GPC_PGC_C1 0x840
  28. #define GPC_PGC_SCU 0x880
  29. #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
  30. #define BM_LPCR_A7_BSC_LPM1 0xc
  31. #define BM_LPCR_A7_BSC_LPM0 0x3
  32. #define BP_LPCR_A7_BSC_LPM0 0
  33. #define BM_SLPCR_EN_DSM 0x80000000
  34. #define BM_SLPCR_RBC_EN 0x40000000
  35. #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
  36. #define BM_SLPCR_VSTBY 0x4
  37. #define BM_SLPCR_SBYOS 0x2
  38. #define BM_SLPCR_BYPASS_PMIC_READY 0x1
  39. #define BM_LPCR_A7_AD_L2PGE 0x10000
  40. #define BM_LPCR_A7_AD_EN_C1_PUP 0x800
  41. #define BM_LPCR_A7_AD_EN_C0_PUP 0x200
  42. #define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10
  43. #define BM_LPCR_A7_AD_EN_C1_PDN 0x8
  44. #define BM_LPCR_A7_AD_EN_C0_PDN 0x2
  45. #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1
  46. #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
  47. #define BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK 0x8000
  48. #define BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK 0x80000000
  49. #define MAX_SLOT_NUMBER 10
  50. #define A7_LPM_WAIT 0x5
  51. #define A7_LPM_STOP 0xa
  52. #define BM_SYS_COUNTER_CNTCR_FCR1 0x200
  53. #define BM_SYS_COUNTER_CNTCR_FCR0 0x100
  54. #define REG_SET 0x4
  55. #define REG_CLR 0x8
  56. #define ANADIG_ARM_PLL 0x60
  57. #define ANADIG_DDR_PLL 0x70
  58. #define ANADIG_SYS_PLL 0xb0
  59. #define ANADIG_ENET_PLL 0xe0
  60. #define ANADIG_AUDIO_PLL 0xf0
  61. #define ANADIG_VIDEO_PLL 0x130
  62. #define BM_ANATOP_ARM_PLL_OVERRIDE BIT(20)
  63. #define BM_ANATOP_DDR_PLL_OVERRIDE BIT(19)
  64. #define BM_ANATOP_SYS_PLL_OVERRIDE (0x1ff << 17)
  65. #define BM_ANATOP_ENET_PLL_OVERRIDE BIT(13)
  66. #define BM_ANATOP_AUDIO_PLL_OVERRIDE BIT(24)
  67. #define BM_ANATOP_VIDEO_PLL_OVERRIDE BIT(24)
  68. #define DDRC_STAT 0x4
  69. #define DDRC_PWRCTL 0x30
  70. #define DDRC_PSTAT 0x3fc
  71. #define SRC_GPR1_MX7D 0x074
  72. #define SRC_GPR2_MX7D 0x078
  73. #define SRC_A7RCR0 0x004
  74. #define SRC_A7RCR1 0x008
  75. #define BP_SRC_A7RCR0_A7_CORE_RESET0 0
  76. #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
  77. #define SNVS_LPCR 0x38
  78. #define BP_SNVS_LPCR_DP_EN 0x20
  79. #define BP_SNVS_LPCR_TOP 0x40
  80. #define CCM_CCGR_SNVS 0x4250
  81. #define CCM_ROOT_WDOG 0xbb80
  82. #define CCM_CCGR_WDOG1 0x49c0
  83. #define MPIDR_AFF0 GENMASK(7, 0)
  84. #define IMX7D_PSCI_NR_CPUS 2
  85. #if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
  86. #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
  87. #endif
  88. #define imx_cpu_gpr_entry_offset(cpu) \
  89. (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
  90. #define imx_cpu_gpr_para_offset(cpu) \
  91. (imx_cpu_gpr_entry_offset(cpu) + 4)
  92. #define IMX_CPU_SYNC_OFF ~0
  93. #define IMX_CPU_SYNC_ON 0
  94. u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = {
  95. PSCI_AFFINITY_LEVEL_ON,
  96. PSCI_AFFINITY_LEVEL_OFF};
  97. enum imx_gpc_slot {
  98. CORE0_A7,
  99. CORE1_A7,
  100. SCU_A7,
  101. FAST_MEGA_MIX,
  102. MIPI_PHY,
  103. PCIE_PHY,
  104. USB_OTG1_PHY,
  105. USB_OTG2_PHY,
  106. USB_HSIC_PHY,
  107. CORE0_M4,
  108. };
  109. enum mxc_cpu_pwr_mode {
  110. RUN,
  111. WAIT,
  112. STOP,
  113. };
  114. extern void psci_system_resume(void);
  115. static inline void psci_set_state(int cpu, u8 state)
  116. {
  117. psci_state[cpu] = state;
  118. dsb();
  119. isb();
  120. }
  121. static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
  122. {
  123. writel(enable, GPC_IPS_BASE_ADDR + offset);
  124. }
  125. __secure void imx_gpcv2_set_core_power(int cpu, bool pdn)
  126. {
  127. u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
  128. u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0;
  129. u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 :
  130. BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7;
  131. u32 val;
  132. imx_gpcv2_set_m_core_pgc(true, pgc);
  133. val = readl(GPC_IPS_BASE_ADDR + reg);
  134. val |= pdn_pup_req;
  135. writel(val, GPC_IPS_BASE_ADDR + reg);
  136. while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0)
  137. ;
  138. imx_gpcv2_set_m_core_pgc(false, pgc);
  139. }
  140. __secure void imx_enable_cpu_ca7(int cpu, bool enable)
  141. {
  142. u32 mask, val;
  143. mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
  144. val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
  145. val = enable ? val | mask : val & ~mask;
  146. writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
  147. }
  148. __secure void psci_arch_cpu_entry(void)
  149. {
  150. u32 cpu = psci_get_cpu_id();
  151. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
  152. }
  153. __secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep,
  154. u32 context_id)
  155. {
  156. u32 cpu = mpidr & MPIDR_AFF0;
  157. if (mpidr & ~MPIDR_AFF0)
  158. return ARM_PSCI_RET_INVAL;
  159. if (cpu >= IMX7D_PSCI_NR_CPUS)
  160. return ARM_PSCI_RET_INVAL;
  161. if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
  162. return ARM_PSCI_RET_ALREADY_ON;
  163. if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
  164. return ARM_PSCI_RET_ON_PENDING;
  165. psci_save(cpu, ep, context_id);
  166. writel((u32)psci_cpu_entry, imx_cpu_gpr_entry_offset(cpu));
  167. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
  168. imx_gpcv2_set_core_power(cpu, true);
  169. imx_enable_cpu_ca7(cpu, true);
  170. return ARM_PSCI_RET_SUCCESS;
  171. }
  172. __secure s32 psci_cpu_off(void)
  173. {
  174. int cpu;
  175. cpu = psci_get_cpu_id();
  176. psci_cpu_off_common();
  177. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
  178. imx_enable_cpu_ca7(cpu, false);
  179. imx_gpcv2_set_core_power(cpu, false);
  180. /*
  181. * We use the cpu jumping argument register to sync with
  182. * psci_affinity_info() which is running on cpu0 to kill the cpu.
  183. */
  184. writel(IMX_CPU_SYNC_OFF, imx_cpu_gpr_para_offset(cpu));
  185. while (1)
  186. wfi();
  187. }
  188. __secure void psci_system_reset(void)
  189. {
  190. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  191. /* make sure WDOG1 clock is enabled */
  192. writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
  193. writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
  194. writew(WCR_WDE, &wdog->wcr);
  195. while (1)
  196. wfi();
  197. }
  198. __secure void psci_system_off(void)
  199. {
  200. u32 val;
  201. /* make sure SNVS clock is enabled */
  202. writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
  203. val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
  204. val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
  205. writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
  206. while (1)
  207. wfi();
  208. }
  209. __secure u32 psci_version(void)
  210. {
  211. return ARM_PSCI_VER_1_0;
  212. }
  213. __secure s32 psci_cpu_suspend(u32 __always_unused function_id, u32 power_state,
  214. u32 entry_point_address,
  215. u32 context_id)
  216. {
  217. return ARM_PSCI_RET_INVAL;
  218. }
  219. __secure s32 psci_affinity_info(u32 __always_unused function_id,
  220. u32 target_affinity,
  221. u32 lowest_affinity_level)
  222. {
  223. u32 cpu = target_affinity & MPIDR_AFF0;
  224. if (lowest_affinity_level > 0)
  225. return ARM_PSCI_RET_INVAL;
  226. if (target_affinity & ~MPIDR_AFF0)
  227. return ARM_PSCI_RET_INVAL;
  228. if (cpu >= IMX7D_PSCI_NR_CPUS)
  229. return ARM_PSCI_RET_INVAL;
  230. /* CPU is waiting for killed */
  231. if (readl(imx_cpu_gpr_para_offset(cpu)) == IMX_CPU_SYNC_OFF) {
  232. imx_enable_cpu_ca7(cpu, false);
  233. imx_gpcv2_set_core_power(cpu, false);
  234. writel(IMX_CPU_SYNC_ON, imx_cpu_gpr_para_offset(cpu));
  235. }
  236. return psci_state[cpu];
  237. }
  238. __secure u32 psci_migrate_info_type(void)
  239. {
  240. /* Trusted OS is either not present or does not require migration */
  241. return 2;
  242. }
  243. __secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
  244. {
  245. switch (psci_fid) {
  246. case ARM_PSCI_0_2_FN_PSCI_VERSION:
  247. case ARM_PSCI_0_2_FN_CPU_OFF:
  248. case ARM_PSCI_0_2_FN_CPU_ON:
  249. case ARM_PSCI_0_2_FN_AFFINITY_INFO:
  250. case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
  251. case ARM_PSCI_0_2_FN_SYSTEM_OFF:
  252. case ARM_PSCI_0_2_FN_SYSTEM_RESET:
  253. case ARM_PSCI_1_0_FN_PSCI_FEATURES:
  254. case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
  255. return 0x0;
  256. }
  257. return ARM_PSCI_RET_NI;
  258. }
  259. static __secure void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode)
  260. {
  261. u32 val1, val2, val3;
  262. val1 = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  263. val2 = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  264. /* all cores' LPM settings must be same */
  265. val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1);
  266. val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
  267. val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
  268. BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY);
  269. /*
  270. * GPC: When improper low-power sequence is used,
  271. * the SoC enters low power mode before the ARM core executes WFI.
  272. *
  273. * Software workaround:
  274. * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
  275. * by setting IOMUX_GPR1_IRQ.
  276. * 2) Software should then unmask IRQ #32 in GPC before setting GPC
  277. * Low-Power mode.
  278. * 3) Software should mask IRQ #32 right after GPC Low-Power mode
  279. * is set.
  280. */
  281. switch (mode) {
  282. case RUN:
  283. val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
  284. val3 &= ~0x1;
  285. writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
  286. break;
  287. case WAIT:
  288. val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0;
  289. val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
  290. val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
  291. val3 &= ~0x1;
  292. writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
  293. break;
  294. case STOP:
  295. val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0;
  296. val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
  297. val2 |= BM_SLPCR_EN_DSM;
  298. val2 |= BM_SLPCR_SBYOS;
  299. val2 |= BM_SLPCR_VSTBY;
  300. val2 |= BM_SLPCR_BYPASS_PMIC_READY;
  301. val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
  302. val3 |= 0x1;
  303. writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
  304. break;
  305. default:
  306. return;
  307. }
  308. writel(val1, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  309. writel(val2, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  310. }
  311. static __secure void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn)
  312. {
  313. u32 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
  314. val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE);
  315. if (pdn)
  316. val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE;
  317. writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
  318. }
  319. static __secure void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn)
  320. {
  321. u32 val;
  322. val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
  323. if (cpu == 0) {
  324. if (pdn)
  325. val |= BM_LPCR_A7_AD_EN_C0_PDN |
  326. BM_LPCR_A7_AD_EN_C0_PUP;
  327. else
  328. val &= ~(BM_LPCR_A7_AD_EN_C0_PDN |
  329. BM_LPCR_A7_AD_EN_C0_PUP);
  330. }
  331. if (cpu == 1) {
  332. if (pdn)
  333. val |= BM_LPCR_A7_AD_EN_C1_PDN |
  334. BM_LPCR_A7_AD_EN_C1_PUP;
  335. else
  336. val &= ~(BM_LPCR_A7_AD_EN_C1_PDN |
  337. BM_LPCR_A7_AD_EN_C1_PUP);
  338. }
  339. writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
  340. }
  341. static __secure void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core,
  342. bool mode, bool ack)
  343. {
  344. u32 val;
  345. if (index >= MAX_SLOT_NUMBER)
  346. return;
  347. /* set slot */
  348. writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) |
  349. ((mode + 1) << (m_core * 2)),
  350. GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4);
  351. if (ack) {
  352. /* set ack */
  353. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
  354. /* clear dummy ack */
  355. val &= ~(mode ? BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK :
  356. BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK);
  357. val |= 1 << (m_core + (mode ? 16 : 0));
  358. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
  359. }
  360. }
  361. static __secure void imx_system_counter_resume(void)
  362. {
  363. u32 val;
  364. val = readl(SYSCNT_CTRL_IPS_BASE_ADDR);
  365. val &= ~BM_SYS_COUNTER_CNTCR_FCR1;
  366. val |= BM_SYS_COUNTER_CNTCR_FCR0;
  367. writel(val, SYSCNT_CTRL_IPS_BASE_ADDR);
  368. }
  369. static __secure void imx_system_counter_suspend(void)
  370. {
  371. u32 val;
  372. val = readl(SYSCNT_CTRL_IPS_BASE_ADDR);
  373. val &= ~BM_SYS_COUNTER_CNTCR_FCR0;
  374. val |= BM_SYS_COUNTER_CNTCR_FCR1;
  375. writel(val, SYSCNT_CTRL_IPS_BASE_ADDR);
  376. }
  377. static __secure void gic_resume(void)
  378. {
  379. u32 itlinesnr, i;
  380. u32 gic_dist_addr = GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET;
  381. /* enable the GIC distributor */
  382. writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
  383. gic_dist_addr + GICD_CTLR);
  384. /* TYPER[4:0] contains an encoded number of available interrupts */
  385. itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
  386. /* set all bits in the GIC group registers to one to allow access
  387. * from non-secure state. The first 32 interrupts are private per
  388. * CPU and will be set later when enabling the GIC for each core
  389. */
  390. for (i = 1; i <= itlinesnr; i++)
  391. writel((u32)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
  392. }
  393. static inline void imx_pll_suspend(void)
  394. {
  395. writel(BM_ANATOP_ARM_PLL_OVERRIDE,
  396. ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_SET);
  397. writel(BM_ANATOP_DDR_PLL_OVERRIDE,
  398. ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_SET);
  399. writel(BM_ANATOP_SYS_PLL_OVERRIDE,
  400. ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_SET);
  401. writel(BM_ANATOP_ENET_PLL_OVERRIDE,
  402. ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_SET);
  403. writel(BM_ANATOP_AUDIO_PLL_OVERRIDE,
  404. ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_SET);
  405. writel(BM_ANATOP_VIDEO_PLL_OVERRIDE,
  406. ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_SET);
  407. }
  408. static inline void imx_pll_resume(void)
  409. {
  410. writel(BM_ANATOP_ARM_PLL_OVERRIDE,
  411. ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_CLR);
  412. writel(BM_ANATOP_DDR_PLL_OVERRIDE,
  413. ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_CLR);
  414. writel(BM_ANATOP_SYS_PLL_OVERRIDE,
  415. ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_CLR);
  416. writel(BM_ANATOP_ENET_PLL_OVERRIDE,
  417. ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_CLR);
  418. writel(BM_ANATOP_AUDIO_PLL_OVERRIDE,
  419. ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_CLR);
  420. writel(BM_ANATOP_VIDEO_PLL_OVERRIDE,
  421. ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_CLR);
  422. }
  423. static inline void imx_udelay(u32 usec)
  424. {
  425. u32 freq;
  426. u64 start, end;
  427. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
  428. asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
  429. do {
  430. asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
  431. if ((end - start) > usec * (freq / 1000000))
  432. break;
  433. } while (1);
  434. }
  435. static inline void imx_ddrc_enter_self_refresh(void)
  436. {
  437. writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
  438. while (readl(DDRC_IPS_BASE_ADDR + DDRC_PSTAT) & 0x10001)
  439. ;
  440. writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
  441. while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x23) != 0x23)
  442. ;
  443. writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8,
  444. DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
  445. }
  446. static inline void imx_ddrc_exit_self_refresh(void)
  447. {
  448. writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
  449. while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x3) == 0x3)
  450. ;
  451. writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1,
  452. DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
  453. }
  454. __secure void imx_system_resume(void)
  455. {
  456. unsigned int i, val, imr[4], entry;
  457. entry = psci_get_target_pc(0);
  458. imx_ddrc_exit_self_refresh();
  459. imx_system_counter_resume();
  460. imx_gpcv2_set_lpm_mode(RUN);
  461. imx_gpcv2_set_cpu_power_gate_by_lpm(0, false);
  462. imx_gpcv2_set_plat_power_gate_by_lpm(false);
  463. imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0);
  464. imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU);
  465. /*
  466. * need to mask all interrupts in GPC before
  467. * operating RBC configurations
  468. */
  469. for (i = 0; i < 4; i++) {
  470. imr[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  471. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  472. }
  473. /* configure RBC enable bit */
  474. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  475. val &= ~BM_SLPCR_RBC_EN;
  476. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  477. /* configure RBC count */
  478. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  479. val &= ~BM_SLPCR_REG_BYPASS_COUNT;
  480. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  481. /*
  482. * need to delay at least 2 cycles of CKIL(32K)
  483. * due to hardware design requirement, which is
  484. * ~61us, here we use 65us for safe
  485. */
  486. imx_udelay(65);
  487. /* restore GPC interrupt mask settings */
  488. for (i = 0; i < 4; i++)
  489. writel(imr[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  490. /* initialize gic distributor */
  491. gic_resume();
  492. _nonsec_init();
  493. /* save cpu0 entry */
  494. psci_save(0, entry, 0);
  495. psci_cpu_entry();
  496. }
  497. __secure void psci_system_suspend(u32 __always_unused function_id,
  498. u32 ep, u32 context_id)
  499. {
  500. u32 gpc_mask[4];
  501. u32 i, val;
  502. psci_save(0, ep, context_id);
  503. /* overwrite PLL to be controlled by low power mode */
  504. imx_pll_suspend();
  505. imx_system_counter_suspend();
  506. /* set CA7 platform to enter STOP mode */
  507. imx_gpcv2_set_lpm_mode(STOP);
  508. /* enable core0/scu power down/up with low power mode */
  509. imx_gpcv2_set_cpu_power_gate_by_lpm(0, true);
  510. imx_gpcv2_set_plat_power_gate_by_lpm(true);
  511. /* time slot settings for core0 and scu */
  512. imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false);
  513. imx_gpcv2_set_slot_ack(1, SCU_A7, false, true);
  514. imx_gpcv2_set_slot_ack(5, SCU_A7, true, false);
  515. imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true);
  516. imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0);
  517. imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU);
  518. psci_v7_flush_dcache_all();
  519. imx_ddrc_enter_self_refresh();
  520. /*
  521. * e10133: ARM: Boot failure after A7 enters into
  522. * low-power idle mode
  523. *
  524. * Workaround:
  525. * If both CPU0/CPU1 are IDLE, the last IDLE CPU should
  526. * disable GIC first, then REG_BYPASS_COUNTER is used
  527. * to mask wakeup INT, and then execute “wfi” is used to
  528. * bring the system into power down processing safely.
  529. * The counter must be enabled as close to the “wfi” state
  530. * as possible. The following equation can be used to
  531. * determine the RBC counter value:
  532. * RBC_COUNT * (1/32K RTC frequency) >=
  533. * (46 + PDNSCR_SW + PDNSCR_SW2ISO ) ( 1/IPG_CLK frequency ).
  534. */
  535. /* disable GIC distributor */
  536. writel(0, GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET);
  537. for (i = 0; i < 4; i++)
  538. gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  539. /*
  540. * enable the RBC bypass counter here
  541. * to hold off the interrupts. RBC counter
  542. * = 8 (240us). With this setting, the latency
  543. * from wakeup interrupt to ARM power up
  544. * is ~250uS.
  545. */
  546. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  547. val &= ~(0x3f << 24);
  548. val |= (0x8 << 24);
  549. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  550. /* enable the counter. */
  551. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  552. val |= (1 << 30);
  553. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  554. /* unmask all the GPC interrupts. */
  555. for (i = 0; i < 4; i++)
  556. writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  557. /*
  558. * now delay for a short while (3usec)
  559. * ARM is at 1GHz at this point
  560. * so a short loop should be enough.
  561. * this delay is required to ensure that
  562. * the RBC counter can start counting in
  563. * case an interrupt is already pending
  564. * or in case an interrupt arrives just
  565. * as ARM is about to assert DSM_request.
  566. */
  567. imx_udelay(3);
  568. /* save resume entry and sp in CPU0 GPR registers */
  569. asm volatile("mov %0, sp" : "=r" (val));
  570. writel((u32)psci_system_resume, SRC_BASE_ADDR + SRC_GPR1_MX7D);
  571. writel(val, SRC_BASE_ADDR + SRC_GPR2_MX7D);
  572. /* sleep */
  573. while (1)
  574. wfi();
  575. }