soc.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/cache.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  18. #error "CPU_TYPE not defined"
  19. #endif
  20. u32 get_cpu_rev(void)
  21. {
  22. #ifdef CONFIG_MX51
  23. int system_rev = 0x51000;
  24. #else
  25. int system_rev = 0x53000;
  26. #endif
  27. int reg = __raw_readl(ROM_SI_REV);
  28. #if defined(CONFIG_MX51)
  29. switch (reg) {
  30. case 0x02:
  31. system_rev |= CHIP_REV_1_1;
  32. break;
  33. case 0x10:
  34. if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  35. system_rev |= CHIP_REV_2_5;
  36. else
  37. system_rev |= CHIP_REV_2_0;
  38. break;
  39. case 0x20:
  40. system_rev |= CHIP_REV_3_0;
  41. break;
  42. default:
  43. system_rev |= CHIP_REV_1_0;
  44. break;
  45. }
  46. #else
  47. if (reg < 0x20)
  48. system_rev |= CHIP_REV_1_0;
  49. else
  50. system_rev |= reg;
  51. #endif
  52. return system_rev;
  53. }
  54. #ifdef CONFIG_REVISION_TAG
  55. u32 __weak get_board_rev(void)
  56. {
  57. return get_cpu_rev();
  58. }
  59. #endif
  60. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  61. void enable_caches(void)
  62. {
  63. /* Enable D-cache. I-cache is already enabled in start.S */
  64. dcache_enable();
  65. }
  66. #endif
  67. #if defined(CONFIG_FEC_MXC)
  68. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  69. {
  70. int i;
  71. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  72. struct fuse_bank *bank = &iim->bank[1];
  73. struct fuse_bank1_regs *fuse =
  74. (struct fuse_bank1_regs *)bank->fuse_regs;
  75. for (i = 0; i < 6; i++)
  76. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  77. }
  78. #endif
  79. #ifdef CONFIG_MX53
  80. void boot_mode_apply(unsigned cfg_val)
  81. {
  82. writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
  83. }
  84. /*
  85. * cfg_val will be used for
  86. * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  87. *
  88. * If bit 28 of LPGR is set upon watchdog reset,
  89. * bits[25:0] of LPGR will move to SBMR.
  90. */
  91. const struct boot_mode soc_boot_modes[] = {
  92. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  93. /* usb or serial download */
  94. {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
  95. {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
  96. {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
  97. {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
  98. {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
  99. {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
  100. /* 4 bit bus width */
  101. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
  102. {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
  103. {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
  104. {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
  105. {NULL, 0},
  106. };
  107. #endif