lowlevel_init.c 5.4 KB

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  1. /*
  2. * Lowlevel setup for EXYNOS5 based board
  3. *
  4. * Copyright (C) 2013 Samsung Electronics
  5. * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <config.h>
  27. #include <debug_uart.h>
  28. #include <asm/system.h>
  29. #include <asm/arch/cpu.h>
  30. #include <asm/arch/dmc.h>
  31. #include <asm/arch/power.h>
  32. #include <asm/arch/tzpc.h>
  33. #include <asm/arch/periph.h>
  34. #include <asm/arch/pinmux.h>
  35. #include <asm/arch/system.h>
  36. #include <asm/armv7.h>
  37. #include "common_setup.h"
  38. #include "exynos5_setup.h"
  39. /* These are the things we can do during low-level init */
  40. enum {
  41. DO_WAKEUP = 1 << 0,
  42. DO_CLOCKS = 1 << 1,
  43. DO_MEM_RESET = 1 << 2,
  44. DO_UART = 1 << 3,
  45. DO_POWER = 1 << 4,
  46. };
  47. #ifdef CONFIG_EXYNOS5420
  48. /*
  49. * Power up secondary CPUs.
  50. */
  51. static void secondary_cpu_start(void)
  52. {
  53. v7_enable_smp(EXYNOS5420_INFORM_BASE);
  54. svc32_mode_en();
  55. branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
  56. }
  57. /*
  58. * This is the entry point of hotplug-in and
  59. * cluster switching.
  60. */
  61. static void low_power_start(void)
  62. {
  63. uint32_t val, reg_val;
  64. reg_val = readl(EXYNOS5420_SPARE_BASE);
  65. if (reg_val != CPU_RST_FLAG_VAL) {
  66. writel(0x0, CONFIG_LOWPOWER_FLAG);
  67. branch_bx(0x0);
  68. }
  69. reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
  70. if (reg_val != (uint32_t)&low_power_start) {
  71. /* Store jump address as low_power_start if not present */
  72. writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
  73. dsb();
  74. sev();
  75. }
  76. /* Set the CPU to SVC32 mode */
  77. svc32_mode_en();
  78. #ifndef CONFIG_SYS_L2CACHE_OFF
  79. /* Read MIDR for Primary Part Number */
  80. mrc_midr(val);
  81. val = (val >> 4);
  82. val &= 0xf;
  83. if (val == 0xf) {
  84. configure_l2_ctlr();
  85. configure_l2_actlr();
  86. v7_enable_l2_hazard_detect();
  87. }
  88. #endif
  89. /* Invalidate L1 & TLB */
  90. val = 0x0;
  91. mcr_tlb(val);
  92. mcr_icache(val);
  93. /* Disable MMU stuff and caches */
  94. mrc_sctlr(val);
  95. val &= ~((0x2 << 12) | 0x7);
  96. val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
  97. mcr_sctlr(val);
  98. /* CPU state is hotplug or reset */
  99. secondary_cpu_start();
  100. /* Core should not enter into WFI here */
  101. wfi();
  102. }
  103. /*
  104. * Pointer to this function is stored in iRam which is used
  105. * for jump and power down of a specific core.
  106. */
  107. static void power_down_core(void)
  108. {
  109. uint32_t tmp, core_id, core_config;
  110. /* Get the unique core id */
  111. /*
  112. * Multiprocessor Affinity Register
  113. * [11:8] Cluster ID
  114. * [1:0] CPU ID
  115. */
  116. mrc_mpafr(core_id);
  117. tmp = core_id & 0x3;
  118. core_id = (core_id >> 6) & ~3;
  119. core_id |= tmp;
  120. core_id &= 0x3f;
  121. /* Set the status of the core to low */
  122. core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
  123. core_config += EXYNOS5420_CPU_CONFIG_BASE;
  124. writel(0x0, core_config);
  125. /* Core enter WFI */
  126. wfi();
  127. }
  128. /*
  129. * Configurations for secondary cores are inapt at this stage.
  130. * Reconfigure secondary cores. Shutdown and change the status
  131. * of all cores except the primary core.
  132. */
  133. static void secondary_cores_configure(void)
  134. {
  135. /* Clear secondary boot iRAM base */
  136. writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
  137. /* set lowpower flag and address */
  138. writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
  139. writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
  140. writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
  141. /* Store jump address for power down */
  142. writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
  143. /* Need all core power down check */
  144. dsb();
  145. sev();
  146. }
  147. extern void relocate_wait_code(void);
  148. #endif
  149. int do_lowlevel_init(void)
  150. {
  151. uint32_t reset_status;
  152. int actions = 0;
  153. arch_cpu_init();
  154. #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
  155. /*
  156. * Init L2 cache parameters here for use by boot and resume
  157. *
  158. * These are here instead of in v7_outer_cache_enable() so that the
  159. * L2 cache settings get properly set even at resume time or if we're
  160. * running U-Boot with the cache off. The kernel still needs us to
  161. * set these for it.
  162. */
  163. configure_l2_ctlr();
  164. configure_l2_actlr();
  165. dsb();
  166. isb();
  167. relocate_wait_code();
  168. /* Reconfigure secondary cores */
  169. secondary_cores_configure();
  170. #endif
  171. reset_status = get_reset_status();
  172. switch (reset_status) {
  173. case S5P_CHECK_SLEEP:
  174. actions = DO_CLOCKS | DO_WAKEUP;
  175. break;
  176. case S5P_CHECK_DIDLE:
  177. case S5P_CHECK_LPA:
  178. actions = DO_WAKEUP;
  179. break;
  180. default:
  181. /* This is a normal boot (not a wake from sleep) */
  182. actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
  183. }
  184. if (actions & DO_POWER)
  185. set_ps_hold_ctrl();
  186. if (actions & DO_CLOCKS) {
  187. system_clock_init();
  188. #ifdef CONFIG_DEBUG_UART
  189. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
  190. !defined(CONFIG_SPL_BUILD)
  191. exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
  192. debug_uart_init();
  193. #endif
  194. #endif
  195. mem_ctrl_init(actions & DO_MEM_RESET);
  196. tzpc_init();
  197. }
  198. return actions & DO_WAKEUP;
  199. }