cache.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /* for now: just dummy functions to satisfy the linker */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <malloc.h>
  10. #include <asm/cache.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /*
  13. * Flush range from all levels of d-cache/unified-cache.
  14. * Affects the range [start, start + size - 1].
  15. */
  16. __weak void flush_cache(unsigned long start, unsigned long size)
  17. {
  18. flush_dcache_range(start, start + size);
  19. }
  20. /*
  21. * Default implementation:
  22. * do a range flush for the entire range
  23. */
  24. __weak void flush_dcache_all(void)
  25. {
  26. flush_cache(0, ~0);
  27. }
  28. /*
  29. * Default implementation of enable_caches()
  30. * Real implementation should be in platform code
  31. */
  32. __weak void enable_caches(void)
  33. {
  34. puts("WARNING: Caches not enabled\n");
  35. }
  36. __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
  37. {
  38. /* An empty stub, real implementation should be in platform code */
  39. }
  40. __weak void flush_dcache_range(unsigned long start, unsigned long stop)
  41. {
  42. /* An empty stub, real implementation should be in platform code */
  43. }
  44. int check_cache_range(unsigned long start, unsigned long stop)
  45. {
  46. int ok = 1;
  47. if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
  48. ok = 0;
  49. if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
  50. ok = 0;
  51. if (!ok) {
  52. warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
  53. start, stop);
  54. }
  55. return ok;
  56. }
  57. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  58. /*
  59. * Reserve one MMU section worth of address space below the malloc() area that
  60. * will be mapped uncached.
  61. */
  62. static unsigned long noncached_start;
  63. static unsigned long noncached_end;
  64. static unsigned long noncached_next;
  65. void noncached_set_region(void)
  66. {
  67. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  68. mmu_set_region_dcache_behaviour(noncached_start,
  69. noncached_end - noncached_start,
  70. DCACHE_OFF);
  71. #endif
  72. }
  73. void noncached_init(void)
  74. {
  75. phys_addr_t start, end;
  76. size_t size;
  77. /* If this calculation changes, update board_f.c:reserve_noncached() */
  78. end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
  79. size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
  80. start = end - size;
  81. debug("mapping memory %pa-%pa non-cached\n", &start, &end);
  82. noncached_start = start;
  83. noncached_end = end;
  84. noncached_next = start;
  85. noncached_set_region();
  86. }
  87. phys_addr_t noncached_alloc(size_t size, size_t align)
  88. {
  89. phys_addr_t next = ALIGN(noncached_next, align);
  90. if (next >= noncached_end || (noncached_end - next) < size)
  91. return 0;
  92. debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
  93. noncached_next = next + size;
  94. return next;
  95. }
  96. #endif /* CONFIG_SYS_NONCACHED_MEMORY */
  97. #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
  98. void invalidate_l2_cache(void)
  99. {
  100. unsigned int val = 0;
  101. asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
  102. : : "r" (val) : "cc");
  103. isb();
  104. }
  105. #endif
  106. int arch_reserve_mmu(void)
  107. {
  108. return arm_reserve_mmu();
  109. }
  110. __weak int arm_reserve_mmu(void)
  111. {
  112. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  113. /* reserve TLB table */
  114. gd->arch.tlb_size = PGTABLE_SIZE;
  115. gd->relocaddr -= gd->arch.tlb_size;
  116. /* round down to next 64 kB limit */
  117. gd->relocaddr &= ~(0x10000 - 1);
  118. gd->arch.tlb_addr = gd->relocaddr;
  119. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  120. gd->arch.tlb_addr + gd->arch.tlb_size);
  121. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  122. /*
  123. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  124. * with location within secure ram.
  125. */
  126. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  127. #endif
  128. #endif
  129. return 0;
  130. }