generic.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <net.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/mc_cgm_regs.h>
  13. #include <asm/arch/mc_me_regs.h>
  14. #include <asm/arch/mc_rgm_regs.h>
  15. #include <netdev.h>
  16. #include <div64.h>
  17. #include <errno.h>
  18. u32 get_cpu_rev(void)
  19. {
  20. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
  21. u32 cpu = readl(&mscmir->cpxtype);
  22. return cpu;
  23. }
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
  26. u32 pllfd, u32 selected_output)
  27. {
  28. u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
  29. u32 plldv_rfdphi_div = 0, fout = 0;
  30. u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
  31. if (selected_output > DFS_MAXNUMBER) {
  32. return -1;
  33. }
  34. plldv_prediv =
  35. (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
  36. plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
  37. pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
  38. plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
  39. /* The formula for VCO is from TR manual, rev. D */
  40. vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
  41. if (selected_output != 0) {
  42. /* Determine the RFDPHI for PHI1 */
  43. plldv_rfdphi_div =
  44. (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
  45. PLLDIG_PLLDV_RFDPHI1_OFFSET;
  46. plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
  47. if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
  48. dfs_portn =
  49. readl(DFS_DVPORTn(pll, selected_output - 1));
  50. dfs_mfi =
  51. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  52. DFS_DVPORTn_MFI_OFFSET;
  53. dfs_mfn =
  54. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  55. DFS_DVPORTn_MFI_OFFSET;
  56. fout = vco / (dfs_mfi + (dfs_mfn / 256));
  57. } else {
  58. fout = vco / plldv_rfdphi_div;
  59. }
  60. } else {
  61. /* Determine the RFDPHI for PHI0 */
  62. plldv_rfdphi_div =
  63. (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
  64. PLLDIG_PLLDV_RFDPHI_OFFSET;
  65. fout = vco / plldv_rfdphi_div;
  66. }
  67. return fout;
  68. }
  69. /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
  70. static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
  71. u32 selected_output)
  72. {
  73. u32 plldv, pllfd;
  74. plldv = readl(PLLDIG_PLLDV(pll));
  75. pllfd = readl(PLLDIG_PLLFD(pll));
  76. return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
  77. }
  78. static u32 get_mcu_main_clk(void)
  79. {
  80. u32 coreclk_div;
  81. u32 sysclk_sel;
  82. u32 freq = 0;
  83. sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  84. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  85. coreclk_div =
  86. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
  87. coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  88. coreclk_div += 1;
  89. switch (sysclk_sel) {
  90. case MC_CGM_SC_SEL_FIRC:
  91. freq = FIRC_CLK_FREQ;
  92. break;
  93. case MC_CGM_SC_SEL_XOSC:
  94. freq = XOSC_CLK_FREQ;
  95. break;
  96. case MC_CGM_SC_SEL_ARMPLL:
  97. /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
  98. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
  99. break;
  100. case MC_CGM_SC_SEL_CLKDISABLE:
  101. printf("Sysclk is disabled\n");
  102. break;
  103. default:
  104. printf("unsupported system clock select\n");
  105. }
  106. return freq / coreclk_div;
  107. }
  108. static u32 get_sys_clk(u32 number)
  109. {
  110. u32 sysclk_div, sysclk_div_number;
  111. u32 sysclk_sel;
  112. u32 freq = 0;
  113. switch (number) {
  114. case 3:
  115. sysclk_div_number = 0;
  116. break;
  117. case 6:
  118. sysclk_div_number = 1;
  119. break;
  120. default:
  121. printf("unsupported system clock \n");
  122. return -1;
  123. }
  124. sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  125. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  126. sysclk_div =
  127. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
  128. MC_CGM_SC_DCn_PREDIV_MASK;
  129. sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  130. sysclk_div += 1;
  131. switch (sysclk_sel) {
  132. case MC_CGM_SC_SEL_FIRC:
  133. freq = FIRC_CLK_FREQ;
  134. break;
  135. case MC_CGM_SC_SEL_XOSC:
  136. freq = XOSC_CLK_FREQ;
  137. break;
  138. case MC_CGM_SC_SEL_ARMPLL:
  139. /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
  140. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
  141. break;
  142. case MC_CGM_SC_SEL_CLKDISABLE:
  143. printf("Sysclk is disabled\n");
  144. break;
  145. default:
  146. printf("unsupported system clock select\n");
  147. }
  148. return freq / sysclk_div;
  149. }
  150. static u32 get_peripherals_clk(void)
  151. {
  152. u32 aux5clk_div;
  153. u32 freq = 0;
  154. aux5clk_div =
  155. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
  156. MC_CGM_ACn_DCm_PREDIV_MASK;
  157. aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  158. aux5clk_div += 1;
  159. freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
  160. return freq / aux5clk_div;
  161. }
  162. static u32 get_uart_clk(void)
  163. {
  164. u32 auxclk3_div, auxclk3_sel, freq = 0;
  165. auxclk3_sel =
  166. readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
  167. auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
  168. auxclk3_div =
  169. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
  170. MC_CGM_ACn_DCm_PREDIV_MASK;
  171. auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  172. auxclk3_div += 1;
  173. switch (auxclk3_sel) {
  174. case MC_CGM_ACn_SEL_FIRC:
  175. freq = FIRC_CLK_FREQ;
  176. break;
  177. case MC_CGM_ACn_SEL_XOSC:
  178. freq = XOSC_CLK_FREQ;
  179. break;
  180. case MC_CGM_ACn_SEL_PERPLLDIVX:
  181. freq = get_peripherals_clk() / 3;
  182. break;
  183. case MC_CGM_ACn_SEL_SYSCLK:
  184. freq = get_sys_clk(6);
  185. break;
  186. default:
  187. printf("unsupported system clock select\n");
  188. }
  189. return freq / auxclk3_div;
  190. }
  191. static u32 get_fec_clk(void)
  192. {
  193. u32 aux2clk_div;
  194. u32 freq = 0;
  195. aux2clk_div =
  196. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
  197. MC_CGM_ACn_DCm_PREDIV_MASK;
  198. aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  199. aux2clk_div += 1;
  200. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
  201. return freq / aux2clk_div;
  202. }
  203. static u32 get_usdhc_clk(void)
  204. {
  205. u32 aux15clk_div;
  206. u32 freq = 0;
  207. aux15clk_div =
  208. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
  209. MC_CGM_ACn_DCm_PREDIV_MASK;
  210. aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  211. aux15clk_div += 1;
  212. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
  213. return freq / aux15clk_div;
  214. }
  215. static u32 get_i2c_clk(void)
  216. {
  217. return get_peripherals_clk();
  218. }
  219. /* return clocks in Hz */
  220. unsigned int mxc_get_clock(enum mxc_clock clk)
  221. {
  222. switch (clk) {
  223. case MXC_ARM_CLK:
  224. return get_mcu_main_clk();
  225. case MXC_PERIPHERALS_CLK:
  226. return get_peripherals_clk();
  227. case MXC_UART_CLK:
  228. return get_uart_clk();
  229. case MXC_FEC_CLK:
  230. return get_fec_clk();
  231. case MXC_I2C_CLK:
  232. return get_i2c_clk();
  233. case MXC_USDHC_CLK:
  234. return get_usdhc_clk();
  235. default:
  236. break;
  237. }
  238. printf("Error: Unsupported function to read the frequency! \
  239. Please define it correctly!");
  240. return -1;
  241. }
  242. /* Not yet implemented - int soc_clk_dump(); */
  243. #if defined(CONFIG_DISPLAY_CPUINFO)
  244. static char *get_reset_cause(void)
  245. {
  246. u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
  247. switch (cause) {
  248. case F_SWT4:
  249. return "WDOG";
  250. case F_JTAG:
  251. return "JTAG";
  252. case F_FCCU_SOFT:
  253. return "FCCU soft reaction";
  254. case F_FCCU_HARD:
  255. return "FCCU hard reaction";
  256. case F_SOFT_FUNC:
  257. return "Software Functional reset";
  258. case F_ST_DONE:
  259. return "Self Test done reset";
  260. case F_EXT_RST:
  261. return "External reset";
  262. default:
  263. return "unknown reset";
  264. }
  265. }
  266. #define SRC_SCR_SW_RST (1<<12)
  267. void reset_cpu(ulong addr)
  268. {
  269. printf("Feature not supported.\n");
  270. };
  271. int print_cpuinfo(void)
  272. {
  273. printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
  274. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  275. printf("Reset cause: %s\n", get_reset_cause());
  276. return 0;
  277. }
  278. #endif
  279. int cpu_eth_init(bd_t * bis)
  280. {
  281. int rc = -ENODEV;
  282. #if defined(CONFIG_FEC_MXC)
  283. rc = fecmxc_initialize(bis);
  284. #endif
  285. return rc;
  286. }
  287. int get_clocks(void)
  288. {
  289. #ifdef CONFIG_FSL_ESDHC_IMX
  290. gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
  291. #endif
  292. return 0;
  293. }