spl.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <env.h>
  9. #include <spl.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <fsl_ifc.h>
  13. #include <i2c.h>
  14. #include <fsl_csu.h>
  15. #include <asm/arch/fdt.h>
  16. #include <asm/arch/ppa.h>
  17. #include <asm/arch/soc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. u32 spl_boot_device(void)
  20. {
  21. #ifdef CONFIG_SPL_MMC_SUPPORT
  22. return BOOT_DEVICE_MMC1;
  23. #endif
  24. #ifdef CONFIG_SPL_NAND_SUPPORT
  25. return BOOT_DEVICE_NAND;
  26. #endif
  27. #ifdef CONFIG_QSPI_BOOT
  28. return BOOT_DEVICE_NOR;
  29. #endif
  30. return 0;
  31. }
  32. #ifdef CONFIG_SPL_BUILD
  33. void spl_board_init(void)
  34. {
  35. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
  36. /*
  37. * In case of Secure Boot, the IBR configures the SMMU
  38. * to allow only Secure transactions.
  39. * SMMU must be reset in bypass mode.
  40. * Set the ClientPD bit and Clear the USFCFG Bit
  41. */
  42. u32 val;
  43. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  44. out_le32(SMMU_SCR0, val);
  45. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  46. out_le32(SMMU_NSCR0, val);
  47. #endif
  48. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  49. enable_layerscape_ns_access();
  50. #endif
  51. #ifdef CONFIG_SPL_FSL_LS_PPA
  52. ppa_init();
  53. #endif
  54. }
  55. void board_init_f(ulong dummy)
  56. {
  57. icache_enable();
  58. /* Clear global data */
  59. memset((void *)gd, 0, sizeof(gd_t));
  60. board_early_init_f();
  61. timer_init();
  62. #ifdef CONFIG_ARCH_LS2080A
  63. env_init();
  64. #endif
  65. get_clocks();
  66. preloader_console_init();
  67. spl_set_bd();
  68. #ifdef CONFIG_SYS_I2C
  69. #ifdef CONFIG_SPL_I2C_SUPPORT
  70. i2c_init_all();
  71. #endif
  72. #endif
  73. #ifdef CONFIG_VID
  74. init_func_vid();
  75. #endif
  76. dram_init();
  77. #ifdef CONFIG_SPL_FSL_LS_PPA
  78. #ifndef CONFIG_SYS_MEM_RESERVE_SECURE
  79. #error Need secure RAM for PPA
  80. #endif
  81. /*
  82. * Secure memory location is determined in dram_init_banksize().
  83. * gd->ram_size is deducted by the size of secure ram.
  84. */
  85. dram_init_banksize();
  86. /*
  87. * After dram_init_bank_size(), we know U-Boot only uses the first
  88. * memory bank regardless how big the memory is.
  89. */
  90. gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
  91. /*
  92. * If PPA is loaded, U-Boot will resume running at EL2.
  93. * Cache and MMU will be enabled. Need a place for TLB.
  94. * U-Boot will be relocated to the end of available memory
  95. * in first bank. At this point, we cannot know how much
  96. * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
  97. * to avoid overlapping. As soon as the RAM version U-Boot sets
  98. * up new MMU, this space is no longer needed.
  99. */
  100. gd->ram_top -= SPL_TLB_SETBACK;
  101. gd->arch.tlb_size = PGTABLE_SIZE;
  102. gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
  103. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  104. #endif /* CONFIG_SPL_FSL_LS_PPA */
  105. #if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
  106. qspi_ahb_init();
  107. #endif
  108. }
  109. #ifdef CONFIG_SPL_OS_BOOT
  110. /*
  111. * Return
  112. * 0 if booting into OS is selected
  113. * 1 if booting into U-Boot is selected
  114. */
  115. int spl_start_uboot(void)
  116. {
  117. env_init();
  118. if (env_get_yesno("boot_os") != 0)
  119. return 0;
  120. return 1;
  121. }
  122. #endif /* CONFIG_SPL_OS_BOOT */
  123. #ifdef CONFIG_SPL_LOAD_FIT
  124. __weak int board_fit_config_name_match(const char *name)
  125. {
  126. /* Just empty function now - can't decide what to choose */
  127. debug("%s: %s\n", __func__, name);
  128. return 0;
  129. }
  130. #endif
  131. #endif /* CONFIG_SPL_BUILD */