soc.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <fsl_immap.h>
  11. #include <fsl_ifc.h>
  12. #include <init.h>
  13. #include <linux/sizes.h>
  14. #include <asm/arch/fsl_serdes.h>
  15. #include <asm/arch/soc.h>
  16. #include <asm/cache.h>
  17. #include <asm/io.h>
  18. #include <asm/global_data.h>
  19. #include <asm/arch-fsl-layerscape/config.h>
  20. #include <asm/arch-fsl-layerscape/ns_access.h>
  21. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  22. #include <asm/gic-v3.h>
  23. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  24. #include <fsl_csu.h>
  25. #endif
  26. #ifdef CONFIG_SYS_FSL_DDR
  27. #include <fsl_ddr_sdram.h>
  28. #include <fsl_ddr.h>
  29. #endif
  30. #ifdef CONFIG_CHAIN_OF_TRUST
  31. #include <fsl_validate.h>
  32. #endif
  33. #include <fsl_immap.h>
  34. #ifdef CONFIG_TFABOOT
  35. #include <env_internal.h>
  36. #endif
  37. #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #endif
  40. #ifdef CONFIG_GIC_V3_ITS
  41. #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
  42. #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
  43. #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
  44. PROPTABLE_MAX_SZ, SZ_1M)
  45. static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
  46. {
  47. u32 phandle;
  48. int err;
  49. struct fdt_memory gic_rd_tables;
  50. gic_rd_tables.start = base;
  51. gic_rd_tables.end = base + size - 1;
  52. err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
  53. &phandle);
  54. if (err < 0)
  55. debug("%s: failed to add reserved memory: %d\n", __func__, err);
  56. return err;
  57. }
  58. int ls_gic_rd_tables_init(void *blob)
  59. {
  60. u64 gic_lpi_base;
  61. int ret;
  62. gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
  63. ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
  64. if (ret)
  65. return ret;
  66. ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
  67. if (ret)
  68. debug("%s: failed to init gic-lpi-tables\n", __func__);
  69. return ret;
  70. }
  71. #endif
  72. bool soc_has_dp_ddr(void)
  73. {
  74. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  75. u32 svr = gur_in32(&gur->svr);
  76. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  77. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  78. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  79. (SVR_SOC_VER(svr) == SVR_LS2048A))
  80. return true;
  81. return false;
  82. }
  83. bool soc_has_aiop(void)
  84. {
  85. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  86. u32 svr = gur_in32(&gur->svr);
  87. /* LS2085A has AIOP */
  88. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  89. return true;
  90. return false;
  91. }
  92. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  93. {
  94. scfg_clrsetbits32(scfg + offset / 4,
  95. 0xF << 6,
  96. SCFG_USB_TXVREFTUNE << 6);
  97. }
  98. static void erratum_a009008(void)
  99. {
  100. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  101. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  102. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  103. defined(CONFIG_ARCH_LS1012A)
  104. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  105. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  106. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  107. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  108. #endif
  109. #elif defined(CONFIG_ARCH_LS2080A)
  110. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  111. #endif
  112. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  113. }
  114. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  115. {
  116. scfg_clrbits32(scfg + offset / 4,
  117. SCFG_USB_SQRXTUNE_MASK << 23);
  118. }
  119. static void erratum_a009798(void)
  120. {
  121. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  122. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  123. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  124. defined(CONFIG_ARCH_LS1012A)
  125. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  126. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  127. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  128. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  129. #endif
  130. #elif defined(CONFIG_ARCH_LS2080A)
  131. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  132. #endif
  133. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  134. }
  135. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  136. defined(CONFIG_ARCH_LS1012A)
  137. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  138. {
  139. scfg_clrsetbits32(scfg + offset / 4,
  140. 0x7F << 9,
  141. SCFG_USB_PCSTXSWINGFULL << 9);
  142. }
  143. #endif
  144. static void erratum_a008997(void)
  145. {
  146. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  147. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  148. defined(CONFIG_ARCH_LS1012A)
  149. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  150. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  151. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  152. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  153. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  154. #endif
  155. #elif defined(CONFIG_ARCH_LS1028A)
  156. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  157. 0x7F << 11,
  158. DCSR_USB_PCSTXSWINGFULL << 11);
  159. #endif
  160. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  161. }
  162. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  163. defined(CONFIG_ARCH_LS1012A)
  164. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  165. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  166. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  167. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  168. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  169. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  170. defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
  171. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  172. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  173. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  174. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  175. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  176. #endif
  177. static void erratum_a009007(void)
  178. {
  179. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  180. defined(CONFIG_ARCH_LS1012A)
  181. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  182. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  183. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  184. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  185. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  186. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  187. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  188. #endif
  189. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  190. defined(CONFIG_ARCH_LS1028A)
  191. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  192. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  193. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  194. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  195. }
  196. #if defined(CONFIG_FSL_LSCH3)
  197. static void erratum_a050106(void)
  198. {
  199. #if defined(CONFIG_ARCH_LX2160A)
  200. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  201. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  202. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  203. #endif
  204. }
  205. /*
  206. * This erratum requires setting a value to eddrtqcr1 to
  207. * optimal the DDR performance.
  208. */
  209. static void erratum_a008336(void)
  210. {
  211. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  212. u32 *eddrtqcr1;
  213. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  214. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  215. if (fsl_ddr_get_version(0) == 0x50200)
  216. out_le32(eddrtqcr1, 0x63b30002);
  217. #endif
  218. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  219. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  220. if (fsl_ddr_get_version(0) == 0x50200)
  221. out_le32(eddrtqcr1, 0x63b30002);
  222. #endif
  223. #endif
  224. }
  225. /*
  226. * This erratum requires a register write before being Memory
  227. * controller 3 being enabled.
  228. */
  229. static void erratum_a008514(void)
  230. {
  231. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  232. u32 *eddrtqcr1;
  233. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  234. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  235. out_le32(eddrtqcr1, 0x63b20002);
  236. #endif
  237. #endif
  238. }
  239. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  240. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  241. static unsigned long get_internval_val_mhz(void)
  242. {
  243. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  244. /*
  245. * interval is the number of platform cycles(MHz) between
  246. * wake up events generated by EPU.
  247. */
  248. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  249. if (interval)
  250. interval_mhz = simple_strtoul(interval, NULL, 10);
  251. return interval_mhz;
  252. }
  253. void erratum_a009635(void)
  254. {
  255. u32 val;
  256. unsigned long interval_mhz = get_internval_val_mhz();
  257. if (!interval_mhz)
  258. return;
  259. val = in_le32(DCSR_CGACRE5);
  260. writel(val | 0x00000200, DCSR_CGACRE5);
  261. val = in_le32(EPU_EPCMPR5);
  262. writel(interval_mhz, EPU_EPCMPR5);
  263. val = in_le32(EPU_EPCCR5);
  264. writel(val | 0x82820000, EPU_EPCCR5);
  265. val = in_le32(EPU_EPSMCR5);
  266. writel(val | 0x002f0000, EPU_EPSMCR5);
  267. val = in_le32(EPU_EPECR5);
  268. writel(val | 0x20000000, EPU_EPECR5);
  269. val = in_le32(EPU_EPGCR);
  270. writel(val | 0x80000000, EPU_EPGCR);
  271. }
  272. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  273. static void erratum_rcw_src(void)
  274. {
  275. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  276. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  277. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  278. u32 val;
  279. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  280. val &= ~DCFG_PORSR1_RCW_SRC;
  281. val |= DCFG_PORSR1_RCW_SRC_NOR;
  282. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  283. #endif
  284. }
  285. #define I2C_DEBUG_REG 0x6
  286. #define I2C_GLITCH_EN 0x8
  287. /*
  288. * This erratum requires setting glitch_en bit to enable
  289. * digital glitch filter to improve clock stability.
  290. */
  291. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  292. static void erratum_a009203(void)
  293. {
  294. #ifdef CONFIG_SYS_I2C
  295. u8 __iomem *ptr;
  296. #ifdef I2C1_BASE_ADDR
  297. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  298. writeb(I2C_GLITCH_EN, ptr);
  299. #endif
  300. #ifdef I2C2_BASE_ADDR
  301. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  302. writeb(I2C_GLITCH_EN, ptr);
  303. #endif
  304. #ifdef I2C3_BASE_ADDR
  305. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  306. writeb(I2C_GLITCH_EN, ptr);
  307. #endif
  308. #ifdef I2C4_BASE_ADDR
  309. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  310. writeb(I2C_GLITCH_EN, ptr);
  311. #endif
  312. #endif
  313. }
  314. #endif
  315. void bypass_smmu(void)
  316. {
  317. u32 val;
  318. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  319. out_le32(SMMU_SCR0, val);
  320. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  321. out_le32(SMMU_NSCR0, val);
  322. }
  323. void fsl_lsch3_early_init_f(void)
  324. {
  325. erratum_rcw_src();
  326. #ifdef CONFIG_FSL_IFC
  327. init_early_memctl_regs(); /* tighten IFC timing */
  328. #endif
  329. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  330. erratum_a009203();
  331. #endif
  332. erratum_a008514();
  333. erratum_a008336();
  334. erratum_a009008();
  335. erratum_a009798();
  336. erratum_a008997();
  337. erratum_a009007();
  338. erratum_a050106();
  339. #ifdef CONFIG_CHAIN_OF_TRUST
  340. /* In case of Secure Boot, the IBR configures the SMMU
  341. * to allow only Secure transactions.
  342. * SMMU must be reset in bypass mode.
  343. * Set the ClientPD bit and Clear the USFCFG Bit
  344. */
  345. if (fsl_check_boot_mode_secure() == 1)
  346. bypass_smmu();
  347. #endif
  348. #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
  349. defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
  350. set_icids();
  351. #endif
  352. }
  353. /* Get VDD in the unit mV from voltage ID */
  354. int get_core_volt_from_fuse(void)
  355. {
  356. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  357. int vdd;
  358. u32 fusesr;
  359. u8 vid;
  360. /* get the voltage ID from fuse status register */
  361. fusesr = in_le32(&gur->dcfg_fusesr);
  362. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  363. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  364. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  365. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  366. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  367. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  368. }
  369. debug("%s: VID = 0x%x\n", __func__, vid);
  370. switch (vid) {
  371. case 0x00: /* VID isn't supported */
  372. vdd = -EINVAL;
  373. debug("%s: The VID feature is not supported\n", __func__);
  374. break;
  375. case 0x08: /* 0.9V silicon */
  376. vdd = 900;
  377. break;
  378. case 0x10: /* 1.0V silicon */
  379. vdd = 1000;
  380. break;
  381. default: /* Other core voltage */
  382. vdd = -EINVAL;
  383. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  384. break;
  385. }
  386. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  387. return vdd;
  388. }
  389. #elif defined(CONFIG_FSL_LSCH2)
  390. static void erratum_a009929(void)
  391. {
  392. #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
  393. struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  394. u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
  395. u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
  396. rstrqmr1 |= 0x00000400;
  397. gur_out32(&gur->rstrqmr1, rstrqmr1);
  398. writel(0x01000000, dcsr_cop_ccp);
  399. #endif
  400. }
  401. /*
  402. * This erratum requires setting a value to eddrtqcr1 to optimal
  403. * the DDR performance. The eddrtqcr1 register is in SCFG space
  404. * of LS1043A and the offset is 0x157_020c.
  405. */
  406. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  407. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  408. #error A009660 and A008514 can not be both enabled.
  409. #endif
  410. static void erratum_a009660(void)
  411. {
  412. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  413. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  414. out_be32(eddrtqcr1, 0x63b20042);
  415. #endif
  416. }
  417. static void erratum_a008850_early(void)
  418. {
  419. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  420. /* part 1 of 2 */
  421. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  422. CONFIG_SYS_CCI400_OFFSET);
  423. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  424. /* Skip if running at lower exception level */
  425. if (current_el() < 3)
  426. return;
  427. /* disables propagation of barrier transactions to DDRC from CCI400 */
  428. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  429. /* disable the re-ordering in DDRC */
  430. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  431. #endif
  432. }
  433. void erratum_a008850_post(void)
  434. {
  435. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  436. /* part 2 of 2 */
  437. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  438. CONFIG_SYS_CCI400_OFFSET);
  439. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  440. u32 tmp;
  441. /* Skip if running at lower exception level */
  442. if (current_el() < 3)
  443. return;
  444. /* enable propagation of barrier transactions to DDRC from CCI400 */
  445. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  446. /* enable the re-ordering in DDRC */
  447. tmp = ddr_in32(&ddr->eor);
  448. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  449. ddr_out32(&ddr->eor, tmp);
  450. #endif
  451. }
  452. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  453. void erratum_a010315(void)
  454. {
  455. int i;
  456. for (i = PCIE1; i <= PCIE4; i++)
  457. if (!is_serdes_configured(i)) {
  458. debug("PCIe%d: disabled all R/W permission!\n", i);
  459. set_pcie_ns_access(i, 0);
  460. }
  461. }
  462. #endif
  463. static void erratum_a010539(void)
  464. {
  465. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  466. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  467. u32 porsr1;
  468. porsr1 = in_be32(&gur->porsr1);
  469. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  470. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  471. porsr1);
  472. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  473. #endif
  474. }
  475. /* Get VDD in the unit mV from voltage ID */
  476. int get_core_volt_from_fuse(void)
  477. {
  478. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  479. int vdd;
  480. u32 fusesr;
  481. u8 vid;
  482. fusesr = in_be32(&gur->dcfg_fusesr);
  483. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  484. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  485. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  486. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  487. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  488. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  489. }
  490. debug("%s: VID = 0x%x\n", __func__, vid);
  491. switch (vid) {
  492. case 0x00: /* VID isn't supported */
  493. vdd = -EINVAL;
  494. debug("%s: The VID feature is not supported\n", __func__);
  495. break;
  496. case 0x08: /* 0.9V silicon */
  497. vdd = 900;
  498. break;
  499. case 0x10: /* 1.0V silicon */
  500. vdd = 1000;
  501. break;
  502. default: /* Other core voltage */
  503. vdd = -EINVAL;
  504. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  505. break;
  506. }
  507. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  508. return vdd;
  509. }
  510. __weak int board_switch_core_volt(u32 vdd)
  511. {
  512. return 0;
  513. }
  514. static int setup_core_volt(u32 vdd)
  515. {
  516. return board_setup_core_volt(vdd);
  517. }
  518. #ifdef CONFIG_SYS_FSL_DDR
  519. static void ddr_enable_0v9_volt(bool en)
  520. {
  521. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  522. u32 tmp;
  523. tmp = ddr_in32(&ddr->ddr_cdr1);
  524. if (en)
  525. tmp |= DDR_CDR1_V0PT9_EN;
  526. else
  527. tmp &= ~DDR_CDR1_V0PT9_EN;
  528. ddr_out32(&ddr->ddr_cdr1, tmp);
  529. }
  530. #endif
  531. int setup_chip_volt(void)
  532. {
  533. int vdd;
  534. vdd = get_core_volt_from_fuse();
  535. /* Nothing to do for silicons doesn't support VID */
  536. if (vdd < 0)
  537. return vdd;
  538. if (setup_core_volt(vdd))
  539. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  540. #ifdef CONFIG_SYS_HAS_SERDES
  541. if (setup_serdes_volt(vdd))
  542. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  543. #endif
  544. #ifdef CONFIG_SYS_FSL_DDR
  545. if (vdd == 900)
  546. ddr_enable_0v9_volt(true);
  547. #endif
  548. return 0;
  549. }
  550. #ifdef CONFIG_FSL_PFE
  551. void init_pfe_scfg_dcfg_regs(void)
  552. {
  553. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  554. u32 ecccr2;
  555. out_be32(&scfg->pfeasbcr,
  556. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  557. out_be32(&scfg->pfebsbcr,
  558. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  559. /* CCI-400 QoS settings for PFE */
  560. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  561. | SCFG_WR_QOS1_PFE2_QOS));
  562. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  563. | SCFG_RD_QOS1_PFE2_QOS));
  564. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  565. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  566. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  567. }
  568. #endif
  569. void fsl_lsch2_early_init_f(void)
  570. {
  571. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  572. CONFIG_SYS_CCI400_OFFSET);
  573. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  574. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  575. enum boot_src src;
  576. #endif
  577. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  578. enable_layerscape_ns_access();
  579. #endif
  580. #ifdef CONFIG_FSL_IFC
  581. init_early_memctl_regs(); /* tighten IFC timing */
  582. #endif
  583. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  584. src = get_boot_src();
  585. if (src != BOOT_SOURCE_QSPI_NOR)
  586. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  587. #else
  588. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  589. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  590. #endif
  591. #endif
  592. /* Make SEC reads and writes snoopable */
  593. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  594. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  595. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  596. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
  597. SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
  598. SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  599. SCFG_SNPCNFGCR_SATAWRSNP);
  600. #elif defined(CONFIG_ARCH_LS1012A)
  601. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  602. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  603. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  604. SCFG_SNPCNFGCR_SATAWRSNP);
  605. #else
  606. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  607. SCFG_SNPCNFGCR_SECWRSNP |
  608. SCFG_SNPCNFGCR_SATARDSNP |
  609. SCFG_SNPCNFGCR_SATAWRSNP);
  610. #endif
  611. /*
  612. * Enable snoop requests and DVM message requests for
  613. * Slave insterface S4 (A53 core cluster)
  614. */
  615. if (current_el() == 3) {
  616. out_le32(&cci->slave[4].snoop_ctrl,
  617. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  618. }
  619. /*
  620. * Program Central Security Unit (CSU) to grant access
  621. * permission for USB 2.0 controller
  622. */
  623. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  624. if (current_el() == 3)
  625. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  626. #endif
  627. /* Erratum */
  628. erratum_a008850_early(); /* part 1 of 2 */
  629. erratum_a009929();
  630. erratum_a009660();
  631. erratum_a010539();
  632. erratum_a009008();
  633. erratum_a009798();
  634. erratum_a008997();
  635. erratum_a009007();
  636. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  637. set_icids();
  638. #endif
  639. }
  640. #endif
  641. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  642. int fspi_ahb_init(void)
  643. {
  644. /* Enable 4bytes address support and fast read */
  645. u32 *fspi_lut, lut_key, *fspi_key;
  646. fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
  647. fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
  648. lut_key = in_be32(fspi_key);
  649. if (lut_key == SYS_NXP_FSPI_LUTKEY) {
  650. /* That means the register is BE */
  651. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  652. /* Unlock the lut table */
  653. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  654. /* Create READ LUT */
  655. out_be32(fspi_lut, 0x0820040c);
  656. out_be32(fspi_lut + 1, 0x24003008);
  657. out_be32(fspi_lut + 2, 0x00000000);
  658. /* Lock the lut table */
  659. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  660. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  661. } else {
  662. /* That means the register is LE */
  663. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  664. /* Unlock the lut table */
  665. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  666. /* Create READ LUT */
  667. out_le32(fspi_lut, 0x0820040c);
  668. out_le32(fspi_lut + 1, 0x24003008);
  669. out_le32(fspi_lut + 2, 0x00000000);
  670. /* Lock the lut table */
  671. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  672. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  673. }
  674. return 0;
  675. }
  676. #endif
  677. #ifdef CONFIG_QSPI_AHB_INIT
  678. /* Enable 4bytes address support and fast read */
  679. int qspi_ahb_init(void)
  680. {
  681. u32 *qspi_lut, lut_key, *qspi_key;
  682. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  683. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  684. lut_key = in_be32(qspi_key);
  685. if (lut_key == 0x5af05af0) {
  686. /* That means the register is BE */
  687. out_be32(qspi_key, 0x5af05af0);
  688. /* Unlock the lut table */
  689. out_be32(qspi_key + 1, 0x00000002);
  690. out_be32(qspi_lut, 0x0820040c);
  691. out_be32(qspi_lut + 1, 0x1c080c08);
  692. out_be32(qspi_lut + 2, 0x00002400);
  693. /* Lock the lut table */
  694. out_be32(qspi_key, 0x5af05af0);
  695. out_be32(qspi_key + 1, 0x00000001);
  696. } else {
  697. /* That means the register is LE */
  698. out_le32(qspi_key, 0x5af05af0);
  699. /* Unlock the lut table */
  700. out_le32(qspi_key + 1, 0x00000002);
  701. out_le32(qspi_lut, 0x0820040c);
  702. out_le32(qspi_lut + 1, 0x1c080c08);
  703. out_le32(qspi_lut + 2, 0x00002400);
  704. /* Lock the lut table */
  705. out_le32(qspi_key, 0x5af05af0);
  706. out_le32(qspi_key + 1, 0x00000001);
  707. }
  708. return 0;
  709. }
  710. #endif
  711. #ifdef CONFIG_TFABOOT
  712. #define MAX_BOOTCMD_SIZE 512
  713. int fsl_setenv_bootcmd(void)
  714. {
  715. int ret;
  716. enum boot_src src = get_boot_src();
  717. char bootcmd_str[MAX_BOOTCMD_SIZE];
  718. switch (src) {
  719. #ifdef IFC_NOR_BOOTCOMMAND
  720. case BOOT_SOURCE_IFC_NOR:
  721. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  722. break;
  723. #endif
  724. #ifdef QSPI_NOR_BOOTCOMMAND
  725. case BOOT_SOURCE_QSPI_NOR:
  726. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  727. break;
  728. #endif
  729. #ifdef XSPI_NOR_BOOTCOMMAND
  730. case BOOT_SOURCE_XSPI_NOR:
  731. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  732. break;
  733. #endif
  734. #ifdef IFC_NAND_BOOTCOMMAND
  735. case BOOT_SOURCE_IFC_NAND:
  736. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  737. break;
  738. #endif
  739. #ifdef QSPI_NAND_BOOTCOMMAND
  740. case BOOT_SOURCE_QSPI_NAND:
  741. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  742. break;
  743. #endif
  744. #ifdef XSPI_NAND_BOOTCOMMAND
  745. case BOOT_SOURCE_XSPI_NAND:
  746. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  747. break;
  748. #endif
  749. #ifdef SD_BOOTCOMMAND
  750. case BOOT_SOURCE_SD_MMC:
  751. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  752. break;
  753. #endif
  754. #ifdef SD2_BOOTCOMMAND
  755. case BOOT_SOURCE_SD_MMC2:
  756. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  757. break;
  758. #endif
  759. default:
  760. #ifdef QSPI_NOR_BOOTCOMMAND
  761. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  762. #endif
  763. break;
  764. }
  765. ret = env_set("bootcmd", bootcmd_str);
  766. if (ret) {
  767. printf("Failed to set bootcmd: ret = %d\n", ret);
  768. return ret;
  769. }
  770. return 0;
  771. }
  772. int fsl_setenv_mcinitcmd(void)
  773. {
  774. int ret = 0;
  775. enum boot_src src = get_boot_src();
  776. switch (src) {
  777. #ifdef IFC_MC_INIT_CMD
  778. case BOOT_SOURCE_IFC_NAND:
  779. case BOOT_SOURCE_IFC_NOR:
  780. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  781. break;
  782. #endif
  783. #ifdef QSPI_MC_INIT_CMD
  784. case BOOT_SOURCE_QSPI_NAND:
  785. case BOOT_SOURCE_QSPI_NOR:
  786. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  787. break;
  788. #endif
  789. #ifdef XSPI_MC_INIT_CMD
  790. case BOOT_SOURCE_XSPI_NAND:
  791. case BOOT_SOURCE_XSPI_NOR:
  792. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  793. break;
  794. #endif
  795. #ifdef SD_MC_INIT_CMD
  796. case BOOT_SOURCE_SD_MMC:
  797. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  798. break;
  799. #endif
  800. #ifdef SD2_MC_INIT_CMD
  801. case BOOT_SOURCE_SD_MMC2:
  802. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  803. break;
  804. #endif
  805. default:
  806. #ifdef QSPI_MC_INIT_CMD
  807. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  808. #endif
  809. break;
  810. }
  811. if (ret) {
  812. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  813. return ret;
  814. }
  815. return 0;
  816. }
  817. #endif
  818. #ifdef CONFIG_BOARD_LATE_INIT
  819. __weak int fsl_board_late_init(void)
  820. {
  821. return 0;
  822. }
  823. int board_late_init(void)
  824. {
  825. #ifdef CONFIG_CHAIN_OF_TRUST
  826. fsl_setenv_chain_of_trust();
  827. #endif
  828. #ifdef CONFIG_TFABOOT
  829. /*
  830. * check if gd->env_addr is default_environment; then setenv bootcmd
  831. * and mcinitcmd.
  832. */
  833. #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
  834. if (gd->env_addr == (ulong)&default_environment[0]) {
  835. #else
  836. if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  837. #endif
  838. fsl_setenv_bootcmd();
  839. fsl_setenv_mcinitcmd();
  840. }
  841. /*
  842. * If the boot mode is secure, default environment is not present then
  843. * setenv command needs to be run by default
  844. */
  845. #ifdef CONFIG_CHAIN_OF_TRUST
  846. if ((fsl_check_boot_mode_secure() == 1)) {
  847. fsl_setenv_bootcmd();
  848. fsl_setenv_mcinitcmd();
  849. }
  850. #endif
  851. #endif
  852. #ifdef CONFIG_QSPI_AHB_INIT
  853. qspi_ahb_init();
  854. #endif
  855. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  856. fspi_ahb_init();
  857. #endif
  858. return fsl_board_late_init();
  859. }
  860. #endif