mp.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <asm/cache.h>
  8. #include <asm/io.h>
  9. #include <asm/system.h>
  10. #include <asm/arch/mp.h>
  11. #include <asm/arch/soc.h>
  12. #include "cpu.h"
  13. #include <asm/arch-fsl-layerscape/soc.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. void *get_spin_tbl_addr(void)
  16. {
  17. return &__spin_table;
  18. }
  19. phys_addr_t determine_mp_bootpg(void)
  20. {
  21. return (phys_addr_t)&secondary_boot_code;
  22. }
  23. void update_os_arch_secondary_cores(uint8_t os_arch)
  24. {
  25. u64 *table = get_spin_tbl_addr();
  26. int i;
  27. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  28. if (os_arch == IH_ARCH_DEFAULT)
  29. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  30. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  31. else
  32. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  33. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  34. }
  35. }
  36. #ifdef CONFIG_FSL_LSCH3
  37. void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  38. {
  39. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  40. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  41. u32 mpidr = 0;
  42. mpidr = ((cluster << 8) | core);
  43. /*
  44. * mpidr_el1 register value of core which needs to be released
  45. * is written to scratchrw[6] register
  46. */
  47. gur_out32(&gur->scratchrw[6], mpidr);
  48. asm volatile("dsb st" : : : "memory");
  49. rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  50. asm volatile("dsb st" : : : "memory");
  51. /*
  52. * scratchrw[6] register value is polled
  53. * when the value becomes zero, this means that this core is up
  54. * and running, next core can be released now
  55. */
  56. while (gur_in32(&gur->scratchrw[6]) != 0)
  57. ;
  58. }
  59. #endif
  60. int fsl_layerscape_wake_seconday_cores(void)
  61. {
  62. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  63. #ifdef CONFIG_FSL_LSCH3
  64. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  65. u32 svr, ver, cluster, type;
  66. int j = 0, cluster_cores = 0;
  67. #elif defined(CONFIG_FSL_LSCH2)
  68. struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  69. #endif
  70. u32 cores, cpu_up_mask = 1;
  71. int i, timeout = 10;
  72. u64 *table = get_spin_tbl_addr();
  73. #ifdef COUNTER_FREQUENCY_REAL
  74. /* update for secondary cores */
  75. __real_cntfrq = COUNTER_FREQUENCY_REAL;
  76. flush_dcache_range((unsigned long)&__real_cntfrq,
  77. (unsigned long)&__real_cntfrq + 8);
  78. #endif
  79. cores = cpu_mask();
  80. /* Clear spin table so that secondary processors
  81. * observe the correct value after waking up from wfe.
  82. */
  83. memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  84. flush_dcache_range((unsigned long)table,
  85. (unsigned long)table +
  86. (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  87. printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
  88. #ifdef CONFIG_FSL_LSCH3
  89. gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
  90. gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
  91. svr = gur_in32(&gur->svr);
  92. ver = SVR_SOC_VER(svr);
  93. if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
  94. gur_out32(&gur->scratchrw[6], 1);
  95. asm volatile("dsb st" : : : "memory");
  96. rst->brrl = cores;
  97. asm volatile("dsb st" : : : "memory");
  98. } else {
  99. /*
  100. * Release the cores out of reset one-at-a-time to avoid
  101. * power spikes
  102. */
  103. i = 0;
  104. cluster = in_le32(&gur->tp_cluster[i].lower);
  105. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  106. type = initiator_type(cluster, j);
  107. if (type &&
  108. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  109. cluster_cores++;
  110. }
  111. do {
  112. cluster = in_le32(&gur->tp_cluster[i].lower);
  113. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  114. type = initiator_type(cluster, j);
  115. if (type &&
  116. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  117. wake_secondary_core_n(i, j,
  118. cluster_cores);
  119. }
  120. i++;
  121. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  122. }
  123. #elif defined(CONFIG_FSL_LSCH2)
  124. scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
  125. scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
  126. asm volatile("dsb st" : : : "memory");
  127. gur_out32(&gur->brrl, cores);
  128. asm volatile("dsb st" : : : "memory");
  129. /* Bootup online cores */
  130. scfg_out32(&scfg->corebcr, cores);
  131. #endif
  132. /* This is needed as a precautionary measure.
  133. * If some code before this has accidentally released the secondary
  134. * cores then the pre-bootloader code will trap them in a "wfe" unless
  135. * the scratchrw[6] is set. In this case we need a sev here to get these
  136. * cores moving again.
  137. */
  138. asm volatile("sev");
  139. while (timeout--) {
  140. flush_dcache_range((unsigned long)table, (unsigned long)table +
  141. CONFIG_MAX_CPUS * 64);
  142. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  143. if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  144. SPIN_TABLE_ELEM_STATUS_IDX])
  145. cpu_up_mask |= 1 << i;
  146. }
  147. if (hweight32(cpu_up_mask) == hweight32(cores))
  148. break;
  149. udelay(10);
  150. }
  151. if (timeout <= 0) {
  152. printf("Not all cores (0x%x) are up (0x%x)\n",
  153. cores, cpu_up_mask);
  154. return 1;
  155. }
  156. printf("All (%d) cores are up.\n", hweight32(cores));
  157. return 0;
  158. }
  159. int is_core_valid(unsigned int core)
  160. {
  161. return !!((1 << core) & cpu_mask());
  162. }
  163. static int is_pos_valid(unsigned int pos)
  164. {
  165. return !!((1 << pos) & cpu_pos_mask());
  166. }
  167. int is_core_online(u64 cpu_id)
  168. {
  169. u64 *table;
  170. int pos = id_to_core(cpu_id);
  171. table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
  172. return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
  173. }
  174. int cpu_reset(u32 nr)
  175. {
  176. puts("Feature is not implemented.\n");
  177. return 0;
  178. }
  179. int cpu_disable(u32 nr)
  180. {
  181. puts("Feature is not implemented.\n");
  182. return 0;
  183. }
  184. static int core_to_pos(int nr)
  185. {
  186. u32 cores = cpu_pos_mask();
  187. int i, count = 0;
  188. if (nr == 0) {
  189. return 0;
  190. } else if (nr >= hweight32(cores)) {
  191. puts("Not a valid core number.\n");
  192. return -1;
  193. }
  194. for (i = 1; i < 32; i++) {
  195. if (is_pos_valid(i)) {
  196. count++;
  197. if (count == nr)
  198. break;
  199. }
  200. }
  201. if (count != nr)
  202. return -1;
  203. return i;
  204. }
  205. int cpu_status(u32 nr)
  206. {
  207. u64 *table;
  208. int pos;
  209. if (nr == 0) {
  210. table = (u64 *)get_spin_tbl_addr();
  211. printf("table base @ 0x%p\n", table);
  212. } else {
  213. pos = core_to_pos(nr);
  214. if (pos < 0)
  215. return -1;
  216. table = (u64 *)get_spin_tbl_addr() + pos *
  217. WORDS_PER_SPIN_TABLE_ENTRY;
  218. printf("table @ 0x%p\n", table);
  219. printf(" addr - 0x%016llx\n",
  220. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
  221. printf(" status - 0x%016llx\n",
  222. table[SPIN_TABLE_ELEM_STATUS_IDX]);
  223. printf(" lpid - 0x%016llx\n",
  224. table[SPIN_TABLE_ELEM_LPID_IDX]);
  225. }
  226. return 0;
  227. }
  228. int cpu_release(u32 nr, int argc, char * const argv[])
  229. {
  230. u64 boot_addr;
  231. u64 *table = (u64 *)get_spin_tbl_addr();
  232. int pos;
  233. pos = core_to_pos(nr);
  234. if (pos <= 0)
  235. return -1;
  236. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  237. boot_addr = simple_strtoull(argv[0], NULL, 16);
  238. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
  239. flush_dcache_range((unsigned long)table,
  240. (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
  241. asm volatile("dsb st");
  242. smp_kick_all_cpus(); /* only those with entry addr set will run */
  243. /*
  244. * When the first release command runs, all cores are set to go. Those
  245. * without a valid entry address will be trapped by "wfe". "sev" kicks
  246. * them off to check the address again. When set, they continue to run.
  247. */
  248. asm volatile("sev");
  249. return 0;
  250. }