cache_v8.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. *
  6. * (C) Copyright 2016
  7. * Alexander Graf <agraf@suse.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <hang.h>
  12. #include <asm/cache.h>
  13. #include <asm/system.h>
  14. #include <asm/armv8/mmu.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  17. /*
  18. * With 4k page granule, a virtual address is split into 4 lookup parts
  19. * spanning 9 bits each:
  20. *
  21. * _______________________________________________
  22. * | | | | | | |
  23. * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
  24. * |_______|_______|_______|_______|_______|_______|
  25. * 63-48 47-39 38-30 29-21 20-12 11-00
  26. *
  27. * mask page size
  28. *
  29. * Lv0: FF8000000000 --
  30. * Lv1: 7FC0000000 1G
  31. * Lv2: 3FE00000 2M
  32. * Lv3: 1FF000 4K
  33. * off: FFF
  34. */
  35. u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
  36. {
  37. u64 max_addr = 0;
  38. u64 ips, va_bits;
  39. u64 tcr;
  40. int i;
  41. /* Find the largest address we need to support */
  42. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  43. max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
  44. /* Calculate the maximum physical (and thus virtual) address */
  45. if (max_addr > (1ULL << 44)) {
  46. ips = 5;
  47. va_bits = 48;
  48. } else if (max_addr > (1ULL << 42)) {
  49. ips = 4;
  50. va_bits = 44;
  51. } else if (max_addr > (1ULL << 40)) {
  52. ips = 3;
  53. va_bits = 42;
  54. } else if (max_addr > (1ULL << 36)) {
  55. ips = 2;
  56. va_bits = 40;
  57. } else if (max_addr > (1ULL << 32)) {
  58. ips = 1;
  59. va_bits = 36;
  60. } else {
  61. ips = 0;
  62. va_bits = 32;
  63. }
  64. if (el == 1) {
  65. tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
  66. } else if (el == 2) {
  67. tcr = TCR_EL2_RSVD | (ips << 16);
  68. } else {
  69. tcr = TCR_EL3_RSVD | (ips << 16);
  70. }
  71. /* PTWs cacheable, inner/outer WBWA and inner shareable */
  72. tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
  73. tcr |= TCR_T0SZ(va_bits);
  74. if (pips)
  75. *pips = ips;
  76. if (pva_bits)
  77. *pva_bits = va_bits;
  78. return tcr;
  79. }
  80. #define MAX_PTE_ENTRIES 512
  81. static int pte_type(u64 *pte)
  82. {
  83. return *pte & PTE_TYPE_MASK;
  84. }
  85. /* Returns the LSB number for a PTE on level <level> */
  86. static int level2shift(int level)
  87. {
  88. /* Page is 12 bits wide, every level translates 9 bits */
  89. return (12 + 9 * (3 - level));
  90. }
  91. static u64 *find_pte(u64 addr, int level)
  92. {
  93. int start_level = 0;
  94. u64 *pte;
  95. u64 idx;
  96. u64 va_bits;
  97. int i;
  98. debug("addr=%llx level=%d\n", addr, level);
  99. get_tcr(0, NULL, &va_bits);
  100. if (va_bits < 39)
  101. start_level = 1;
  102. if (level < start_level)
  103. return NULL;
  104. /* Walk through all page table levels to find our PTE */
  105. pte = (u64*)gd->arch.tlb_addr;
  106. for (i = start_level; i < 4; i++) {
  107. idx = (addr >> level2shift(i)) & 0x1FF;
  108. pte += idx;
  109. debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
  110. /* Found it */
  111. if (i == level)
  112. return pte;
  113. /* PTE is no table (either invalid or block), can't traverse */
  114. if (pte_type(pte) != PTE_TYPE_TABLE)
  115. return NULL;
  116. /* Off to the next level */
  117. pte = (u64*)(*pte & 0x0000fffffffff000ULL);
  118. }
  119. /* Should never reach here */
  120. return NULL;
  121. }
  122. /* Returns and creates a new full table (512 entries) */
  123. static u64 *create_table(void)
  124. {
  125. u64 *new_table = (u64*)gd->arch.tlb_fillptr;
  126. u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
  127. /* Allocate MAX_PTE_ENTRIES pte entries */
  128. gd->arch.tlb_fillptr += pt_len;
  129. if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
  130. panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
  131. "Please increase the size in get_page_table_size()",
  132. gd->arch.tlb_fillptr - gd->arch.tlb_addr,
  133. gd->arch.tlb_size);
  134. /* Mark all entries as invalid */
  135. memset(new_table, 0, pt_len);
  136. return new_table;
  137. }
  138. static void set_pte_table(u64 *pte, u64 *table)
  139. {
  140. /* Point *pte to the new table */
  141. debug("Setting %p to addr=%p\n", pte, table);
  142. *pte = PTE_TYPE_TABLE | (ulong)table;
  143. }
  144. /* Splits a block PTE into table with subpages spanning the old block */
  145. static void split_block(u64 *pte, int level)
  146. {
  147. u64 old_pte = *pte;
  148. u64 *new_table;
  149. u64 i = 0;
  150. /* level describes the parent level, we need the child ones */
  151. int levelshift = level2shift(level + 1);
  152. if (pte_type(pte) != PTE_TYPE_BLOCK)
  153. panic("PTE %p (%llx) is not a block. Some driver code wants to "
  154. "modify dcache settings for an range not covered in "
  155. "mem_map.", pte, old_pte);
  156. new_table = create_table();
  157. debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
  158. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  159. new_table[i] = old_pte | (i << levelshift);
  160. /* Level 3 block PTEs have the table type */
  161. if ((level + 1) == 3)
  162. new_table[i] |= PTE_TYPE_TABLE;
  163. debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
  164. }
  165. /* Set the new table into effect */
  166. set_pte_table(pte, new_table);
  167. }
  168. /* Add one mm_region map entry to the page tables */
  169. static void add_map(struct mm_region *map)
  170. {
  171. u64 *pte;
  172. u64 virt = map->virt;
  173. u64 phys = map->phys;
  174. u64 size = map->size;
  175. u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
  176. u64 blocksize;
  177. int level;
  178. u64 *new_table;
  179. while (size) {
  180. pte = find_pte(virt, 0);
  181. if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
  182. debug("Creating table for virt 0x%llx\n", virt);
  183. new_table = create_table();
  184. set_pte_table(pte, new_table);
  185. }
  186. for (level = 1; level < 4; level++) {
  187. pte = find_pte(virt, level);
  188. if (!pte)
  189. panic("pte not found\n");
  190. blocksize = 1ULL << level2shift(level);
  191. debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
  192. virt, size, blocksize);
  193. if (size >= blocksize && !(virt & (blocksize - 1))) {
  194. /* Page fits, create block PTE */
  195. debug("Setting PTE %p to block virt=%llx\n",
  196. pte, virt);
  197. if (level == 3)
  198. *pte = phys | attrs | PTE_TYPE_PAGE;
  199. else
  200. *pte = phys | attrs;
  201. virt += blocksize;
  202. phys += blocksize;
  203. size -= blocksize;
  204. break;
  205. } else if (pte_type(pte) == PTE_TYPE_FAULT) {
  206. /* Page doesn't fit, create subpages */
  207. debug("Creating subtable for virt 0x%llx blksize=%llx\n",
  208. virt, blocksize);
  209. new_table = create_table();
  210. set_pte_table(pte, new_table);
  211. } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
  212. debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
  213. virt, blocksize);
  214. split_block(pte, level);
  215. }
  216. }
  217. }
  218. }
  219. enum pte_type {
  220. PTE_INVAL,
  221. PTE_BLOCK,
  222. PTE_LEVEL,
  223. };
  224. /*
  225. * This is a recursively called function to count the number of
  226. * page tables we need to cover a particular PTE range. If you
  227. * call this with level = -1 you basically get the full 48 bit
  228. * coverage.
  229. */
  230. static int count_required_pts(u64 addr, int level, u64 maxaddr)
  231. {
  232. int levelshift = level2shift(level);
  233. u64 levelsize = 1ULL << levelshift;
  234. u64 levelmask = levelsize - 1;
  235. u64 levelend = addr + levelsize;
  236. int r = 0;
  237. int i;
  238. enum pte_type pte_type = PTE_INVAL;
  239. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
  240. struct mm_region *map = &mem_map[i];
  241. u64 start = map->virt;
  242. u64 end = start + map->size;
  243. /* Check if the PTE would overlap with the map */
  244. if (max(addr, start) <= min(levelend, end)) {
  245. start = max(addr, start);
  246. end = min(levelend, end);
  247. /* We need a sub-pt for this level */
  248. if ((start & levelmask) || (end & levelmask)) {
  249. pte_type = PTE_LEVEL;
  250. break;
  251. }
  252. /* Lv0 can not do block PTEs, so do levels here too */
  253. if (level <= 0) {
  254. pte_type = PTE_LEVEL;
  255. break;
  256. }
  257. /* PTE is active, but fits into a block */
  258. pte_type = PTE_BLOCK;
  259. }
  260. }
  261. /*
  262. * Block PTEs at this level are already covered by the parent page
  263. * table, so we only need to count sub page tables.
  264. */
  265. if (pte_type == PTE_LEVEL) {
  266. int sublevel = level + 1;
  267. u64 sublevelsize = 1ULL << level2shift(sublevel);
  268. /* Account for the new sub page table ... */
  269. r = 1;
  270. /* ... and for all child page tables that one might have */
  271. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  272. r += count_required_pts(addr, sublevel, maxaddr);
  273. addr += sublevelsize;
  274. if (addr >= maxaddr) {
  275. /*
  276. * We reached the end of address space, no need
  277. * to look any further.
  278. */
  279. break;
  280. }
  281. }
  282. }
  283. return r;
  284. }
  285. /* Returns the estimated required size of all page tables */
  286. __weak u64 get_page_table_size(void)
  287. {
  288. u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
  289. u64 size = 0;
  290. u64 va_bits;
  291. int start_level = 0;
  292. get_tcr(0, NULL, &va_bits);
  293. if (va_bits < 39)
  294. start_level = 1;
  295. /* Account for all page tables we would need to cover our memory map */
  296. size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
  297. /*
  298. * We need to duplicate our page table once to have an emergency pt to
  299. * resort to when splitting page tables later on
  300. */
  301. size *= 2;
  302. /*
  303. * We may need to split page tables later on if dcache settings change,
  304. * so reserve up to 4 (random pick) page tables for that.
  305. */
  306. size += one_pt * 4;
  307. return size;
  308. }
  309. void setup_pgtables(void)
  310. {
  311. int i;
  312. if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
  313. panic("Page table pointer not setup.");
  314. /*
  315. * Allocate the first level we're on with invalidate entries.
  316. * If the starting level is 0 (va_bits >= 39), then this is our
  317. * Lv0 page table, otherwise it's the entry Lv1 page table.
  318. */
  319. create_table();
  320. /* Now add all MMU table entries one after another to the table */
  321. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  322. add_map(&mem_map[i]);
  323. }
  324. static void setup_all_pgtables(void)
  325. {
  326. u64 tlb_addr = gd->arch.tlb_addr;
  327. u64 tlb_size = gd->arch.tlb_size;
  328. /* Reset the fill ptr */
  329. gd->arch.tlb_fillptr = tlb_addr;
  330. /* Create normal system page tables */
  331. setup_pgtables();
  332. /* Create emergency page tables */
  333. gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
  334. (uintptr_t)gd->arch.tlb_addr;
  335. gd->arch.tlb_addr = gd->arch.tlb_fillptr;
  336. setup_pgtables();
  337. gd->arch.tlb_emerg = gd->arch.tlb_addr;
  338. gd->arch.tlb_addr = tlb_addr;
  339. gd->arch.tlb_size = tlb_size;
  340. }
  341. /* to activate the MMU we need to set up virtual memory */
  342. __weak void mmu_setup(void)
  343. {
  344. int el;
  345. /* Set up page tables only once */
  346. if (!gd->arch.tlb_fillptr)
  347. setup_all_pgtables();
  348. el = current_el();
  349. set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
  350. MEMORY_ATTRIBUTES);
  351. /* enable the mmu */
  352. set_sctlr(get_sctlr() | CR_M);
  353. }
  354. /*
  355. * Performs a invalidation of the entire data cache at all levels
  356. */
  357. void invalidate_dcache_all(void)
  358. {
  359. __asm_invalidate_dcache_all();
  360. __asm_invalidate_l3_dcache();
  361. }
  362. /*
  363. * Performs a clean & invalidation of the entire data cache at all levels.
  364. * This function needs to be inline to avoid using stack.
  365. * __asm_flush_l3_dcache return status of timeout
  366. */
  367. inline void flush_dcache_all(void)
  368. {
  369. int ret;
  370. __asm_flush_dcache_all();
  371. ret = __asm_flush_l3_dcache();
  372. if (ret)
  373. debug("flushing dcache returns 0x%x\n", ret);
  374. else
  375. debug("flushing dcache successfully.\n");
  376. }
  377. #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
  378. /*
  379. * Invalidates range in all levels of D-cache/unified cache
  380. */
  381. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  382. {
  383. __asm_invalidate_dcache_range(start, stop);
  384. }
  385. /*
  386. * Flush range(clean & invalidate) from all levels of D-cache/unified cache
  387. */
  388. void flush_dcache_range(unsigned long start, unsigned long stop)
  389. {
  390. __asm_flush_dcache_range(start, stop);
  391. }
  392. #else
  393. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  394. {
  395. }
  396. void flush_dcache_range(unsigned long start, unsigned long stop)
  397. {
  398. }
  399. #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
  400. void dcache_enable(void)
  401. {
  402. /* The data cache is not active unless the mmu is enabled */
  403. if (!(get_sctlr() & CR_M)) {
  404. invalidate_dcache_all();
  405. __asm_invalidate_tlb_all();
  406. mmu_setup();
  407. }
  408. set_sctlr(get_sctlr() | CR_C);
  409. }
  410. void dcache_disable(void)
  411. {
  412. uint32_t sctlr;
  413. sctlr = get_sctlr();
  414. /* if cache isn't enabled no need to disable */
  415. if (!(sctlr & CR_C))
  416. return;
  417. set_sctlr(sctlr & ~(CR_C|CR_M));
  418. flush_dcache_all();
  419. __asm_invalidate_tlb_all();
  420. }
  421. int dcache_status(void)
  422. {
  423. return (get_sctlr() & CR_C) != 0;
  424. }
  425. u64 *__weak arch_get_page_table(void) {
  426. puts("No page table offset defined\n");
  427. return NULL;
  428. }
  429. static bool is_aligned(u64 addr, u64 size, u64 align)
  430. {
  431. return !(addr & (align - 1)) && !(size & (align - 1));
  432. }
  433. /* Use flag to indicate if attrs has more than d-cache attributes */
  434. static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
  435. {
  436. int levelshift = level2shift(level);
  437. u64 levelsize = 1ULL << levelshift;
  438. u64 *pte = find_pte(start, level);
  439. /* Can we can just modify the current level block PTE? */
  440. if (is_aligned(start, size, levelsize)) {
  441. if (flag) {
  442. *pte &= ~PMD_ATTRMASK;
  443. *pte |= attrs & PMD_ATTRMASK;
  444. } else {
  445. *pte &= ~PMD_ATTRINDX_MASK;
  446. *pte |= attrs & PMD_ATTRINDX_MASK;
  447. }
  448. debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
  449. return levelsize;
  450. }
  451. /* Unaligned or doesn't fit, maybe split block into table */
  452. debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
  453. /* Maybe we need to split the block into a table */
  454. if (pte_type(pte) == PTE_TYPE_BLOCK)
  455. split_block(pte, level);
  456. /* And then double-check it became a table or already is one */
  457. if (pte_type(pte) != PTE_TYPE_TABLE)
  458. panic("PTE %p (%llx) for addr=%llx should be a table",
  459. pte, *pte, start);
  460. /* Roll on to the next page table level */
  461. return 0;
  462. }
  463. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  464. enum dcache_option option)
  465. {
  466. u64 attrs = PMD_ATTRINDX(option);
  467. u64 real_start = start;
  468. u64 real_size = size;
  469. debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
  470. if (!gd->arch.tlb_emerg)
  471. panic("Emergency page table not setup.");
  472. /*
  473. * We can not modify page tables that we're currently running on,
  474. * so we first need to switch to the "emergency" page tables where
  475. * we can safely modify our primary page tables and then switch back
  476. */
  477. __asm_switch_ttbr(gd->arch.tlb_emerg);
  478. /*
  479. * Loop through the address range until we find a page granule that fits
  480. * our alignment constraints, then set it to the new cache attributes
  481. */
  482. while (size > 0) {
  483. int level;
  484. u64 r;
  485. for (level = 1; level < 4; level++) {
  486. /* Set d-cache attributes only */
  487. r = set_one_region(start, size, attrs, false, level);
  488. if (r) {
  489. /* PTE successfully replaced */
  490. size -= r;
  491. start += r;
  492. break;
  493. }
  494. }
  495. }
  496. /* We're done modifying page tables, switch back to our primary ones */
  497. __asm_switch_ttbr(gd->arch.tlb_addr);
  498. /*
  499. * Make sure there's nothing stale in dcache for a region that might
  500. * have caches off now
  501. */
  502. flush_dcache_range(real_start, real_start + real_size);
  503. }
  504. /*
  505. * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
  506. * The procecess is break-before-make. The target region will be marked as
  507. * invalid during the process of changing.
  508. */
  509. void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
  510. {
  511. int level;
  512. u64 r, size, start;
  513. start = addr;
  514. size = siz;
  515. /*
  516. * Loop through the address range until we find a page granule that fits
  517. * our alignment constraints, then set it to "invalid".
  518. */
  519. while (size > 0) {
  520. for (level = 1; level < 4; level++) {
  521. /* Set PTE to fault */
  522. r = set_one_region(start, size, PTE_TYPE_FAULT, true,
  523. level);
  524. if (r) {
  525. /* PTE successfully invalidated */
  526. size -= r;
  527. start += r;
  528. break;
  529. }
  530. }
  531. }
  532. flush_dcache_range(gd->arch.tlb_addr,
  533. gd->arch.tlb_addr + gd->arch.tlb_size);
  534. __asm_invalidate_tlb_all();
  535. /*
  536. * Loop through the address range until we find a page granule that fits
  537. * our alignment constraints, then set it to the new cache attributes
  538. */
  539. start = addr;
  540. size = siz;
  541. while (size > 0) {
  542. for (level = 1; level < 4; level++) {
  543. /* Set PTE to new attributes */
  544. r = set_one_region(start, size, attrs, true, level);
  545. if (r) {
  546. /* PTE successfully updated */
  547. size -= r;
  548. start += r;
  549. break;
  550. }
  551. }
  552. }
  553. flush_dcache_range(gd->arch.tlb_addr,
  554. gd->arch.tlb_addr + gd->arch.tlb_size);
  555. __asm_invalidate_tlb_all();
  556. }
  557. #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  558. /*
  559. * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
  560. * running however really wants to have dcache and the MMU active. Check that
  561. * everything is sane and give the developer a hint if it isn't.
  562. */
  563. #ifndef CONFIG_SPL_BUILD
  564. #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
  565. #endif
  566. void invalidate_dcache_all(void)
  567. {
  568. }
  569. void flush_dcache_all(void)
  570. {
  571. }
  572. void dcache_enable(void)
  573. {
  574. }
  575. void dcache_disable(void)
  576. {
  577. }
  578. int dcache_status(void)
  579. {
  580. return 0;
  581. }
  582. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  583. enum dcache_option option)
  584. {
  585. }
  586. #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  587. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  588. void icache_enable(void)
  589. {
  590. invalidate_icache_all();
  591. set_sctlr(get_sctlr() | CR_I);
  592. }
  593. void icache_disable(void)
  594. {
  595. set_sctlr(get_sctlr() & ~CR_I);
  596. }
  597. int icache_status(void)
  598. {
  599. return (get_sctlr() & CR_I) != 0;
  600. }
  601. void invalidate_icache_all(void)
  602. {
  603. __asm_invalidate_icache_all();
  604. __asm_invalidate_l3_icache();
  605. }
  606. #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  607. void icache_enable(void)
  608. {
  609. }
  610. void icache_disable(void)
  611. {
  612. }
  613. int icache_status(void)
  614. {
  615. return 0;
  616. }
  617. void invalidate_icache_all(void)
  618. {
  619. }
  620. #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  621. /*
  622. * Enable dCache & iCache, whether cache is actually enabled
  623. * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
  624. */
  625. void __weak enable_caches(void)
  626. {
  627. icache_enable();
  628. dcache_enable();
  629. }