generic.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <net.h>
  9. #include <asm/cache.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/mach-imx/sys_proto.h>
  15. #include <env.h>
  16. #include <netdev.h>
  17. #ifdef CONFIG_FSL_ESDHC_IMX
  18. #include <fsl_esdhc_imx.h>
  19. #endif
  20. #ifdef CONFIG_FSL_ESDHC_IMX
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #endif
  23. static char soc_type[] = "xx0";
  24. #ifdef CONFIG_MXC_OCOTP
  25. void enable_ocotp_clk(unsigned char enable)
  26. {
  27. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  28. u32 reg;
  29. reg = readl(&ccm->ccgr6);
  30. if (enable)
  31. reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
  32. else
  33. reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
  34. writel(reg, &ccm->ccgr6);
  35. }
  36. #endif
  37. static u32 get_mcu_main_clk(void)
  38. {
  39. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  40. u32 ccm_ccsr, ccm_cacrr, armclk_div;
  41. u32 sysclk_sel, pll_pfd_sel = 0;
  42. u32 freq = 0;
  43. ccm_ccsr = readl(&ccm->ccsr);
  44. sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
  45. sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
  46. ccm_cacrr = readl(&ccm->cacrr);
  47. armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
  48. armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
  49. armclk_div += 1;
  50. switch (sysclk_sel) {
  51. case 0:
  52. freq = FASE_CLK_FREQ;
  53. break;
  54. case 1:
  55. freq = SLOW_CLK_FREQ;
  56. break;
  57. case 2:
  58. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
  59. pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
  60. if (pll_pfd_sel == 0)
  61. freq = PLL2_MAIN_FREQ;
  62. else if (pll_pfd_sel == 1)
  63. freq = PLL2_PFD1_FREQ;
  64. else if (pll_pfd_sel == 2)
  65. freq = PLL2_PFD2_FREQ;
  66. else if (pll_pfd_sel == 3)
  67. freq = PLL2_PFD3_FREQ;
  68. else if (pll_pfd_sel == 4)
  69. freq = PLL2_PFD4_FREQ;
  70. break;
  71. case 3:
  72. freq = PLL2_MAIN_FREQ;
  73. break;
  74. case 4:
  75. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
  76. pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
  77. if (pll_pfd_sel == 0)
  78. freq = PLL1_MAIN_FREQ;
  79. else if (pll_pfd_sel == 1)
  80. freq = PLL1_PFD1_FREQ;
  81. else if (pll_pfd_sel == 2)
  82. freq = PLL1_PFD2_FREQ;
  83. else if (pll_pfd_sel == 3)
  84. freq = PLL1_PFD3_FREQ;
  85. else if (pll_pfd_sel == 4)
  86. freq = PLL1_PFD4_FREQ;
  87. break;
  88. case 5:
  89. freq = PLL3_MAIN_FREQ;
  90. break;
  91. default:
  92. printf("unsupported system clock select\n");
  93. }
  94. return freq / armclk_div;
  95. }
  96. static u32 get_bus_clk(void)
  97. {
  98. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  99. u32 ccm_cacrr, busclk_div;
  100. ccm_cacrr = readl(&ccm->cacrr);
  101. busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
  102. busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
  103. busclk_div += 1;
  104. return get_mcu_main_clk() / busclk_div;
  105. }
  106. static u32 get_ipg_clk(void)
  107. {
  108. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  109. u32 ccm_cacrr, ipgclk_div;
  110. ccm_cacrr = readl(&ccm->cacrr);
  111. ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
  112. ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
  113. ipgclk_div += 1;
  114. return get_bus_clk() / ipgclk_div;
  115. }
  116. static u32 get_uart_clk(void)
  117. {
  118. return get_ipg_clk();
  119. }
  120. static u32 get_sdhc_clk(void)
  121. {
  122. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  123. u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
  124. u32 freq = 0;
  125. ccm_cscmr1 = readl(&ccm->cscmr1);
  126. sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
  127. sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
  128. ccm_cscdr2 = readl(&ccm->cscdr2);
  129. sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
  130. sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
  131. sdhc_clk_div += 1;
  132. switch (sdhc_clk_sel) {
  133. case 0:
  134. freq = PLL3_MAIN_FREQ;
  135. break;
  136. case 1:
  137. freq = PLL3_PFD3_FREQ;
  138. break;
  139. case 2:
  140. freq = PLL1_PFD3_FREQ;
  141. break;
  142. case 3:
  143. freq = get_bus_clk();
  144. break;
  145. }
  146. return freq / sdhc_clk_div;
  147. }
  148. u32 get_fec_clk(void)
  149. {
  150. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  151. u32 ccm_cscmr2, rmii_clk_sel;
  152. u32 freq = 0;
  153. ccm_cscmr2 = readl(&ccm->cscmr2);
  154. rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
  155. rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
  156. switch (rmii_clk_sel) {
  157. case 0:
  158. freq = ENET_EXTERNAL_CLK;
  159. break;
  160. case 1:
  161. freq = AUDIO_EXTERNAL_CLK;
  162. break;
  163. case 2:
  164. freq = PLL5_MAIN_FREQ;
  165. break;
  166. case 3:
  167. freq = PLL5_MAIN_FREQ / 2;
  168. break;
  169. }
  170. return freq;
  171. }
  172. static u32 get_i2c_clk(void)
  173. {
  174. return get_ipg_clk();
  175. }
  176. static u32 get_dspi_clk(void)
  177. {
  178. return get_ipg_clk();
  179. }
  180. u32 get_lpuart_clk(void)
  181. {
  182. return get_uart_clk();
  183. }
  184. unsigned int mxc_get_clock(enum mxc_clock clk)
  185. {
  186. switch (clk) {
  187. case MXC_ARM_CLK:
  188. return get_mcu_main_clk();
  189. case MXC_BUS_CLK:
  190. return get_bus_clk();
  191. case MXC_IPG_CLK:
  192. return get_ipg_clk();
  193. case MXC_UART_CLK:
  194. return get_uart_clk();
  195. case MXC_ESDHC_CLK:
  196. return get_sdhc_clk();
  197. case MXC_FEC_CLK:
  198. return get_fec_clk();
  199. case MXC_I2C_CLK:
  200. return get_i2c_clk();
  201. case MXC_DSPI_CLK:
  202. return get_dspi_clk();
  203. default:
  204. break;
  205. }
  206. return -1;
  207. }
  208. /* Dump some core clocks */
  209. int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
  210. char * const argv[])
  211. {
  212. printf("\n");
  213. printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  214. printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
  215. printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
  216. return 0;
  217. }
  218. U_BOOT_CMD(
  219. clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
  220. "display clocks",
  221. ""
  222. );
  223. #ifdef CONFIG_FEC_MXC
  224. __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  225. {
  226. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  227. struct fuse_bank *bank = &ocotp->bank[4];
  228. struct fuse_bank4_regs *fuse =
  229. (struct fuse_bank4_regs *)bank->fuse_regs;
  230. u32 value = readl(&fuse->mac_addr0);
  231. mac[0] = (value >> 8);
  232. mac[1] = value;
  233. value = readl(&fuse->mac_addr1);
  234. mac[2] = value >> 24;
  235. mac[3] = value >> 16;
  236. mac[4] = value >> 8;
  237. mac[5] = value;
  238. }
  239. #endif
  240. u32 get_cpu_rev(void)
  241. {
  242. return MXC_CPU_VF610 << 12;
  243. }
  244. #if defined(CONFIG_DISPLAY_CPUINFO)
  245. static char *get_reset_cause(void)
  246. {
  247. u32 cause;
  248. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  249. cause = readl(&src_regs->srsr);
  250. writel(cause, &src_regs->srsr);
  251. if (cause & SRC_SRSR_POR_RST)
  252. return "POWER ON RESET";
  253. else if (cause & SRC_SRSR_WDOG_A5)
  254. return "WDOG A5";
  255. else if (cause & SRC_SRSR_WDOG_M4)
  256. return "WDOG M4";
  257. else if (cause & SRC_SRSR_JTAG_RST)
  258. return "JTAG HIGH-Z";
  259. else if (cause & SRC_SRSR_SW_RST)
  260. return "SW RESET";
  261. else if (cause & SRC_SRSR_RESETB)
  262. return "EXTERNAL RESET";
  263. else
  264. return "unknown reset";
  265. }
  266. int print_cpuinfo(void)
  267. {
  268. printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
  269. soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
  270. printf("Reset cause: %s\n", get_reset_cause());
  271. return 0;
  272. }
  273. #endif
  274. int arch_cpu_init(void)
  275. {
  276. struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
  277. soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
  278. soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
  279. return 0;
  280. }
  281. #ifdef CONFIG_ARCH_MISC_INIT
  282. int arch_misc_init(void)
  283. {
  284. char soc[6];
  285. strcpy(soc, "vf");
  286. strcat(soc, soc_type);
  287. env_set("soc", soc);
  288. return 0;
  289. }
  290. #endif
  291. int cpu_eth_init(bd_t *bis)
  292. {
  293. int rc = -ENODEV;
  294. #if defined(CONFIG_FEC_MXC)
  295. rc = fecmxc_initialize(bis);
  296. #endif
  297. return rc;
  298. }
  299. #ifdef CONFIG_FSL_ESDHC_IMX
  300. int cpu_mmc_init(bd_t *bis)
  301. {
  302. return fsl_esdhc_mmc_init(bis);
  303. }
  304. #endif
  305. int get_clocks(void)
  306. {
  307. #ifdef CONFIG_FSL_ESDHC_IMX
  308. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  309. #endif
  310. return 0;
  311. }
  312. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  313. void enable_caches(void)
  314. {
  315. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  316. enum dcache_option option = DCACHE_WRITETHROUGH;
  317. #else
  318. enum dcache_option option = DCACHE_WRITEBACK;
  319. #endif
  320. dcache_enable();
  321. icache_enable();
  322. /* Enable caching on OCRAM */
  323. mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
  324. }
  325. #endif
  326. #ifdef CONFIG_SYS_I2C_MXC
  327. /* i2c_num can be from 0 - 3 */
  328. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  329. {
  330. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  331. switch (i2c_num) {
  332. case 0:
  333. clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
  334. CCM_CCGR4_I2C0_CTRL_MASK);
  335. case 2:
  336. clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
  337. CCM_CCGR10_I2C2_CTRL_MASK);
  338. break;
  339. default:
  340. return -EINVAL;
  341. }
  342. return 0;
  343. }
  344. #endif