fsl_ahci.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NXP PPC SATA platform driver
  4. *
  5. * (C) Copyright 2019 NXP, Inc.
  6. *
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <asm/fsl_serdes.h>
  11. #include <dm/lists.h>
  12. #include <dm.h>
  13. #include <ahci.h>
  14. #include <scsi.h>
  15. #include <libata.h>
  16. #include <sata.h>
  17. #include <malloc.h>
  18. #include <memalign.h>
  19. #include <fis.h>
  20. #include "fsl_sata.h"
  21. struct fsl_ahci_priv {
  22. u32 base;
  23. u32 flag;
  24. u32 number;
  25. fsl_sata_t *fsl_sata;
  26. };
  27. static int fsl_ahci_bind(struct udevice *dev)
  28. {
  29. return device_bind_driver(dev, "fsl_ahci_scsi", "fsl_ahci_scsi", NULL);
  30. }
  31. static int fsl_ahci_ofdata_to_platdata(struct udevice *dev)
  32. {
  33. struct fsl_ahci_priv *priv = dev_get_priv(dev);
  34. priv->number = dev_read_u32_default(dev, "sata-number", -1);
  35. priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
  36. priv->base = dev_read_addr(dev);
  37. if (priv->base == FDT_ADDR_T_NONE)
  38. return -EINVAL;
  39. return 0;
  40. }
  41. static int ata_wait_register(unsigned __iomem *addr, u32 mask,
  42. u32 val, u32 timeout_msec)
  43. {
  44. int i;
  45. for (i = 0; ((in_le32(addr) & mask) != val) && i < timeout_msec; i++)
  46. mdelay(1);
  47. return (i < timeout_msec) ? 0 : -1;
  48. }
  49. static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
  50. {
  51. printf("Status FIS dump:\n\r");
  52. printf("fis_type: %02x\n\r", s->fis_type);
  53. printf("pm_port_i: %02x\n\r", s->pm_port_i);
  54. printf("status: %02x\n\r", s->status);
  55. printf("error: %02x\n\r", s->error);
  56. printf("lba_low: %02x\n\r", s->lba_low);
  57. printf("lba_mid: %02x\n\r", s->lba_mid);
  58. printf("lba_high: %02x\n\r", s->lba_high);
  59. printf("device: %02x\n\r", s->device);
  60. printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
  61. printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
  62. printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
  63. printf("res1: %02x\n\r", s->res1);
  64. printf("sector_count: %02x\n\r", s->sector_count);
  65. printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
  66. }
  67. static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
  68. {
  69. printf("\n\rSATA: %08x\n\r", (u32)reg);
  70. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  71. printf("CAR: %08x\n\r", in_le32(&reg->car));
  72. printf("CCR: %08x\n\r", in_le32(&reg->ccr));
  73. printf("CER: %08x\n\r", in_le32(&reg->cer));
  74. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  75. printf("DER: %08x\n\r", in_le32(&reg->der));
  76. printf("CHBA: %08x\n\r", in_le32(&reg->chba));
  77. printf("HStatus: %08x\n\r", in_le32(&reg->hstatus));
  78. printf("HControl: %08x\n\r", in_le32(&reg->hcontrol));
  79. printf("CQPMP: %08x\n\r", in_le32(&reg->cqpmp));
  80. printf("SIG: %08x\n\r", in_le32(&reg->sig));
  81. printf("ICC: %08x\n\r", in_le32(&reg->icc));
  82. printf("SStatus: %08x\n\r", in_le32(&reg->sstatus));
  83. printf("SError: %08x\n\r", in_le32(&reg->serror));
  84. printf("SControl: %08x\n\r", in_le32(&reg->scontrol));
  85. printf("SNotification: %08x\n\r", in_le32(&reg->snotification));
  86. printf("TransCfg: %08x\n\r", in_le32(&reg->transcfg));
  87. printf("TransStatus: %08x\n\r", in_le32(&reg->transstatus));
  88. printf("LinkCfg: %08x\n\r", in_le32(&reg->linkcfg));
  89. printf("LinkCfg1: %08x\n\r", in_le32(&reg->linkcfg1));
  90. printf("LinkCfg2: %08x\n\r", in_le32(&reg->linkcfg2));
  91. printf("LinkStatus: %08x\n\r", in_le32(&reg->linkstatus));
  92. printf("LinkStatus1: %08x\n\r", in_le32(&reg->linkstatus1));
  93. printf("PhyCtrlCfg: %08x\n\r", in_le32(&reg->phyctrlcfg));
  94. printf("SYSPR: %08x\n\r", in_be32(&reg->syspr));
  95. }
  96. static int init_sata(struct fsl_ahci_priv *priv)
  97. {
  98. int i;
  99. u32 cda;
  100. u32 val32;
  101. u32 sig;
  102. fsl_sata_t *sata;
  103. u32 length, align;
  104. cmd_hdr_tbl_t *cmd_hdr;
  105. fsl_sata_reg_t __iomem *reg;
  106. int dev = priv->number;
  107. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  108. printf("the sata index %d is out of ranges\n\r", dev);
  109. return -EINVAL;
  110. }
  111. #ifdef CONFIG_MPC85xx
  112. if (dev == 0 && (!is_serdes_configured(SATA1))) {
  113. printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
  114. return -EINVAL;
  115. }
  116. if (dev == 1 && (!is_serdes_configured(SATA2))) {
  117. printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
  118. return -EINVAL;
  119. }
  120. #endif
  121. /* Allocate SATA device driver struct */
  122. sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
  123. if (!sata) {
  124. printf("alloc the sata device struct failed\n\r");
  125. return -ENOMEM;
  126. }
  127. /* Zero all of the device driver struct */
  128. memset((void *)sata, 0, sizeof(fsl_sata_t));
  129. sata->dma_flag = priv->flag;
  130. snprintf(sata->name, 12, "SATA%d", dev);
  131. /* Set the controller register base address to device struct */
  132. reg = (fsl_sata_reg_t *)priv->base;
  133. sata->reg_base = reg;
  134. /* Allocate the command header table, 4 bytes aligned */
  135. length = sizeof(struct cmd_hdr_tbl);
  136. align = SATA_HC_CMD_HDR_TBL_ALIGN;
  137. sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
  138. if (!sata->cmd_hdr_tbl_offset) {
  139. printf("alloc the command header failed\n\r");
  140. return -ENOMEM;
  141. }
  142. cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
  143. & ~(align - 1));
  144. sata->cmd_hdr = cmd_hdr;
  145. /* Zero all of the command header table */
  146. memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
  147. /* Allocate command descriptor for all command */
  148. length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
  149. align = SATA_HC_CMD_DESC_ALIGN;
  150. sata->cmd_desc_offset = (void *)malloc(length + align);
  151. if (!sata->cmd_desc_offset) {
  152. printf("alloc the command descriptor failed\n\r");
  153. return -ENOMEM;
  154. }
  155. sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
  156. & ~(align - 1));
  157. /* Zero all of command descriptor */
  158. memset((void *)sata->cmd_desc_offset, 0, length + align);
  159. /* Link the command descriptor to command header */
  160. for (i = 0; i < SATA_HC_MAX_CMD; i++) {
  161. cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
  162. & ~(CMD_HDR_CDA_ALIGN - 1);
  163. cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
  164. }
  165. /* To have safe state, force the controller offline */
  166. val32 = in_le32(&reg->hcontrol);
  167. val32 &= ~HCONTROL_ONOFF;
  168. val32 |= HCONTROL_FORCE_OFFLINE;
  169. out_le32(&reg->hcontrol, val32);
  170. /* Wait the controller offline */
  171. ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
  172. /* Set the command header base address to CHBA register to tell DMA */
  173. out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
  174. /* Snoop for the command header */
  175. val32 = in_le32(&reg->hcontrol);
  176. val32 |= HCONTROL_HDR_SNOOP;
  177. out_le32(&reg->hcontrol, val32);
  178. /* Disable all of interrupts */
  179. val32 = in_le32(&reg->hcontrol);
  180. val32 &= ~HCONTROL_INT_EN_ALL;
  181. out_le32(&reg->hcontrol, val32);
  182. /* Clear all of interrupts */
  183. val32 = in_le32(&reg->hstatus);
  184. out_le32(&reg->hstatus, val32);
  185. /* Set the ICC, no interrupt coalescing */
  186. out_le32(&reg->icc, 0x01000000);
  187. /* No PM attatched, the SATA device direct connect */
  188. out_le32(&reg->cqpmp, 0);
  189. /* Clear SError register */
  190. val32 = in_le32(&reg->serror);
  191. out_le32(&reg->serror, val32);
  192. /* Clear CER register */
  193. val32 = in_le32(&reg->cer);
  194. out_le32(&reg->cer, val32);
  195. /* Clear DER register */
  196. val32 = in_le32(&reg->der);
  197. out_le32(&reg->der, val32);
  198. /* No device detection or initialization action requested */
  199. out_le32(&reg->scontrol, 0x00000300);
  200. /* Configure the transport layer, default value */
  201. out_le32(&reg->transcfg, 0x08000016);
  202. /* Configure the link layer, default value */
  203. out_le32(&reg->linkcfg, 0x0000ff34);
  204. /* Bring the controller online */
  205. val32 = in_le32(&reg->hcontrol);
  206. val32 |= HCONTROL_ONOFF;
  207. out_le32(&reg->hcontrol, val32);
  208. mdelay(100);
  209. /* print sata device name */
  210. printf("%s ", sata->name);
  211. /* Wait PHY RDY signal changed for 500ms */
  212. ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
  213. HSTATUS_PHY_RDY, 500);
  214. /* Check PHYRDY */
  215. val32 = in_le32(&reg->hstatus);
  216. if (val32 & HSTATUS_PHY_RDY) {
  217. sata->link = 1;
  218. } else {
  219. sata->link = 0;
  220. printf("(No RDY)\n\r");
  221. return -EINVAL;
  222. }
  223. /* Wait for signature updated, which is 1st D2H */
  224. ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
  225. HSTATUS_SIGNATURE, 10000);
  226. if (val32 & HSTATUS_SIGNATURE) {
  227. sig = in_le32(&reg->sig);
  228. debug("Signature updated, the sig =%08x\n\r", sig);
  229. sata->ata_device_type = ata_dev_classify(sig);
  230. }
  231. /* Check the speed */
  232. val32 = in_le32(&reg->sstatus);
  233. if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
  234. printf("(1.5 Gbps)\n\r");
  235. else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
  236. printf("(3 Gbps)\n\r");
  237. priv->fsl_sata = sata;
  238. return 0;
  239. }
  240. static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata,
  241. struct sata_fis_h2d *cfis,
  242. int is_ncq, int tag,
  243. u8 *buffer, u32 len)
  244. {
  245. cmd_hdr_entry_t *cmd_hdr;
  246. cmd_desc_t *cmd_desc;
  247. sata_fis_h2d_t *h2d;
  248. prd_entry_t *prde;
  249. u32 ext_c_ddc;
  250. u32 prde_count;
  251. u32 val32;
  252. u32 ttl;
  253. u32 der;
  254. int i;
  255. fsl_sata_reg_t *reg = sata->reg_base;
  256. /* Check xfer length */
  257. if (len > SATA_HC_MAX_XFER_LEN) {
  258. printf("max transfer length is 64MB\n\r");
  259. return 0;
  260. }
  261. /* Setup the command descriptor */
  262. cmd_desc = sata->cmd_desc + tag;
  263. /* Get the pointer cfis of command descriptor */
  264. h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
  265. /* Zero the cfis of command descriptor */
  266. memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
  267. /* Copy the cfis from user to command descriptor */
  268. h2d->fis_type = cfis->fis_type;
  269. h2d->pm_port_c = cfis->pm_port_c;
  270. h2d->command = cfis->command;
  271. h2d->features = cfis->features;
  272. h2d->features_exp = cfis->features_exp;
  273. h2d->lba_low = cfis->lba_low;
  274. h2d->lba_mid = cfis->lba_mid;
  275. h2d->lba_high = cfis->lba_high;
  276. h2d->lba_low_exp = cfis->lba_low_exp;
  277. h2d->lba_mid_exp = cfis->lba_mid_exp;
  278. h2d->lba_high_exp = cfis->lba_high_exp;
  279. if (!is_ncq) {
  280. h2d->sector_count = cfis->sector_count;
  281. h2d->sector_count_exp = cfis->sector_count_exp;
  282. } else { /* NCQ */
  283. h2d->sector_count = (u8)(tag << 3);
  284. }
  285. h2d->device = cfis->device;
  286. h2d->control = cfis->control;
  287. /* Setup the PRD table */
  288. prde = (prd_entry_t *)cmd_desc->prdt;
  289. memset((void *)prde, 0, sizeof(struct prdt));
  290. prde_count = 0;
  291. ttl = len;
  292. for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
  293. if (!len)
  294. break;
  295. prde->dba = cpu_to_le32((u32)buffer & ~0x3);
  296. debug("dba = %08x\n\r", (u32)buffer);
  297. if (len < PRD_ENTRY_MAX_XFER_SZ) {
  298. ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
  299. debug("ext_c_ddc1 = %08x, len = %08x\n\r",
  300. ext_c_ddc, len);
  301. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  302. prde_count++;
  303. prde++;
  304. } else {
  305. ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
  306. debug("ext_c_ddc2 = %08x, len = %08x\n\r",
  307. ext_c_ddc, len);
  308. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  309. buffer += PRD_ENTRY_MAX_XFER_SZ;
  310. len -= PRD_ENTRY_MAX_XFER_SZ;
  311. prde_count++;
  312. prde++;
  313. }
  314. }
  315. /* Setup the command slot of cmd hdr */
  316. cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
  317. cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
  318. val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
  319. val32 |= sizeof(sata_fis_h2d_t);
  320. cmd_hdr->prde_fis_len = cpu_to_le32(val32);
  321. cmd_hdr->ttl = cpu_to_le32(ttl);
  322. if (!is_ncq)
  323. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
  324. else
  325. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP |
  326. CMD_HDR_ATTR_FPDMA;
  327. tag &= CMD_HDR_ATTR_TAG;
  328. val32 |= tag;
  329. debug("attribute = %08x\n\r", val32);
  330. cmd_hdr->attribute = cpu_to_le32(val32);
  331. /* Make sure cmd desc and cmd slot valid before command issue */
  332. sync();
  333. /* PMP*/
  334. val32 = (u32)(h2d->pm_port_c & 0x0f);
  335. out_le32(&reg->cqpmp, val32);
  336. /* Wait no active */
  337. if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
  338. printf("Wait no active time out\n\r");
  339. /* Issue command */
  340. if (!(in_le32(&reg->cqr) & (1 << tag))) {
  341. val32 = 1 << tag;
  342. out_le32(&reg->cqr, val32);
  343. }
  344. /* Wait command completed for 10s */
  345. if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
  346. if (!is_ncq)
  347. printf("Non-NCQ command time out\n\r");
  348. else
  349. printf("NCQ command time out\n\r");
  350. }
  351. val32 = in_le32(&reg->cer);
  352. if (val32) {
  353. fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
  354. printf("CE at device\n\r");
  355. fsl_sata_dump_regs(reg);
  356. der = in_le32(&reg->der);
  357. out_le32(&reg->cer, val32);
  358. out_le32(&reg->der, der);
  359. }
  360. /* Clear complete flags */
  361. val32 = in_le32(&reg->ccr);
  362. out_le32(&reg->ccr, val32);
  363. return len;
  364. }
  365. static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  366. enum cmd_type command_type, int tag, u8 *buffer,
  367. u32 len)
  368. {
  369. int rc;
  370. if (tag > SATA_HC_MAX_CMD || tag < 0) {
  371. printf("tag is out of range, tag=%d\n\r", tag);
  372. return -1;
  373. }
  374. switch (command_type) {
  375. case CMD_ATA:
  376. rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
  377. return rc;
  378. case CMD_NCQ:
  379. rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
  380. return rc;
  381. case CMD_ATAPI:
  382. case CMD_VENDOR_BIST:
  383. case CMD_BIST:
  384. printf("not support now\n\r");
  385. return -1;
  386. default:
  387. break;
  388. }
  389. return -1;
  390. }
  391. static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
  392. {
  393. struct sata_fis_h2d h2d, *cfis = &h2d;
  394. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  395. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  396. cfis->pm_port_c = 0x80; /* is command */
  397. cfis->command = ATA_CMD_ID_ATA;
  398. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
  399. ata_swap_buf_le16(id, ATA_ID_WORDS);
  400. }
  401. static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
  402. {
  403. sata->pio = id[ATA_ID_PIO_MODES];
  404. sata->mwdma = id[ATA_ID_MWDMA_MODES];
  405. sata->udma = id[ATA_ID_UDMA_MODES];
  406. debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio,
  407. sata->mwdma, sata->udma);
  408. }
  409. static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
  410. {
  411. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  412. sata->wcache = 1;
  413. if (ata_id_has_flush(id))
  414. sata->flush = 1;
  415. if (ata_id_has_flush_ext(id))
  416. sata->flush_ext = 1;
  417. }
  418. static void fsl_sata_set_features(fsl_sata_t *sata)
  419. {
  420. struct sata_fis_h2d h2d, *cfis = &h2d;
  421. u8 udma_cap;
  422. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  423. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  424. cfis->pm_port_c = 0x80; /* is command */
  425. cfis->command = ATA_CMD_SET_FEATURES;
  426. cfis->features = SETFEATURES_XFER;
  427. /* First check the device capablity */
  428. udma_cap = (u8)(sata->udma & 0xff);
  429. debug("udma_cap %02x\n\r", udma_cap);
  430. if (udma_cap == ATA_UDMA6)
  431. cfis->sector_count = XFER_UDMA_6;
  432. if (udma_cap == ATA_UDMA5)
  433. cfis->sector_count = XFER_UDMA_5;
  434. if (udma_cap == ATA_UDMA4)
  435. cfis->sector_count = XFER_UDMA_4;
  436. if (udma_cap == ATA_UDMA3)
  437. cfis->sector_count = XFER_UDMA_3;
  438. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  439. }
  440. static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
  441. u8 *buffer, int is_write)
  442. {
  443. struct sata_fis_h2d h2d, *cfis = &h2d;
  444. u32 block;
  445. block = start;
  446. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  447. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  448. cfis->pm_port_c = 0x80; /* is command */
  449. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  450. cfis->device = ATA_LBA;
  451. cfis->device |= (block >> 24) & 0xf;
  452. cfis->lba_high = (block >> 16) & 0xff;
  453. cfis->lba_mid = (block >> 8) & 0xff;
  454. cfis->lba_low = block & 0xff;
  455. cfis->sector_count = (u8)(blkcnt & 0xff);
  456. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
  457. ATA_SECT_SIZE * blkcnt);
  458. return blkcnt;
  459. }
  460. static void fsl_sata_flush_cache(fsl_sata_t *sata)
  461. {
  462. struct sata_fis_h2d h2d, *cfis = &h2d;
  463. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  464. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  465. cfis->pm_port_c = 0x80; /* is command */
  466. cfis->command = ATA_CMD_FLUSH;
  467. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  468. }
  469. static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start,
  470. u32 blkcnt, u8 *buffer, int is_write)
  471. {
  472. struct sata_fis_h2d h2d, *cfis = &h2d;
  473. u64 block;
  474. block = (u64)start;
  475. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  476. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  477. cfis->pm_port_c = 0x80; /* is command */
  478. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  479. : ATA_CMD_READ_EXT;
  480. cfis->lba_high_exp = (block >> 40) & 0xff;
  481. cfis->lba_mid_exp = (block >> 32) & 0xff;
  482. cfis->lba_low_exp = (block >> 24) & 0xff;
  483. cfis->lba_high = (block >> 16) & 0xff;
  484. cfis->lba_mid = (block >> 8) & 0xff;
  485. cfis->lba_low = block & 0xff;
  486. cfis->device = ATA_LBA;
  487. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  488. cfis->sector_count = blkcnt & 0xff;
  489. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
  490. ATA_SECT_SIZE * blkcnt);
  491. return blkcnt;
  492. }
  493. static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
  494. u8 *buffer,
  495. int is_write)
  496. {
  497. struct sata_fis_h2d h2d, *cfis = &h2d;
  498. int ncq_channel;
  499. u64 block;
  500. if (sata->lba48 != 1) {
  501. printf("execute FPDMA command on non-LBA48 hard disk\n\r");
  502. return -1;
  503. }
  504. block = (u64)start;
  505. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  506. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  507. cfis->pm_port_c = 0x80; /* is command */
  508. cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
  509. : ATA_CMD_FPDMA_READ;
  510. cfis->lba_high_exp = (block >> 40) & 0xff;
  511. cfis->lba_mid_exp = (block >> 32) & 0xff;
  512. cfis->lba_low_exp = (block >> 24) & 0xff;
  513. cfis->lba_high = (block >> 16) & 0xff;
  514. cfis->lba_mid = (block >> 8) & 0xff;
  515. cfis->lba_low = block & 0xff;
  516. cfis->device = ATA_LBA;
  517. cfis->features_exp = (blkcnt >> 8) & 0xff;
  518. cfis->features = blkcnt & 0xff;
  519. if (sata->queue_depth >= SATA_HC_MAX_CMD)
  520. ncq_channel = SATA_HC_MAX_CMD - 1;
  521. else
  522. ncq_channel = sata->queue_depth - 1;
  523. /* Use the latest queue */
  524. fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer,
  525. ATA_SECT_SIZE * blkcnt);
  526. return blkcnt;
  527. }
  528. static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
  529. {
  530. struct sata_fis_h2d h2d, *cfis = &h2d;
  531. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  532. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  533. cfis->pm_port_c = 0x80; /* is command */
  534. cfis->command = ATA_CMD_FLUSH_EXT;
  535. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  536. }
  537. static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
  538. const void *buffer, int is_write)
  539. {
  540. u32 start, blks;
  541. u8 *addr;
  542. int max_blks;
  543. start = blknr;
  544. blks = blkcnt;
  545. addr = (u8 *)buffer;
  546. max_blks = ATA_MAX_SECTORS_LBA48;
  547. do {
  548. if (blks > max_blks) {
  549. if (sata->dma_flag != FLAGS_FPDMA)
  550. fsl_sata_rw_cmd_ext(sata, start, max_blks,
  551. addr, is_write);
  552. else
  553. fsl_sata_rw_ncq_cmd(sata, start, max_blks,
  554. addr, is_write);
  555. start += max_blks;
  556. blks -= max_blks;
  557. addr += ATA_SECT_SIZE * max_blks;
  558. } else {
  559. if (sata->dma_flag != FLAGS_FPDMA)
  560. fsl_sata_rw_cmd_ext(sata, start, blks,
  561. addr, is_write);
  562. else
  563. fsl_sata_rw_ncq_cmd(sata, start, blks,
  564. addr, is_write);
  565. start += blks;
  566. blks = 0;
  567. addr += ATA_SECT_SIZE * blks;
  568. }
  569. } while (blks != 0);
  570. return blks;
  571. }
  572. static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
  573. const void *buffer, int is_write)
  574. {
  575. u32 start, blks;
  576. u8 *addr;
  577. int max_blks;
  578. start = blknr;
  579. blks = blkcnt;
  580. addr = (u8 *)buffer;
  581. max_blks = ATA_MAX_SECTORS;
  582. do {
  583. if (blks > max_blks) {
  584. fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
  585. start += max_blks;
  586. blks -= max_blks;
  587. addr += ATA_SECT_SIZE * max_blks;
  588. } else {
  589. fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
  590. start += blks;
  591. blks = 0;
  592. addr += ATA_SECT_SIZE * blks;
  593. }
  594. } while (blks != 0);
  595. return blks;
  596. }
  597. /*
  598. * SATA interface between low level driver and command layer
  599. */
  600. static int sata_read(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
  601. void *buffer)
  602. {
  603. u32 rc;
  604. if (sata->lba48)
  605. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  606. READ_CMD);
  607. else
  608. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  609. READ_CMD);
  610. return rc;
  611. }
  612. static int sata_write(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
  613. const void *buffer)
  614. {
  615. u32 rc;
  616. if (sata->lba48) {
  617. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  618. WRITE_CMD);
  619. if (sata->wcache && sata->flush_ext)
  620. fsl_sata_flush_cache_ext(sata);
  621. } else {
  622. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  623. WRITE_CMD);
  624. if (sata->wcache && sata->flush)
  625. fsl_sata_flush_cache(sata);
  626. }
  627. return rc;
  628. }
  629. int sata_getinfo(fsl_sata_t *sata, u16 *id)
  630. {
  631. /* if no detected link */
  632. if (!sata->link)
  633. return -EINVAL;
  634. #ifdef CONFIG_LBA48
  635. /* Check if support LBA48 */
  636. if (ata_id_has_lba48(id)) {
  637. sata->lba48 = 1;
  638. debug("Device support LBA48\n\r");
  639. } else {
  640. debug("Device supports LBA28\n\r");
  641. }
  642. #endif
  643. /* Get the NCQ queue depth from device */
  644. sata->queue_depth = ata_id_queue_depth(id);
  645. /* Get the xfer mode from device */
  646. fsl_sata_xfer_mode(sata, id);
  647. /* Get the write cache status from device */
  648. fsl_sata_init_wcache(sata, id);
  649. /* Set the xfer mode to highest speed */
  650. fsl_sata_set_features(sata);
  651. return 0;
  652. }
  653. static int fsl_scsi_exec(fsl_sata_t *sata, struct scsi_cmd *pccb,
  654. bool is_write)
  655. {
  656. int ret;
  657. u32 temp;
  658. u16 blocks = 0;
  659. lbaint_t start = 0;
  660. u8 *buffer = pccb->pdata;
  661. /* Retrieve the base LBA number from the ccb structure. */
  662. if (pccb->cmd[0] == SCSI_READ16) {
  663. memcpy(&start, pccb->cmd + 2, 8);
  664. start = be64_to_cpu(start);
  665. } else {
  666. memcpy(&temp, pccb->cmd + 2, 4);
  667. start = be32_to_cpu(temp);
  668. }
  669. if (pccb->cmd[0] == SCSI_READ16)
  670. blocks = (((u16)pccb->cmd[13]) << 8) | ((u16)pccb->cmd[14]);
  671. else
  672. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16)pccb->cmd[8]);
  673. debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
  674. is_write ? "write" : "read", blocks, start);
  675. if (is_write)
  676. ret = sata_write(sata, start, blocks, buffer);
  677. else
  678. ret = sata_read(sata, start, blocks, buffer);
  679. return ret;
  680. }
  681. static char *fsl_ata_id_strcpy(u16 *target, u16 *src, int len)
  682. {
  683. int i;
  684. for (i = 0; i < len / 2; i++)
  685. target[i] = src[i];
  686. return (char *)target;
  687. }
  688. static int fsl_ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
  689. struct scsi_cmd *pccb,
  690. fsl_sata_t *sata)
  691. {
  692. u8 port;
  693. u16 *idbuf;
  694. ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
  695. /* Clean ccb data buffer */
  696. memset(pccb->pdata, 0, pccb->datalen);
  697. if (pccb->datalen <= 35)
  698. return 0;
  699. /* Read id from sata */
  700. port = pccb->target;
  701. fsl_sata_identify(sata, (u16 *)tmpid);
  702. if (!uc_priv->ataid[port]) {
  703. uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
  704. if (!uc_priv->ataid[port]) {
  705. printf("%s: No memory for ataid[port]\n", __func__);
  706. return -ENOMEM;
  707. }
  708. }
  709. idbuf = uc_priv->ataid[port];
  710. memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
  711. memcpy(&pccb->pdata[8], "ATA ", 8);
  712. fsl_ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
  713. fsl_ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
  714. sata_getinfo(sata, (u16 *)idbuf);
  715. #ifdef DEBUG
  716. ata_dump_id(idbuf);
  717. #endif
  718. return 0;
  719. }
  720. /*
  721. * SCSI READ CAPACITY10 command operation.
  722. */
  723. static int fsl_ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
  724. struct scsi_cmd *pccb)
  725. {
  726. u32 cap;
  727. u64 cap64;
  728. u32 block_size;
  729. if (!uc_priv->ataid[pccb->target]) {
  730. printf("scsi_ahci: SCSI READ CAPACITY10 command failure.");
  731. printf("\tNo ATA info!\n");
  732. printf("\tPlease run SCSI command INQUIRY first!\n");
  733. return -EPERM;
  734. }
  735. cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  736. if (cap64 > 0x100000000ULL)
  737. cap64 = 0xffffffff;
  738. cap = cpu_to_be32(cap64);
  739. memcpy(pccb->pdata, &cap, sizeof(cap));
  740. block_size = cpu_to_be32((u32)512);
  741. memcpy(&pccb->pdata[4], &block_size, 4);
  742. return 0;
  743. }
  744. /*
  745. * SCSI READ CAPACITY16 command operation.
  746. */
  747. static int fsl_ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
  748. struct scsi_cmd *pccb)
  749. {
  750. u64 cap;
  751. u64 block_size;
  752. if (!uc_priv->ataid[pccb->target]) {
  753. printf("scsi_ahci: SCSI READ CAPACITY16 command failure.");
  754. printf("\tNo ATA info!\n");
  755. printf("\tPlease run SCSI command INQUIRY first!\n");
  756. return -EPERM;
  757. }
  758. cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  759. cap = cpu_to_be64(cap);
  760. memcpy(pccb->pdata, &cap, sizeof(cap));
  761. block_size = cpu_to_be64((u64)512);
  762. memcpy(&pccb->pdata[8], &block_size, 8);
  763. return 0;
  764. }
  765. /*
  766. * SCSI TEST UNIT READY command operation.
  767. */
  768. static int fsl_ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
  769. struct scsi_cmd *pccb)
  770. {
  771. return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
  772. }
  773. static int fsl_ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  774. {
  775. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
  776. struct fsl_ahci_priv *priv = dev_get_priv(dev->parent);
  777. fsl_sata_t *sata = priv->fsl_sata;
  778. int ret;
  779. switch (pccb->cmd[0]) {
  780. case SCSI_READ16:
  781. case SCSI_READ10:
  782. ret = fsl_scsi_exec(sata, pccb, 0);
  783. break;
  784. case SCSI_WRITE10:
  785. ret = fsl_scsi_exec(sata, pccb, 1);
  786. break;
  787. case SCSI_RD_CAPAC10:
  788. ret = fsl_ata_scsiop_read_capacity10(uc_priv, pccb);
  789. break;
  790. case SCSI_RD_CAPAC16:
  791. ret = fsl_ata_scsiop_read_capacity16(uc_priv, pccb);
  792. break;
  793. case SCSI_TST_U_RDY:
  794. ret = fsl_ata_scsiop_test_unit_ready(uc_priv, pccb);
  795. break;
  796. case SCSI_INQUIRY:
  797. ret = fsl_ata_scsiop_inquiry(uc_priv, pccb, sata);
  798. break;
  799. default:
  800. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  801. return -ENOTSUPP;
  802. }
  803. if (ret) {
  804. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  805. return ret;
  806. }
  807. return 0;
  808. }
  809. static int fsl_ahci_probe(struct udevice *dev)
  810. {
  811. struct fsl_ahci_priv *priv = dev_get_priv(dev);
  812. struct udevice *child_dev;
  813. struct scsi_platdata *uc_plat;
  814. device_find_first_child(dev, &child_dev);
  815. if (!child_dev)
  816. return -ENODEV;
  817. uc_plat = dev_get_uclass_platdata(child_dev);
  818. uc_plat->base = priv->base;
  819. uc_plat->max_lun = 1;
  820. uc_plat->max_id = 1;
  821. return init_sata(priv);
  822. }
  823. struct scsi_ops fsl_scsi_ops = {
  824. .exec = fsl_ahci_scsi_exec,
  825. };
  826. static const struct udevice_id fsl_ahci_ids[] = {
  827. { .compatible = "fsl,pq-sata-v2" },
  828. { }
  829. };
  830. U_BOOT_DRIVER(fsl_ahci_scsi) = {
  831. .name = "fsl_ahci_scsi",
  832. .id = UCLASS_SCSI,
  833. .ops = &fsl_scsi_ops,
  834. };
  835. U_BOOT_DRIVER(fsl_ahci) = {
  836. .name = "fsl_ahci",
  837. .id = UCLASS_AHCI,
  838. .of_match = fsl_ahci_ids,
  839. .bind = fsl_ahci_bind,
  840. .ofdata_to_platdata = fsl_ahci_ofdata_to_platdata,
  841. .probe = fsl_ahci_probe,
  842. .priv_auto_alloc_size = sizeof(struct fsl_ahci_priv),
  843. };