ls1046aqds.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2019-2020 NXP
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fdt_support.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <init.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include <asm/arch/ppa.h>
  15. #include <asm/arch/fdt.h>
  16. #include <asm/arch/mmu.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/soc.h>
  19. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  20. #include <ahci.h>
  21. #include <hwconfig.h>
  22. #include <mmc.h>
  23. #include <scsi.h>
  24. #include <fm_eth.h>
  25. #include <fsl_csu.h>
  26. #include <fsl_esdhc.h>
  27. #include <fsl_ifc.h>
  28. #include <fsl_sec.h>
  29. #include <spl.h>
  30. #include "../common/vid.h"
  31. #include "../common/qixis.h"
  32. #include "ls1046aqds_qixis.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  35. void i2c_early_init_f(void);
  36. #endif
  37. #ifdef CONFIG_TFABOOT
  38. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  39. {
  40. "nor0",
  41. CONFIG_SYS_NOR0_CSPR,
  42. CONFIG_SYS_NOR0_CSPR_EXT,
  43. CONFIG_SYS_NOR_AMASK,
  44. CONFIG_SYS_NOR_CSOR,
  45. {
  46. CONFIG_SYS_NOR_FTIM0,
  47. CONFIG_SYS_NOR_FTIM1,
  48. CONFIG_SYS_NOR_FTIM2,
  49. CONFIG_SYS_NOR_FTIM3
  50. },
  51. },
  52. {
  53. "nor1",
  54. CONFIG_SYS_NOR1_CSPR,
  55. CONFIG_SYS_NOR1_CSPR_EXT,
  56. CONFIG_SYS_NOR_AMASK,
  57. CONFIG_SYS_NOR_CSOR,
  58. {
  59. CONFIG_SYS_NOR_FTIM0,
  60. CONFIG_SYS_NOR_FTIM1,
  61. CONFIG_SYS_NOR_FTIM2,
  62. CONFIG_SYS_NOR_FTIM3
  63. },
  64. },
  65. {
  66. "nand",
  67. CONFIG_SYS_NAND_CSPR,
  68. CONFIG_SYS_NAND_CSPR_EXT,
  69. CONFIG_SYS_NAND_AMASK,
  70. CONFIG_SYS_NAND_CSOR,
  71. {
  72. CONFIG_SYS_NAND_FTIM0,
  73. CONFIG_SYS_NAND_FTIM1,
  74. CONFIG_SYS_NAND_FTIM2,
  75. CONFIG_SYS_NAND_FTIM3
  76. },
  77. },
  78. {
  79. "fpga",
  80. CONFIG_SYS_FPGA_CSPR,
  81. CONFIG_SYS_FPGA_CSPR_EXT,
  82. CONFIG_SYS_FPGA_AMASK,
  83. CONFIG_SYS_FPGA_CSOR,
  84. {
  85. CONFIG_SYS_FPGA_FTIM0,
  86. CONFIG_SYS_FPGA_FTIM1,
  87. CONFIG_SYS_FPGA_FTIM2,
  88. CONFIG_SYS_FPGA_FTIM3
  89. },
  90. }
  91. };
  92. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  93. {
  94. "nand",
  95. CONFIG_SYS_NAND_CSPR,
  96. CONFIG_SYS_NAND_CSPR_EXT,
  97. CONFIG_SYS_NAND_AMASK,
  98. CONFIG_SYS_NAND_CSOR,
  99. {
  100. CONFIG_SYS_NAND_FTIM0,
  101. CONFIG_SYS_NAND_FTIM1,
  102. CONFIG_SYS_NAND_FTIM2,
  103. CONFIG_SYS_NAND_FTIM3
  104. },
  105. },
  106. {
  107. "nor0",
  108. CONFIG_SYS_NOR0_CSPR,
  109. CONFIG_SYS_NOR0_CSPR_EXT,
  110. CONFIG_SYS_NOR_AMASK,
  111. CONFIG_SYS_NOR_CSOR,
  112. {
  113. CONFIG_SYS_NOR_FTIM0,
  114. CONFIG_SYS_NOR_FTIM1,
  115. CONFIG_SYS_NOR_FTIM2,
  116. CONFIG_SYS_NOR_FTIM3
  117. },
  118. },
  119. {
  120. "nor1",
  121. CONFIG_SYS_NOR1_CSPR,
  122. CONFIG_SYS_NOR1_CSPR_EXT,
  123. CONFIG_SYS_NOR_AMASK,
  124. CONFIG_SYS_NOR_CSOR,
  125. {
  126. CONFIG_SYS_NOR_FTIM0,
  127. CONFIG_SYS_NOR_FTIM1,
  128. CONFIG_SYS_NOR_FTIM2,
  129. CONFIG_SYS_NOR_FTIM3
  130. },
  131. },
  132. {
  133. "fpga",
  134. CONFIG_SYS_FPGA_CSPR,
  135. CONFIG_SYS_FPGA_CSPR_EXT,
  136. CONFIG_SYS_FPGA_AMASK,
  137. CONFIG_SYS_FPGA_CSOR,
  138. {
  139. CONFIG_SYS_FPGA_FTIM0,
  140. CONFIG_SYS_FPGA_FTIM1,
  141. CONFIG_SYS_FPGA_FTIM2,
  142. CONFIG_SYS_FPGA_FTIM3
  143. },
  144. }
  145. };
  146. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  147. {
  148. enum boot_src src = get_boot_src();
  149. if (src == BOOT_SOURCE_IFC_NAND)
  150. regs_info->regs = ifc_cfg_nand_boot;
  151. else
  152. regs_info->regs = ifc_cfg_nor_boot;
  153. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  154. }
  155. #endif
  156. enum {
  157. MUX_TYPE_GPIO,
  158. };
  159. int checkboard(void)
  160. {
  161. #ifdef CONFIG_TFABOOT
  162. enum boot_src src = get_boot_src();
  163. #endif
  164. char buf[64];
  165. #ifndef CONFIG_SD_BOOT
  166. u8 sw;
  167. #endif
  168. puts("Board: LS1046AQDS, boot from ");
  169. #ifdef CONFIG_TFABOOT
  170. if (src == BOOT_SOURCE_SD_MMC)
  171. puts("SD\n");
  172. else {
  173. #endif
  174. #ifdef CONFIG_SD_BOOT
  175. puts("SD\n");
  176. #else
  177. sw = QIXIS_READ(brdcfg[0]);
  178. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  179. if (sw < 0x8)
  180. printf("vBank: %d\n", sw);
  181. else if (sw == 0x8)
  182. puts("PromJet\n");
  183. else if (sw == 0x9)
  184. puts("NAND\n");
  185. else if (sw == 0xF)
  186. printf("QSPI\n");
  187. else
  188. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  189. #endif
  190. #ifdef CONFIG_TFABOOT
  191. }
  192. #endif
  193. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  194. QIXIS_READ(id), QIXIS_READ(arch));
  195. printf("FPGA: v%d (%s), build %d\n",
  196. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  197. (int)qixis_read_minor());
  198. return 0;
  199. }
  200. bool if_board_diff_clk(void)
  201. {
  202. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  203. return diff_conf & 0x40;
  204. }
  205. unsigned long get_board_sys_clk(void)
  206. {
  207. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  208. switch (sysclk_conf & 0x0f) {
  209. case QIXIS_SYSCLK_64:
  210. return 64000000;
  211. case QIXIS_SYSCLK_83:
  212. return 83333333;
  213. case QIXIS_SYSCLK_100:
  214. return 100000000;
  215. case QIXIS_SYSCLK_125:
  216. return 125000000;
  217. case QIXIS_SYSCLK_133:
  218. return 133333333;
  219. case QIXIS_SYSCLK_150:
  220. return 150000000;
  221. case QIXIS_SYSCLK_160:
  222. return 160000000;
  223. case QIXIS_SYSCLK_166:
  224. return 166666666;
  225. }
  226. return 66666666;
  227. }
  228. unsigned long get_board_ddr_clk(void)
  229. {
  230. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  231. if (if_board_diff_clk())
  232. return get_board_sys_clk();
  233. switch ((ddrclk_conf & 0x30) >> 4) {
  234. case QIXIS_DDRCLK_100:
  235. return 100000000;
  236. case QIXIS_DDRCLK_125:
  237. return 125000000;
  238. case QIXIS_DDRCLK_133:
  239. return 133333333;
  240. }
  241. return 66666666;
  242. }
  243. #ifdef CONFIG_LPUART
  244. u32 get_lpuart_clk(void)
  245. {
  246. return gd->bus_clk;
  247. }
  248. #endif
  249. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  250. {
  251. int ret;
  252. #ifdef CONFIG_DM_I2C
  253. struct udevice *dev;
  254. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  255. 1, &dev);
  256. if (ret) {
  257. printf("%s: Cannot find udev for a bus %d\n", __func__,
  258. bus_num);
  259. return ret;
  260. }
  261. ret = dm_i2c_write(dev, 0, &ch, 1);
  262. #else
  263. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  264. #endif
  265. if (ret) {
  266. puts("PCA: failed to select proper channel\n");
  267. return ret;
  268. }
  269. return 0;
  270. }
  271. int dram_init(void)
  272. {
  273. /*
  274. * When resuming from deep sleep, the I2C channel may not be
  275. * in the default channel. So, switch to the default channel
  276. * before accessing DDR SPD.
  277. *
  278. * PCA9547 mount on I2C1 bus
  279. */
  280. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  281. fsl_initdram();
  282. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  283. defined(CONFIG_SPL_BUILD)
  284. /* This will break-before-make MMU for DDR */
  285. update_early_mmu_table();
  286. #endif
  287. return 0;
  288. }
  289. int i2c_multiplexer_select_vid_channel(u8 channel)
  290. {
  291. return select_i2c_ch_pca9547(channel, 0);
  292. }
  293. int board_early_init_f(void)
  294. {
  295. u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
  296. #ifdef CONFIG_HAS_FSL_XHCI_USB
  297. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  298. u32 usb_pwrfault;
  299. #endif
  300. #ifdef CONFIG_LPUART
  301. u8 uart;
  302. #endif
  303. /*
  304. * Enable secure system counter for timer
  305. */
  306. out_le32(cntcr, 0x1);
  307. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  308. i2c_early_init_f();
  309. #endif
  310. fsl_lsch2_early_init_f();
  311. #ifdef CONFIG_HAS_FSL_XHCI_USB
  312. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  313. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  314. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  315. SCFG_USBPWRFAULT_USB3_SHIFT) |
  316. (SCFG_USBPWRFAULT_DEDICATED <<
  317. SCFG_USBPWRFAULT_USB2_SHIFT) |
  318. (SCFG_USBPWRFAULT_SHARED <<
  319. SCFG_USBPWRFAULT_USB1_SHIFT);
  320. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  321. #endif
  322. #ifdef CONFIG_LPUART
  323. /* We use lpuart0 as system console */
  324. uart = QIXIS_READ(brdcfg[14]);
  325. uart &= ~CFG_UART_MUX_MASK;
  326. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  327. QIXIS_WRITE(brdcfg[14], uart);
  328. #endif
  329. return 0;
  330. }
  331. #ifdef CONFIG_FSL_DEEP_SLEEP
  332. /* determine if it is a warm boot */
  333. bool is_warm_boot(void)
  334. {
  335. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  336. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  337. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  338. return 1;
  339. return 0;
  340. }
  341. #endif
  342. int config_board_mux(int ctrl_type)
  343. {
  344. u8 reg14;
  345. reg14 = QIXIS_READ(brdcfg[14]);
  346. switch (ctrl_type) {
  347. case MUX_TYPE_GPIO:
  348. reg14 = (reg14 & (~0x6)) | 0x2;
  349. break;
  350. default:
  351. puts("Unsupported mux interface type\n");
  352. return -1;
  353. }
  354. QIXIS_WRITE(brdcfg[14], reg14);
  355. return 0;
  356. }
  357. int config_serdes_mux(void)
  358. {
  359. return 0;
  360. }
  361. #ifdef CONFIG_MISC_INIT_R
  362. int misc_init_r(void)
  363. {
  364. if (hwconfig("gpio"))
  365. config_board_mux(MUX_TYPE_GPIO);
  366. return 0;
  367. }
  368. #endif
  369. int board_init(void)
  370. {
  371. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  372. #ifdef CONFIG_SYS_FSL_SERDES
  373. config_serdes_mux();
  374. #endif
  375. if (adjust_vdd(0))
  376. printf("Warning: Adjusting core voltage failed.\n");
  377. #ifdef CONFIG_FSL_LS_PPA
  378. ppa_init();
  379. #endif
  380. #ifdef CONFIG_NXP_ESBC
  381. /*
  382. * In case of Secure Boot, the IBR configures the SMMU
  383. * to allow only Secure transactions.
  384. * SMMU must be reset in bypass mode.
  385. * Set the ClientPD bit and Clear the USFCFG Bit
  386. */
  387. u32 val;
  388. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  389. out_le32(SMMU_SCR0, val);
  390. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  391. out_le32(SMMU_NSCR0, val);
  392. #endif
  393. #ifdef CONFIG_FSL_CAAM
  394. sec_init();
  395. #endif
  396. return 0;
  397. }
  398. #ifdef CONFIG_OF_BOARD_SETUP
  399. int ft_board_setup(void *blob, struct bd_info *bd)
  400. {
  401. u64 base[CONFIG_NR_DRAM_BANKS];
  402. u64 size[CONFIG_NR_DRAM_BANKS];
  403. u8 reg;
  404. /* fixup DT for the two DDR banks */
  405. base[0] = gd->bd->bi_dram[0].start;
  406. size[0] = gd->bd->bi_dram[0].size;
  407. base[1] = gd->bd->bi_dram[1].start;
  408. size[1] = gd->bd->bi_dram[1].size;
  409. fdt_fixup_memory_banks(blob, base, size, 2);
  410. ft_cpu_setup(blob, bd);
  411. #ifdef CONFIG_SYS_DPAA_FMAN
  412. #ifndef CONFIG_DM_ETH
  413. fdt_fixup_fman_ethernet(blob);
  414. #endif
  415. fdt_fixup_board_enet(blob);
  416. #endif
  417. fdt_fixup_icid(blob);
  418. reg = QIXIS_READ(brdcfg[0]);
  419. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  420. /* Disable IFC if QSPI is enabled */
  421. if (reg == 0xF)
  422. do_fixup_by_compat(blob, "fsl,ifc",
  423. "status", "disabled", 8 + 1, 1);
  424. return 0;
  425. }
  426. #endif
  427. u8 flash_read8(void *addr)
  428. {
  429. return __raw_readb(addr + 1);
  430. }
  431. void flash_write16(u16 val, void *addr)
  432. {
  433. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  434. __raw_writew(shftval, addr);
  435. }
  436. u16 flash_read16(void *addr)
  437. {
  438. u16 val = __raw_readw(addr);
  439. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  440. }
  441. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  442. void *env_sf_get_env_addr(void)
  443. {
  444. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  445. }
  446. #endif