qixis.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011 Freescale Semiconductor
  4. * Copyright 2020 NXP
  5. * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
  6. *
  7. * This file provides support for the QIXIS of some Freescale reference boards.
  8. */
  9. #ifndef __QIXIS_H_
  10. #define __QIXIS_H_
  11. struct qixis {
  12. u8 id; /* ID value uniquely identifying each QDS board type */
  13. u8 arch; /* Board version information */
  14. u8 scver; /* QIXIS Version Register */
  15. u8 model; /* Information of software programming model version */
  16. u8 tagdata;
  17. u8 ctl_sys;
  18. u8 aux; /* Auxiliary Register,0x06 */
  19. u8 clk_spd;
  20. u8 stat_dut;
  21. u8 stat_sys;
  22. u8 stat_alrm;
  23. u8 present;
  24. u8 present2; /* Presence Status Register 2,0x0c */
  25. u8 rcw_ctl;
  26. u8 ctl_led;
  27. u8 i2cblk;
  28. u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
  29. u8 rcfg_st;
  30. u8 dcm_ad;
  31. u8 dcm_da;
  32. u8 dcmd;
  33. u8 dmsg;
  34. u8 gdc;
  35. u8 gdd; /* DCM Debug Data Register,0x17 */
  36. u8 dmack;
  37. u8 res1;
  38. u8 sdhc1;
  39. u8 sdhc2;
  40. u8 stat_pres3;
  41. u8 los_stat;
  42. u8 usb_ctl;
  43. u8 watch; /* Watchdog Register,0x1F */
  44. u8 pwr_ctl[2]; /* Power Control Register,0x20 */
  45. u8 res2[2];
  46. u8 pwr_stat[4]; /* Power Status Register,0x24 */
  47. u8 res3[8];
  48. u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
  49. u8 res4[2];
  50. u8 sclk[3]; /* Clock Configuration Registers,0x34 */
  51. u8 res5;
  52. u8 dclk[3];
  53. u8 res6;
  54. u8 clk_dspd[3];
  55. u8 res7;
  56. u8 rst_ctl; /* Reset Control Register,0x40 */
  57. u8 rst_stat; /* Reset Status Register */
  58. u8 rst_rsn; /* Reset Reason Register */
  59. u8 rst_frc[2]; /* Reset Force Registers,0x43 */
  60. u8 res8[11];
  61. u8 brdcfg[16]; /* Board Configuration Register,0x50 */
  62. u8 dutcfg[16];
  63. u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
  64. u8 rcw_data;
  65. u8 res9[5];
  66. u8 post_ctl;
  67. u8 post_stat;
  68. u8 post_dat[2];
  69. u8 pi_d[4];
  70. u8 gpio_io[4];
  71. u8 gpio_dir[4];
  72. u8 res10[20];
  73. u8 rjtag_ctl;
  74. u8 rjtag_dat;
  75. u8 res11[2];
  76. u8 trig_src[4];
  77. u8 trig_dst[4];
  78. u8 trig_stat;
  79. u8 res12[3];
  80. u8 trig_ctr[4];
  81. u8 res13[16];
  82. u8 clk_freq[6]; /* Clock Measurement Registers */
  83. u8 res_c6[8];
  84. u8 clk_base[2]; /* Clock Frequency Base Reg */
  85. u8 res_d0[8];
  86. u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
  87. u8 res_c0[6];
  88. u8 aux2[4]; /* Auxiliary Registers,0xE0 */
  89. u8 res14[10];
  90. u8 aux_ad;
  91. u8 aux_da;
  92. u8 res15[16];
  93. };
  94. u8 qixis_read(unsigned int reg);
  95. void qixis_write(unsigned int reg, u8 value);
  96. u16 qixis_read_minor(void);
  97. char *qixis_read_time(char *result);
  98. char *qixis_read_tag(char *buf);
  99. const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
  100. #ifdef CONFIG_SYS_I2C_FPGA_ADDR
  101. u8 qixis_read_i2c(unsigned int reg);
  102. void qixis_write_i2c(unsigned int reg, u8 value);
  103. #endif
  104. #if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
  105. #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
  106. #define QIXIS_WRITE(reg, value) \
  107. qixis_write_i2c(offsetof(struct qixis, reg), value)
  108. #else
  109. #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
  110. #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
  111. #endif
  112. #ifdef CONFIG_SYS_I2C_FPGA_ADDR
  113. #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
  114. #define QIXIS_WRITE_I2C(reg, value) \
  115. qixis_write_i2c(offsetof(struct qixis, reg), value)
  116. #endif
  117. /* Use for SDHC adapter card type identification and operation */
  118. #define QIXIS_SDID_MASK 0x07
  119. #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
  120. #define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
  121. #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
  122. #define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */
  123. #define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */
  124. #define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
  125. #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
  126. #define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */
  127. #define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */
  128. #define QIXIS_SDCLKIN 0x08
  129. #define QIXIS_SDCLKOUT 0x02
  130. #define QIXIS_DAT5_6_7 0X02
  131. #define QIXIS_DAT4 0X01
  132. #define QIXIS_EVDD_BY_SDHC_VS 0x0c
  133. #endif