fsl-lx2160a.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP lx2160a SOC common device tree source
  4. *
  5. * Copyright 2018-2020 NXP
  6. *
  7. */
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. compatible = "fsl,lx2160a";
  11. interrupt-parent = <&gic>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. memory@80000000 {
  15. device_type = "memory";
  16. reg = <0x00000000 0x80000000 0 0x80000000>;
  17. /* DRAM space - 1, size : 2 GB DRAM */
  18. };
  19. sysclk: sysclk {
  20. compatible = "fixed-clock";
  21. #clock-cells = <0>;
  22. clock-frequency = <100000000>;
  23. clock-output-names = "sysclk";
  24. };
  25. clockgen: clocking@1300000 {
  26. compatible = "fsl,ls2080a-clockgen";
  27. reg = <0 0x1300000 0 0xa0000>;
  28. #clock-cells = <2>;
  29. clocks = <&sysclk>;
  30. };
  31. gic: interrupt-controller@6000000 {
  32. compatible = "arm,gic-v3";
  33. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  34. <0x0 0x06200000 0 0x100000>; /* GICR */
  35. #interrupt-cells = <3>;
  36. interrupt-controller;
  37. interrupts = <1 9 0x4>;
  38. };
  39. timer {
  40. compatible = "arm,armv8-timer";
  41. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  42. <1 14 0x8>, /* Physical NS PPI, active-low */
  43. <1 11 0x8>, /* Virtual PPI, active-low */
  44. <1 10 0x8>; /* Hypervisor PPI, active-low */
  45. };
  46. fspi: flexspi@20c0000 {
  47. compatible = "nxp,lx2160a-fspi";
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. reg = <0x0 0x20c0000 0x0 0x10000>,
  51. <0x0 0x20000000 0x0 0x10000000>;
  52. reg-names = "fspi_base", "fspi_mmap";
  53. clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  54. clock-names = "fspi_en", "fspi";
  55. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  56. status = "disabled";
  57. };
  58. i2c0: i2c@2000000 {
  59. compatible = "fsl,vf610-i2c";
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. reg = <0x0 0x2000000 0x0 0x10000>;
  63. interrupts = <0 34 4>;
  64. scl-gpio = <&gpio2 15 0>;
  65. status = "disabled";
  66. };
  67. i2c1: i2c@2010000 {
  68. compatible = "fsl,vf610-i2c";
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. reg = <0x0 0x2010000 0x0 0x10000>;
  72. interrupts = <0 34 4>;
  73. status = "disabled";
  74. };
  75. i2c2: i2c@2020000 {
  76. compatible = "fsl,vf610-i2c";
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. reg = <0x0 0x2020000 0x0 0x10000>;
  80. interrupts = <0 35 4>;
  81. status = "disabled";
  82. };
  83. i2c3: i2c@2030000 {
  84. compatible = "fsl,vf610-i2c";
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. reg = <0x0 0x2030000 0x0 0x10000>;
  88. interrupts = <0 35 4>;
  89. status = "disabled";
  90. };
  91. i2c4: i2c@2040000 {
  92. compatible = "fsl,vf610-i2c";
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. reg = <0x0 0x2040000 0x0 0x10000>;
  96. interrupts = <0 74 4>;
  97. scl-gpio = <&gpio2 16 0>;
  98. status = "disabled";
  99. };
  100. i2c5: i2c@2050000 {
  101. compatible = "fsl,vf610-i2c";
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. reg = <0x0 0x2050000 0x0 0x10000>;
  105. interrupts = <0 74 4>;
  106. status = "disabled";
  107. };
  108. i2c6: i2c@2060000 {
  109. compatible = "fsl,vf610-i2c";
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. reg = <0x0 0x2060000 0x0 0x10000>;
  113. interrupts = <0 75 4>;
  114. status = "disabled";
  115. };
  116. i2c7: i2c@2070000 {
  117. compatible = "fsl,vf610-i2c";
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. reg = <0x0 0x2070000 0x0 0x10000>;
  121. interrupts = <0 75 4>;
  122. status = "disabled";
  123. };
  124. uart0: serial@21c0000 {
  125. compatible = "arm,pl011";
  126. reg = <0x0 0x21c0000 0x0 0x1000>;
  127. clocks = <&clockgen 4 0>;
  128. status = "disabled";
  129. };
  130. uart1: serial@21d0000 {
  131. compatible = "arm,pl011";
  132. reg = <0x0 0x21d0000 0x0 0x1000>;
  133. clocks = <&clockgen 4 0>;
  134. status = "disabled";
  135. };
  136. uart2: serial@21e0000 {
  137. compatible = "arm,pl011";
  138. reg = <0x0 0x21e0000 0x0 0x1000>;
  139. clocks = <&clockgen 4 0>;
  140. status = "disabled";
  141. };
  142. uart3: serial@21f0000 {
  143. compatible = "arm,pl011";
  144. reg = <0x0 0x21f0000 0x0 0x1000>;
  145. clocks = <&clockgen 4 0>;
  146. status = "disabled";
  147. };
  148. dspi0: dspi@2100000 {
  149. compatible = "fsl,vf610-dspi";
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. reg = <0x0 0x2100000 0x0 0x10000>;
  153. interrupts = <0 26 0x4>; /* Level high type */
  154. num-cs = <6>;
  155. };
  156. dspi1: dspi@2110000 {
  157. compatible = "fsl,vf610-dspi";
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. reg = <0x0 0x2110000 0x0 0x10000>;
  161. interrupts = <0 26 0x4>; /* Level high type */
  162. num-cs = <6>;
  163. };
  164. dspi2: dspi@2120000 {
  165. compatible = "fsl,vf610-dspi";
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. reg = <0x0 0x2120000 0x0 0x10000>;
  169. interrupts = <0 241 0x4>; /* Level high type */
  170. num-cs = <6>;
  171. };
  172. gpio2: gpio@2320000 {
  173. compatible = "fsl,qoriq-gpio";
  174. reg = <0x0 0x2320000 0x0 0x10000>;
  175. interrupts = <0 37 4>;
  176. gpio-controller;
  177. little-endian;
  178. #gpio-cells = <2>;
  179. interrupt-controller;
  180. #interrupt-cells = <2>;
  181. };
  182. watchdog@23a0000 {
  183. compatible = "arm,sbsa-gwdt";
  184. reg = <0x0 0x23a0000 0 0x1000>,
  185. <0x0 0x2390000 0 0x1000>;
  186. timeout-sec = <30>;
  187. };
  188. usb0: usb3@3100000 {
  189. compatible = "fsl,layerscape-dwc3";
  190. reg = <0x0 0x3100000 0x0 0x10000>;
  191. interrupts = <0 80 0x4>; /* Level high type */
  192. dr_mode = "host";
  193. };
  194. usb1: usb3@3110000 {
  195. compatible = "fsl,layerscape-dwc3";
  196. reg = <0x0 0x3110000 0x0 0x10000>;
  197. interrupts = <0 81 0x4>; /* Level high type */
  198. dr_mode = "host";
  199. };
  200. esdhc0: esdhc@2140000 {
  201. compatible = "fsl,esdhc";
  202. reg = <0x0 0x2140000 0x0 0x10000>;
  203. interrupts = <0 28 0x4>; /* Level high type */
  204. clocks = <&clockgen 4 1>;
  205. voltage-ranges = <1800 1800 3300 3300>;
  206. sdhci,auto-cmd12;
  207. little-endian;
  208. bus-width = <4>;
  209. status = "disabled";
  210. };
  211. esdhc1: esdhc@2150000 {
  212. compatible = "fsl,esdhc";
  213. reg = <0x0 0x2150000 0x0 0x10000>;
  214. interrupts = <0 63 0x4>; /* Level high type */
  215. clocks = <&clockgen 4 1>;
  216. voltage-ranges = <1800 1800 3300 3300>;
  217. sdhci,auto-cmd12;
  218. non-removable;
  219. little-endian;
  220. bus-width = <4>;
  221. status = "disabled";
  222. };
  223. sata0: sata@3200000 {
  224. compatible = "fsl,ls2080a-ahci";
  225. reg = <0x0 0x3200000 0x0 0x10000>;
  226. interrupts = <0 133 4>;
  227. clocks = <&clockgen 4 3>;
  228. status = "disabled";
  229. };
  230. sata1: sata@3210000 {
  231. compatible = "fsl,ls2080a-ahci";
  232. reg = <0x0 0x3210000 0x0 0x10000>;
  233. interrupts = <0 136 4>;
  234. clocks = <&clockgen 4 3>;
  235. status = "disabled";
  236. };
  237. sata2: sata@3220000 {
  238. compatible = "fsl,ls2080a-ahci";
  239. reg = <0x0 0x3220000 0x0 0x10000>;
  240. interrupts = <0 97 4>;
  241. clocks = <&clockgen 4 3>;
  242. status = "disabled";
  243. };
  244. sata3: sata@3230000 {
  245. compatible = "fsl,ls2080a-ahci";
  246. reg = <0x0 0x3230000 0x0 0x10000>;
  247. interrupts = <0 100 4>;
  248. clocks = <&clockgen 4 3>;
  249. status = "disabled";
  250. };
  251. pcie@3400000 {
  252. compatible = "fsl,lx2160a-pcie";
  253. reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
  254. 0x00 0x03480000 0x0 0x40000 /* LUT registers */
  255. 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
  256. 0x80 0x00000000 0x0 0x2000>; /* configuration space */
  257. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  258. #address-cells = <3>;
  259. #size-cells = <2>;
  260. device_type = "pci";
  261. bus-range = <0x0 0xff>;
  262. ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
  263. };
  264. pcie@3500000 {
  265. compatible = "fsl,lx2160a-pcie";
  266. reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
  267. 0x00 0x03580000 0x0 0x40000 /* LUT registers */
  268. 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
  269. 0x88 0x00000000 0x0 0x2000>; /* configuration space */
  270. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  271. #address-cells = <3>;
  272. #size-cells = <2>;
  273. device_type = "pci";
  274. num-lanes = <2>;
  275. bus-range = <0x0 0xff>;
  276. ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
  277. };
  278. pcie@3600000 {
  279. compatible = "fsl,lx2160a-pcie";
  280. reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
  281. 0x00 0x03680000 0x0 0x40000 /* LUT registers */
  282. 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
  283. 0x90 0x00000000 0x0 0x2000>; /* configuration space */
  284. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  285. #address-cells = <3>;
  286. #size-cells = <2>;
  287. device_type = "pci";
  288. bus-range = <0x0 0xff>;
  289. ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
  290. };
  291. pcie@3700000 {
  292. compatible = "fsl,lx2160a-pcie";
  293. reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
  294. 0x00 0x03780000 0x0 0x40000 /* LUT registers */
  295. 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
  296. 0x98 0x00000000 0x0 0x2000>; /* configuration space */
  297. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  298. #address-cells = <3>;
  299. #size-cells = <2>;
  300. device_type = "pci";
  301. bus-range = <0x0 0xff>;
  302. ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
  303. };
  304. pcie@3800000 {
  305. compatible = "fsl,lx2160a-pcie";
  306. reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
  307. 0x00 0x03880000 0x0 0x40000 /* LUT registers */
  308. 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
  309. 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
  310. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  311. #address-cells = <3>;
  312. #size-cells = <2>;
  313. device_type = "pci";
  314. bus-range = <0x0 0xff>;
  315. ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
  316. };
  317. pcie@3900000 {
  318. compatible = "fsl,lx2160a-pcie";
  319. reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
  320. 0x00 0x03980000 0x0 0x40000 /* LUT registers */
  321. 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
  322. 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
  323. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  324. #address-cells = <3>;
  325. #size-cells = <2>;
  326. device_type = "pci";
  327. bus-range = <0x0 0xff>;
  328. ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
  329. };
  330. fsl_mc: fsl-mc@80c000000 {
  331. compatible = "fsl,qoriq-mc", "simple-mfd";
  332. reg = <0x00000008 0x0c000000 0 0x40>,
  333. <0x00000000 0x08340000 0 0x40000>;
  334. #address-cells = <3>;
  335. #size-cells = <1>;
  336. /*
  337. * Region type 0x0 - MC portals
  338. * Region type 0x1 - QBMAN portals
  339. */
  340. ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
  341. 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
  342. dpmacs {
  343. compatible = "simple-mfd";
  344. #address-cells = <1>;
  345. #size-cells = <0>;
  346. dpmac1: dpmac@1 {
  347. compatible = "fsl,qoriq-mc-dpmac";
  348. reg = <0x1>;
  349. status = "disabled";
  350. };
  351. dpmac2: dpmac@2 {
  352. compatible = "fsl,qoriq-mc-dpmac";
  353. reg = <0x2>;
  354. status = "disabled";
  355. };
  356. dpmac3: dpmac@3 {
  357. compatible = "fsl,qoriq-mc-dpmac";
  358. reg = <0x3>;
  359. status = "disabled";
  360. };
  361. dpmac4: dpmac@4 {
  362. compatible = "fsl,qoriq-mc-dpmac";
  363. reg = <0x4>;
  364. status = "disabled";
  365. };
  366. dpmac5: dpmac@5 {
  367. compatible = "fsl,qoriq-mc-dpmac";
  368. reg = <0x5>;
  369. status = "disabled";
  370. };
  371. dpmac6: dpmac@6 {
  372. compatible = "fsl,qoriq-mc-dpmac";
  373. reg = <0x6>;
  374. status = "disabled";
  375. };
  376. dpmac7: dpmac@7 {
  377. compatible = "fsl,qoriq-mc-dpmac";
  378. reg = <0x7>;
  379. status = "disabled";
  380. };
  381. dpmac8: dpmac@8 {
  382. compatible = "fsl,qoriq-mc-dpmac";
  383. reg = <0x8>;
  384. status = "disabled";
  385. };
  386. dpmac9: dpmac@9 {
  387. compatible = "fsl,qoriq-mc-dpmac";
  388. reg = <0x9>;
  389. status = "disabled";
  390. };
  391. dpmac10: dpmac@a {
  392. compatible = "fsl,qoriq-mc-dpmac";
  393. reg = <0xa>;
  394. status = "disabled";
  395. };
  396. dpmac11: dpmac@b {
  397. compatible = "fsl,qoriq-mc-dpmac";
  398. reg = <0xb>;
  399. status = "disabled";
  400. };
  401. dpmac12: dpmac@c {
  402. compatible = "fsl,qoriq-mc-dpmac";
  403. reg = <0xc>;
  404. status = "disabled";
  405. };
  406. dpmac13: dpmac@d {
  407. compatible = "fsl,qoriq-mc-dpmac";
  408. reg = <0xd>;
  409. status = "disabled";
  410. };
  411. dpmac14: dpmac@e {
  412. compatible = "fsl,qoriq-mc-dpmac";
  413. reg = <0xe>;
  414. status = "disabled";
  415. };
  416. dpmac15: dpmac@f {
  417. compatible = "fsl,qoriq-mc-dpmac";
  418. reg = <0xf>;
  419. status = "disabled";
  420. };
  421. dpmac16: dpmac@10 {
  422. compatible = "fsl,qoriq-mc-dpmac";
  423. reg = <0x10>;
  424. status = "disabled";
  425. };
  426. dpmac17: dpmac@11 {
  427. compatible = "fsl,qoriq-mc-dpmac";
  428. reg = <0x11>;
  429. status = "disabled";
  430. };
  431. dpmac18: dpmac@12 {
  432. compatible = "fsl,qoriq-mc-dpmac";
  433. reg = <0x12>;
  434. status = "disabled";
  435. };
  436. };
  437. };
  438. /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
  439. emdio1: mdio@8b96000 {
  440. compatible = "fsl,ls-mdio";
  441. reg = <0x0 0x8b96000 0x0 0x1000>;
  442. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  443. #address-cells = <1>;
  444. #size-cells = <0>;
  445. status = "disabled";
  446. };
  447. /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
  448. emdio2: mdio@8b97000 {
  449. compatible = "fsl,ls-mdio";
  450. reg = <0x0 0x8b97000 0x0 0x1000>;
  451. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  452. #address-cells = <1>;
  453. #size-cells = <0>;
  454. status = "disabled";
  455. };
  456. firmware {
  457. optee {
  458. compatible = "linaro,optee-tz";
  459. method = "smc";
  460. };
  461. };
  462. };