soc.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <fsl_immap.h>
  11. #include <fsl_ifc.h>
  12. #include <init.h>
  13. #include <linux/sizes.h>
  14. #include <log.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/cache.h>
  18. #include <asm/io.h>
  19. #include <asm/global_data.h>
  20. #include <asm/arch-fsl-layerscape/config.h>
  21. #include <asm/arch-fsl-layerscape/ns_access.h>
  22. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  23. #include <asm/gic-v3.h>
  24. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  25. #include <fsl_csu.h>
  26. #endif
  27. #ifdef CONFIG_SYS_FSL_DDR
  28. #include <fsl_ddr_sdram.h>
  29. #include <fsl_ddr.h>
  30. #endif
  31. #ifdef CONFIG_CHAIN_OF_TRUST
  32. #include <fsl_validate.h>
  33. #endif
  34. #include <fsl_immap.h>
  35. #ifdef CONFIG_TFABOOT
  36. #include <env_internal.h>
  37. #endif
  38. #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #endif
  41. #ifdef CONFIG_GIC_V3_ITS
  42. #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
  43. #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
  44. #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
  45. PROPTABLE_MAX_SZ, SZ_1M)
  46. static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
  47. {
  48. u32 phandle;
  49. int err;
  50. struct fdt_memory gic_rd_tables;
  51. gic_rd_tables.start = base;
  52. gic_rd_tables.end = base + size - 1;
  53. err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
  54. &phandle);
  55. if (err < 0)
  56. debug("%s: failed to add reserved memory: %d\n", __func__, err);
  57. return err;
  58. }
  59. int ls_gic_rd_tables_init(void *blob)
  60. {
  61. u64 gic_lpi_base;
  62. int ret;
  63. gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
  64. ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
  65. if (ret)
  66. return ret;
  67. ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
  68. if (ret)
  69. debug("%s: failed to init gic-lpi-tables\n", __func__);
  70. return ret;
  71. }
  72. #endif
  73. bool soc_has_dp_ddr(void)
  74. {
  75. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  76. u32 svr = gur_in32(&gur->svr);
  77. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  78. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  79. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  80. (SVR_SOC_VER(svr) == SVR_LS2048A))
  81. return true;
  82. return false;
  83. }
  84. bool soc_has_aiop(void)
  85. {
  86. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  87. u32 svr = gur_in32(&gur->svr);
  88. /* LS2085A has AIOP */
  89. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  90. return true;
  91. return false;
  92. }
  93. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  94. {
  95. scfg_clrsetbits32(scfg + offset / 4,
  96. 0xF << 6,
  97. SCFG_USB_TXVREFTUNE << 6);
  98. }
  99. static void erratum_a009008(void)
  100. {
  101. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  102. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  103. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  104. defined(CONFIG_ARCH_LS1012A)
  105. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  106. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  107. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  108. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  109. #endif
  110. #elif defined(CONFIG_ARCH_LS2080A)
  111. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  112. #endif
  113. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  114. }
  115. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  116. {
  117. scfg_clrbits32(scfg + offset / 4,
  118. SCFG_USB_SQRXTUNE_MASK << 23);
  119. }
  120. static void erratum_a009798(void)
  121. {
  122. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  123. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  124. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  125. defined(CONFIG_ARCH_LS1012A)
  126. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  127. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  128. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  129. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  130. #endif
  131. #elif defined(CONFIG_ARCH_LS2080A)
  132. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  133. #endif
  134. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  135. }
  136. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  137. defined(CONFIG_ARCH_LS1012A)
  138. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  139. {
  140. scfg_clrsetbits32(scfg + offset / 4,
  141. 0x7F << 9,
  142. SCFG_USB_PCSTXSWINGFULL << 9);
  143. }
  144. #endif
  145. static void erratum_a008997(void)
  146. {
  147. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  148. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  149. defined(CONFIG_ARCH_LS1012A)
  150. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  151. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  152. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  153. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  154. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  155. #endif
  156. #elif defined(CONFIG_ARCH_LS1028A)
  157. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  158. 0x7F << 11,
  159. DCSR_USB_PCSTXSWINGFULL << 11);
  160. #endif
  161. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  162. }
  163. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  164. defined(CONFIG_ARCH_LS1012A)
  165. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  166. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  167. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  168. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  169. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  170. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  171. defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
  172. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  173. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  174. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  175. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  176. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  177. #endif
  178. static void erratum_a009007(void)
  179. {
  180. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  181. defined(CONFIG_ARCH_LS1012A)
  182. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  183. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  184. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  185. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  186. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  187. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  188. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  189. #endif
  190. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  191. defined(CONFIG_ARCH_LS1028A)
  192. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  193. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  194. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  195. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  196. }
  197. #if defined(CONFIG_FSL_LSCH3)
  198. static void erratum_a050106(void)
  199. {
  200. #if defined(CONFIG_ARCH_LX2160A)
  201. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  202. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  203. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  204. #endif
  205. }
  206. /*
  207. * This erratum requires setting a value to eddrtqcr1 to
  208. * optimal the DDR performance.
  209. */
  210. static void erratum_a008336(void)
  211. {
  212. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  213. u32 *eddrtqcr1;
  214. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  215. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  216. if (fsl_ddr_get_version(0) == 0x50200)
  217. out_le32(eddrtqcr1, 0x63b30002);
  218. #endif
  219. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  220. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  221. if (fsl_ddr_get_version(0) == 0x50200)
  222. out_le32(eddrtqcr1, 0x63b30002);
  223. #endif
  224. #endif
  225. }
  226. /*
  227. * This erratum requires a register write before being Memory
  228. * controller 3 being enabled.
  229. */
  230. static void erratum_a008514(void)
  231. {
  232. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  233. u32 *eddrtqcr1;
  234. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  235. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  236. out_le32(eddrtqcr1, 0x63b20002);
  237. #endif
  238. #endif
  239. }
  240. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  241. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  242. static unsigned long get_internval_val_mhz(void)
  243. {
  244. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  245. /*
  246. * interval is the number of platform cycles(MHz) between
  247. * wake up events generated by EPU.
  248. */
  249. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  250. if (interval)
  251. interval_mhz = simple_strtoul(interval, NULL, 10);
  252. return interval_mhz;
  253. }
  254. void erratum_a009635(void)
  255. {
  256. u32 val;
  257. unsigned long interval_mhz = get_internval_val_mhz();
  258. if (!interval_mhz)
  259. return;
  260. val = in_le32(DCSR_CGACRE5);
  261. writel(val | 0x00000200, DCSR_CGACRE5);
  262. val = in_le32(EPU_EPCMPR5);
  263. writel(interval_mhz, EPU_EPCMPR5);
  264. val = in_le32(EPU_EPCCR5);
  265. writel(val | 0x82820000, EPU_EPCCR5);
  266. val = in_le32(EPU_EPSMCR5);
  267. writel(val | 0x002f0000, EPU_EPSMCR5);
  268. val = in_le32(EPU_EPECR5);
  269. writel(val | 0x20000000, EPU_EPECR5);
  270. val = in_le32(EPU_EPGCR);
  271. writel(val | 0x80000000, EPU_EPGCR);
  272. }
  273. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  274. static void erratum_rcw_src(void)
  275. {
  276. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  277. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  278. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  279. u32 val;
  280. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  281. val &= ~DCFG_PORSR1_RCW_SRC;
  282. val |= DCFG_PORSR1_RCW_SRC_NOR;
  283. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  284. #endif
  285. }
  286. #define I2C_DEBUG_REG 0x6
  287. #define I2C_GLITCH_EN 0x8
  288. /*
  289. * This erratum requires setting glitch_en bit to enable
  290. * digital glitch filter to improve clock stability.
  291. */
  292. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  293. static void erratum_a009203(void)
  294. {
  295. #ifdef CONFIG_SYS_I2C
  296. u8 __iomem *ptr;
  297. #ifdef I2C1_BASE_ADDR
  298. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  299. writeb(I2C_GLITCH_EN, ptr);
  300. #endif
  301. #ifdef I2C2_BASE_ADDR
  302. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  303. writeb(I2C_GLITCH_EN, ptr);
  304. #endif
  305. #ifdef I2C3_BASE_ADDR
  306. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  307. writeb(I2C_GLITCH_EN, ptr);
  308. #endif
  309. #ifdef I2C4_BASE_ADDR
  310. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  311. writeb(I2C_GLITCH_EN, ptr);
  312. #endif
  313. #endif
  314. }
  315. #endif
  316. void bypass_smmu(void)
  317. {
  318. u32 val;
  319. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  320. out_le32(SMMU_SCR0, val);
  321. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  322. out_le32(SMMU_NSCR0, val);
  323. }
  324. void fsl_lsch3_early_init_f(void)
  325. {
  326. erratum_rcw_src();
  327. #ifdef CONFIG_FSL_IFC
  328. init_early_memctl_regs(); /* tighten IFC timing */
  329. #endif
  330. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  331. erratum_a009203();
  332. #endif
  333. erratum_a008514();
  334. erratum_a008336();
  335. erratum_a009008();
  336. erratum_a009798();
  337. erratum_a008997();
  338. erratum_a009007();
  339. erratum_a050106();
  340. #ifdef CONFIG_CHAIN_OF_TRUST
  341. /* In case of Secure Boot, the IBR configures the SMMU
  342. * to allow only Secure transactions.
  343. * SMMU must be reset in bypass mode.
  344. * Set the ClientPD bit and Clear the USFCFG Bit
  345. */
  346. if (fsl_check_boot_mode_secure() == 1)
  347. bypass_smmu();
  348. #endif
  349. #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
  350. defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
  351. set_icids();
  352. #endif
  353. }
  354. /* Get VDD in the unit mV from voltage ID */
  355. int get_core_volt_from_fuse(void)
  356. {
  357. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  358. int vdd;
  359. u32 fusesr;
  360. u8 vid;
  361. /* get the voltage ID from fuse status register */
  362. fusesr = in_le32(&gur->dcfg_fusesr);
  363. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  364. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  365. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  366. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  367. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  368. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  369. }
  370. debug("%s: VID = 0x%x\n", __func__, vid);
  371. switch (vid) {
  372. case 0x00: /* VID isn't supported */
  373. vdd = -EINVAL;
  374. debug("%s: The VID feature is not supported\n", __func__);
  375. break;
  376. case 0x08: /* 0.9V silicon */
  377. vdd = 900;
  378. break;
  379. case 0x10: /* 1.0V silicon */
  380. vdd = 1000;
  381. break;
  382. default: /* Other core voltage */
  383. vdd = -EINVAL;
  384. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  385. break;
  386. }
  387. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  388. return vdd;
  389. }
  390. #elif defined(CONFIG_FSL_LSCH2)
  391. /*
  392. * This erratum requires setting a value to eddrtqcr1 to optimal
  393. * the DDR performance. The eddrtqcr1 register is in SCFG space
  394. * of LS1043A and the offset is 0x157_020c.
  395. */
  396. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  397. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  398. #error A009660 and A008514 can not be both enabled.
  399. #endif
  400. static void erratum_a009660(void)
  401. {
  402. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  403. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  404. out_be32(eddrtqcr1, 0x63b20042);
  405. #endif
  406. }
  407. static void erratum_a008850_early(void)
  408. {
  409. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  410. /* part 1 of 2 */
  411. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  412. CONFIG_SYS_CCI400_OFFSET);
  413. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  414. /* Skip if running at lower exception level */
  415. if (current_el() < 3)
  416. return;
  417. /* disables propagation of barrier transactions to DDRC from CCI400 */
  418. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  419. /* disable the re-ordering in DDRC */
  420. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  421. #endif
  422. }
  423. void erratum_a008850_post(void)
  424. {
  425. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  426. /* part 2 of 2 */
  427. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  428. CONFIG_SYS_CCI400_OFFSET);
  429. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  430. u32 tmp;
  431. /* Skip if running at lower exception level */
  432. if (current_el() < 3)
  433. return;
  434. /* enable propagation of barrier transactions to DDRC from CCI400 */
  435. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  436. /* enable the re-ordering in DDRC */
  437. tmp = ddr_in32(&ddr->eor);
  438. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  439. ddr_out32(&ddr->eor, tmp);
  440. #endif
  441. }
  442. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  443. void erratum_a010315(void)
  444. {
  445. int i;
  446. for (i = PCIE1; i <= PCIE4; i++)
  447. if (!is_serdes_configured(i)) {
  448. debug("PCIe%d: disabled all R/W permission!\n", i);
  449. set_pcie_ns_access(i, 0);
  450. }
  451. }
  452. #endif
  453. static void erratum_a010539(void)
  454. {
  455. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  456. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  457. u32 porsr1;
  458. porsr1 = in_be32(&gur->porsr1);
  459. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  460. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  461. porsr1);
  462. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  463. #endif
  464. }
  465. /* Get VDD in the unit mV from voltage ID */
  466. int get_core_volt_from_fuse(void)
  467. {
  468. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  469. int vdd;
  470. u32 fusesr;
  471. u8 vid;
  472. fusesr = in_be32(&gur->dcfg_fusesr);
  473. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  474. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  475. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  476. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  477. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  478. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  479. }
  480. debug("%s: VID = 0x%x\n", __func__, vid);
  481. switch (vid) {
  482. case 0x00: /* VID isn't supported */
  483. vdd = -EINVAL;
  484. debug("%s: The VID feature is not supported\n", __func__);
  485. break;
  486. case 0x08: /* 0.9V silicon */
  487. vdd = 900;
  488. break;
  489. case 0x10: /* 1.0V silicon */
  490. vdd = 1000;
  491. break;
  492. default: /* Other core voltage */
  493. vdd = -EINVAL;
  494. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  495. break;
  496. }
  497. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  498. return vdd;
  499. }
  500. __weak int board_switch_core_volt(u32 vdd)
  501. {
  502. return 0;
  503. }
  504. static int setup_core_volt(u32 vdd)
  505. {
  506. return board_setup_core_volt(vdd);
  507. }
  508. #ifdef CONFIG_SYS_FSL_DDR
  509. static void ddr_enable_0v9_volt(bool en)
  510. {
  511. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  512. u32 tmp;
  513. tmp = ddr_in32(&ddr->ddr_cdr1);
  514. if (en)
  515. tmp |= DDR_CDR1_V0PT9_EN;
  516. else
  517. tmp &= ~DDR_CDR1_V0PT9_EN;
  518. ddr_out32(&ddr->ddr_cdr1, tmp);
  519. }
  520. #endif
  521. int setup_chip_volt(void)
  522. {
  523. int vdd;
  524. vdd = get_core_volt_from_fuse();
  525. /* Nothing to do for silicons doesn't support VID */
  526. if (vdd < 0)
  527. return vdd;
  528. if (setup_core_volt(vdd))
  529. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  530. #ifdef CONFIG_SYS_HAS_SERDES
  531. if (setup_serdes_volt(vdd))
  532. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  533. #endif
  534. #ifdef CONFIG_SYS_FSL_DDR
  535. if (vdd == 900)
  536. ddr_enable_0v9_volt(true);
  537. #endif
  538. return 0;
  539. }
  540. #ifdef CONFIG_FSL_PFE
  541. void init_pfe_scfg_dcfg_regs(void)
  542. {
  543. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  544. u32 ecccr2;
  545. out_be32(&scfg->pfeasbcr,
  546. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  547. out_be32(&scfg->pfebsbcr,
  548. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  549. /* CCI-400 QoS settings for PFE */
  550. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  551. | SCFG_WR_QOS1_PFE2_QOS));
  552. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  553. | SCFG_RD_QOS1_PFE2_QOS));
  554. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  555. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  556. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  557. }
  558. #endif
  559. void fsl_lsch2_early_init_f(void)
  560. {
  561. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  562. CONFIG_SYS_CCI400_OFFSET);
  563. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  564. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  565. enum boot_src src;
  566. #endif
  567. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  568. enable_layerscape_ns_access();
  569. #endif
  570. #ifdef CONFIG_FSL_IFC
  571. init_early_memctl_regs(); /* tighten IFC timing */
  572. #endif
  573. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  574. src = get_boot_src();
  575. if (src != BOOT_SOURCE_QSPI_NOR)
  576. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  577. #else
  578. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  579. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  580. #endif
  581. #endif
  582. /* Make SEC reads and writes snoopable */
  583. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  584. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  585. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  586. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
  587. SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
  588. SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  589. SCFG_SNPCNFGCR_SATAWRSNP);
  590. #elif defined(CONFIG_ARCH_LS1012A)
  591. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  592. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  593. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  594. SCFG_SNPCNFGCR_SATAWRSNP);
  595. #else
  596. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  597. SCFG_SNPCNFGCR_SECWRSNP |
  598. SCFG_SNPCNFGCR_SATARDSNP |
  599. SCFG_SNPCNFGCR_SATAWRSNP);
  600. #endif
  601. /*
  602. * Enable snoop requests and DVM message requests for
  603. * Slave insterface S4 (A53 core cluster)
  604. */
  605. if (current_el() == 3) {
  606. out_le32(&cci->slave[4].snoop_ctrl,
  607. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  608. }
  609. /*
  610. * Program Central Security Unit (CSU) to grant access
  611. * permission for USB 2.0 controller
  612. */
  613. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  614. if (current_el() == 3)
  615. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  616. #endif
  617. /* Erratum */
  618. erratum_a008850_early(); /* part 1 of 2 */
  619. erratum_a009660();
  620. erratum_a010539();
  621. erratum_a009008();
  622. erratum_a009798();
  623. erratum_a008997();
  624. erratum_a009007();
  625. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  626. set_icids();
  627. #endif
  628. }
  629. #endif
  630. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  631. int fspi_ahb_init(void)
  632. {
  633. /* Enable 4bytes address support and fast read */
  634. u32 *fspi_lut, lut_key, *fspi_key;
  635. fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
  636. fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
  637. lut_key = in_be32(fspi_key);
  638. if (lut_key == SYS_NXP_FSPI_LUTKEY) {
  639. /* That means the register is BE */
  640. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  641. /* Unlock the lut table */
  642. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  643. /* Create READ LUT */
  644. out_be32(fspi_lut, 0x0820040c);
  645. out_be32(fspi_lut + 1, 0x24003008);
  646. out_be32(fspi_lut + 2, 0x00000000);
  647. /* Lock the lut table */
  648. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  649. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  650. } else {
  651. /* That means the register is LE */
  652. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  653. /* Unlock the lut table */
  654. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  655. /* Create READ LUT */
  656. out_le32(fspi_lut, 0x0820040c);
  657. out_le32(fspi_lut + 1, 0x24003008);
  658. out_le32(fspi_lut + 2, 0x00000000);
  659. /* Lock the lut table */
  660. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  661. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  662. }
  663. return 0;
  664. }
  665. #endif
  666. #ifdef CONFIG_QSPI_AHB_INIT
  667. /* Enable 4bytes address support and fast read */
  668. int qspi_ahb_init(void)
  669. {
  670. u32 *qspi_lut, lut_key, *qspi_key;
  671. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  672. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  673. lut_key = in_be32(qspi_key);
  674. if (lut_key == 0x5af05af0) {
  675. /* That means the register is BE */
  676. out_be32(qspi_key, 0x5af05af0);
  677. /* Unlock the lut table */
  678. out_be32(qspi_key + 1, 0x00000002);
  679. out_be32(qspi_lut, 0x0820040c);
  680. out_be32(qspi_lut + 1, 0x1c080c08);
  681. out_be32(qspi_lut + 2, 0x00002400);
  682. /* Lock the lut table */
  683. out_be32(qspi_key, 0x5af05af0);
  684. out_be32(qspi_key + 1, 0x00000001);
  685. } else {
  686. /* That means the register is LE */
  687. out_le32(qspi_key, 0x5af05af0);
  688. /* Unlock the lut table */
  689. out_le32(qspi_key + 1, 0x00000002);
  690. out_le32(qspi_lut, 0x0820040c);
  691. out_le32(qspi_lut + 1, 0x1c080c08);
  692. out_le32(qspi_lut + 2, 0x00002400);
  693. /* Lock the lut table */
  694. out_le32(qspi_key, 0x5af05af0);
  695. out_le32(qspi_key + 1, 0x00000001);
  696. }
  697. return 0;
  698. }
  699. #endif
  700. #ifdef CONFIG_TFABOOT
  701. #define MAX_BOOTCMD_SIZE 512
  702. int fsl_setenv_bootcmd(void)
  703. {
  704. int ret;
  705. enum boot_src src = get_boot_src();
  706. char bootcmd_str[MAX_BOOTCMD_SIZE];
  707. switch (src) {
  708. #ifdef IFC_NOR_BOOTCOMMAND
  709. case BOOT_SOURCE_IFC_NOR:
  710. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  711. break;
  712. #endif
  713. #ifdef QSPI_NOR_BOOTCOMMAND
  714. case BOOT_SOURCE_QSPI_NOR:
  715. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  716. break;
  717. #endif
  718. #ifdef XSPI_NOR_BOOTCOMMAND
  719. case BOOT_SOURCE_XSPI_NOR:
  720. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  721. break;
  722. #endif
  723. #ifdef IFC_NAND_BOOTCOMMAND
  724. case BOOT_SOURCE_IFC_NAND:
  725. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  726. break;
  727. #endif
  728. #ifdef QSPI_NAND_BOOTCOMMAND
  729. case BOOT_SOURCE_QSPI_NAND:
  730. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  731. break;
  732. #endif
  733. #ifdef XSPI_NAND_BOOTCOMMAND
  734. case BOOT_SOURCE_XSPI_NAND:
  735. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  736. break;
  737. #endif
  738. #ifdef SD_BOOTCOMMAND
  739. case BOOT_SOURCE_SD_MMC:
  740. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  741. break;
  742. #endif
  743. #ifdef SD2_BOOTCOMMAND
  744. case BOOT_SOURCE_SD_MMC2:
  745. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  746. break;
  747. #endif
  748. default:
  749. #ifdef QSPI_NOR_BOOTCOMMAND
  750. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  751. #endif
  752. break;
  753. }
  754. ret = env_set("bootcmd", bootcmd_str);
  755. if (ret) {
  756. printf("Failed to set bootcmd: ret = %d\n", ret);
  757. return ret;
  758. }
  759. return 0;
  760. }
  761. int fsl_setenv_mcinitcmd(void)
  762. {
  763. int ret = 0;
  764. enum boot_src src = get_boot_src();
  765. switch (src) {
  766. #ifdef IFC_MC_INIT_CMD
  767. case BOOT_SOURCE_IFC_NAND:
  768. case BOOT_SOURCE_IFC_NOR:
  769. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  770. break;
  771. #endif
  772. #ifdef QSPI_MC_INIT_CMD
  773. case BOOT_SOURCE_QSPI_NAND:
  774. case BOOT_SOURCE_QSPI_NOR:
  775. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  776. break;
  777. #endif
  778. #ifdef XSPI_MC_INIT_CMD
  779. case BOOT_SOURCE_XSPI_NAND:
  780. case BOOT_SOURCE_XSPI_NOR:
  781. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  782. break;
  783. #endif
  784. #ifdef SD_MC_INIT_CMD
  785. case BOOT_SOURCE_SD_MMC:
  786. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  787. break;
  788. #endif
  789. #ifdef SD2_MC_INIT_CMD
  790. case BOOT_SOURCE_SD_MMC2:
  791. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  792. break;
  793. #endif
  794. default:
  795. #ifdef QSPI_MC_INIT_CMD
  796. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  797. #endif
  798. break;
  799. }
  800. if (ret) {
  801. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  802. return ret;
  803. }
  804. return 0;
  805. }
  806. #endif
  807. #ifdef CONFIG_BOARD_LATE_INIT
  808. __weak int fsl_board_late_init(void)
  809. {
  810. return 0;
  811. }
  812. int board_late_init(void)
  813. {
  814. #ifdef CONFIG_CHAIN_OF_TRUST
  815. fsl_setenv_chain_of_trust();
  816. #endif
  817. #ifdef CONFIG_TFABOOT
  818. /*
  819. * check if gd->env_addr is default_environment; then setenv bootcmd
  820. * and mcinitcmd.
  821. */
  822. #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
  823. if (gd->env_addr == (ulong)&default_environment[0]) {
  824. #else
  825. if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  826. #endif
  827. fsl_setenv_bootcmd();
  828. fsl_setenv_mcinitcmd();
  829. }
  830. /*
  831. * If the boot mode is secure, default environment is not present then
  832. * setenv command needs to be run by default
  833. */
  834. #ifdef CONFIG_CHAIN_OF_TRUST
  835. if ((fsl_check_boot_mode_secure() == 1)) {
  836. fsl_setenv_bootcmd();
  837. fsl_setenv_mcinitcmd();
  838. }
  839. #endif
  840. #endif
  841. #ifdef CONFIG_QSPI_AHB_INIT
  842. qspi_ahb_init();
  843. #endif
  844. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  845. fspi_ahb_init();
  846. #endif
  847. return fsl_board_late_init();
  848. }
  849. #endif