mp.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <image.h>
  8. #include <log.h>
  9. #include <asm/cache.h>
  10. #include <asm/io.h>
  11. #include <asm/system.h>
  12. #include <asm/arch/mp.h>
  13. #include <asm/arch/soc.h>
  14. #include <linux/delay.h>
  15. #include "cpu.h"
  16. #include <asm/arch-fsl-layerscape/soc.h>
  17. #include <efi_loader.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. void *get_spin_tbl_addr(void)
  20. {
  21. /* the spin table is at the beginning */
  22. return secondary_boot_code_start;
  23. }
  24. void update_os_arch_secondary_cores(uint8_t os_arch)
  25. {
  26. u64 *table = get_spin_tbl_addr();
  27. int i;
  28. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  29. if (os_arch == IH_ARCH_DEFAULT)
  30. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  31. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  32. else
  33. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  34. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  35. }
  36. }
  37. #ifdef CONFIG_FSL_LSCH3
  38. static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  39. {
  40. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  41. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  42. u32 mpidr = 0;
  43. mpidr = ((cluster << 8) | core);
  44. /*
  45. * mpidr_el1 register value of core which needs to be released
  46. * is written to scratchrw[6] register
  47. */
  48. gur_out32(&gur->scratchrw[6], mpidr);
  49. asm volatile("dsb st" : : : "memory");
  50. rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  51. asm volatile("dsb st" : : : "memory");
  52. /*
  53. * scratchrw[6] register value is polled
  54. * when the value becomes zero, this means that this core is up
  55. * and running, next core can be released now
  56. */
  57. while (gur_in32(&gur->scratchrw[6]) != 0)
  58. ;
  59. }
  60. #endif
  61. int fsl_layerscape_wake_seconday_cores(void)
  62. {
  63. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  64. #ifdef CONFIG_FSL_LSCH3
  65. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  66. u32 svr, ver, cluster, type;
  67. int j = 0, cluster_cores = 0;
  68. #elif defined(CONFIG_FSL_LSCH2)
  69. struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  70. #endif
  71. u32 cores, cpu_up_mask = 1;
  72. int i, timeout = 10;
  73. u64 *table;
  74. #ifdef CONFIG_EFI_LOADER
  75. u64 reloc_addr = U32_MAX;
  76. efi_status_t ret;
  77. #endif
  78. #ifdef COUNTER_FREQUENCY_REAL
  79. /* update for secondary cores */
  80. __real_cntfrq = COUNTER_FREQUENCY_REAL;
  81. flush_dcache_range((unsigned long)&__real_cntfrq,
  82. (unsigned long)&__real_cntfrq + 8);
  83. #endif
  84. #ifdef CONFIG_EFI_LOADER
  85. /*
  86. * EFI will reserve 64kb for its runtime services. This will probably
  87. * overlap with our spin table code, which is why we have to relocate
  88. * it.
  89. * Keep this after the __real_cntfrq update, so we have it when we
  90. * copy the complete section here.
  91. */
  92. ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
  93. EFI_RESERVED_MEMORY_TYPE,
  94. efi_size_in_pages(secondary_boot_code_size),
  95. &reloc_addr);
  96. if (ret == EFI_SUCCESS) {
  97. debug("Relocating spin table from %llx to %llx (size %lx)\n",
  98. (u64)secondary_boot_code_start, reloc_addr,
  99. secondary_boot_code_size);
  100. memcpy((void *)reloc_addr, secondary_boot_code_start,
  101. secondary_boot_code_size);
  102. flush_dcache_range(reloc_addr,
  103. reloc_addr + secondary_boot_code_size);
  104. /* set new entry point for secondary cores */
  105. secondary_boot_addr += (void *)reloc_addr -
  106. secondary_boot_code_start;
  107. flush_dcache_range((unsigned long)&secondary_boot_addr,
  108. (unsigned long)&secondary_boot_addr + 8);
  109. /* this will be used to reserve the memory */
  110. secondary_boot_code_start = (void *)reloc_addr;
  111. }
  112. #endif
  113. cores = cpu_mask();
  114. /* Clear spin table so that secondary processors
  115. * observe the correct value after waking up from wfe.
  116. */
  117. table = get_spin_tbl_addr();
  118. memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  119. flush_dcache_range((unsigned long)table,
  120. (unsigned long)table +
  121. (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  122. debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
  123. #ifdef CONFIG_FSL_LSCH3
  124. gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
  125. gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
  126. svr = gur_in32(&gur->svr);
  127. ver = SVR_SOC_VER(svr);
  128. if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
  129. gur_out32(&gur->scratchrw[6], 1);
  130. asm volatile("dsb st" : : : "memory");
  131. rst->brrl = cores;
  132. asm volatile("dsb st" : : : "memory");
  133. } else {
  134. /*
  135. * Release the cores out of reset one-at-a-time to avoid
  136. * power spikes
  137. */
  138. i = 0;
  139. cluster = in_le32(&gur->tp_cluster[i].lower);
  140. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  141. type = initiator_type(cluster, j);
  142. if (type &&
  143. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  144. cluster_cores++;
  145. }
  146. do {
  147. cluster = in_le32(&gur->tp_cluster[i].lower);
  148. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  149. type = initiator_type(cluster, j);
  150. if (type &&
  151. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  152. wake_secondary_core_n(i, j,
  153. cluster_cores);
  154. }
  155. i++;
  156. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  157. }
  158. #elif defined(CONFIG_FSL_LSCH2)
  159. scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
  160. scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
  161. asm volatile("dsb st" : : : "memory");
  162. gur_out32(&gur->brrl, cores);
  163. asm volatile("dsb st" : : : "memory");
  164. /* Bootup online cores */
  165. scfg_out32(&scfg->corebcr, cores);
  166. #endif
  167. /* This is needed as a precautionary measure.
  168. * If some code before this has accidentally released the secondary
  169. * cores then the pre-bootloader code will trap them in a "wfe" unless
  170. * the scratchrw[6] is set. In this case we need a sev here to get these
  171. * cores moving again.
  172. */
  173. asm volatile("sev");
  174. while (timeout--) {
  175. flush_dcache_range((unsigned long)table, (unsigned long)table +
  176. CONFIG_MAX_CPUS * 64);
  177. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  178. if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  179. SPIN_TABLE_ELEM_STATUS_IDX])
  180. cpu_up_mask |= 1 << i;
  181. }
  182. if (hweight32(cpu_up_mask) == hweight32(cores))
  183. break;
  184. udelay(10);
  185. }
  186. if (timeout <= 0) {
  187. printf("CPU: Failed to bring up some cores (mask 0x%x)\n",
  188. cores ^ cpu_up_mask);
  189. return 1;
  190. }
  191. printf("CPU: %d cores online\n", hweight32(cores));
  192. return 0;
  193. }
  194. int is_core_valid(unsigned int core)
  195. {
  196. return !!((1 << core) & cpu_mask());
  197. }
  198. static int is_pos_valid(unsigned int pos)
  199. {
  200. return !!((1 << pos) & cpu_pos_mask());
  201. }
  202. int is_core_online(u64 cpu_id)
  203. {
  204. u64 *table = get_spin_tbl_addr();
  205. int pos = id_to_core(cpu_id);
  206. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  207. return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
  208. }
  209. int cpu_reset(u32 nr)
  210. {
  211. puts("Feature is not implemented.\n");
  212. return 0;
  213. }
  214. int cpu_disable(u32 nr)
  215. {
  216. puts("Feature is not implemented.\n");
  217. return 0;
  218. }
  219. static int core_to_pos(int nr)
  220. {
  221. u32 cores = cpu_pos_mask();
  222. int i, count = 0;
  223. if (nr == 0) {
  224. return 0;
  225. } else if (nr >= hweight32(cores)) {
  226. puts("Not a valid core number.\n");
  227. return -1;
  228. }
  229. for (i = 1; i < 32; i++) {
  230. if (is_pos_valid(i)) {
  231. count++;
  232. if (count == nr)
  233. break;
  234. }
  235. }
  236. if (count != nr)
  237. return -1;
  238. return i;
  239. }
  240. int cpu_status(u32 nr)
  241. {
  242. u64 *table = get_spin_tbl_addr();
  243. int pos;
  244. if (nr == 0) {
  245. printf("table base @ 0x%p\n", table);
  246. } else {
  247. pos = core_to_pos(nr);
  248. if (pos < 0)
  249. return -1;
  250. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  251. printf("table @ 0x%p\n", table);
  252. printf(" addr - 0x%016llx\n",
  253. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
  254. printf(" status - 0x%016llx\n",
  255. table[SPIN_TABLE_ELEM_STATUS_IDX]);
  256. printf(" lpid - 0x%016llx\n",
  257. table[SPIN_TABLE_ELEM_LPID_IDX]);
  258. }
  259. return 0;
  260. }
  261. int cpu_release(u32 nr, int argc, char *const argv[])
  262. {
  263. u64 boot_addr;
  264. u64 *table = get_spin_tbl_addr();
  265. int pos;
  266. pos = core_to_pos(nr);
  267. if (pos <= 0)
  268. return -1;
  269. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  270. boot_addr = simple_strtoull(argv[0], NULL, 16);
  271. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
  272. flush_dcache_range((unsigned long)table,
  273. (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
  274. asm volatile("dsb st");
  275. /*
  276. * The secondary CPUs polling the spin-table above for a non-zero
  277. * value. To save power "wfe" is called. Thus call "sev" here to
  278. * wake the CPUs and let them check the spin-table again (see
  279. * slave_cpu loop in lowlevel.S)
  280. */
  281. asm volatile("sev");
  282. return 0;
  283. }